An instrumentation amplifier (INA) preserves microvolt-to-millivolt bridge signals in the presence of large common-mode noise, cable-coupled EMI, and drift—by rejecting common-mode content while applying a stable, settable gain.

When an INA is the right tool

• Bridge output is tiny (mV-level differential) while the system environment injects large common-mode content (ground offsets, mains pickup, switching noise).
• Cables/connectors are unavoidable, and readings change when the cable is moved, touched, or routed near power electronics—classic EMI → common-mode → differential conversion.
• Zero shifts with temperature or warm-up, even when the sensor is stable—drift, bias/leakage, and self-heating become comparable to the signal.
• CMRR looks “good on paper”, but the board shows hum or random steps—often a sign that symmetry was broken by filtering, protection, or layout parasitics.

What an INA buys—only if the design is done correctly

• High CMRR: rejects common-mode pickup (mains, switching, ground offsets). Common failure path: any asymmetry (RC/ESD/layout) converts common-mode into a false differential signal.
• Settable gain: lifts mV-level bridge signals into a usable measurement range. Common failure path: gain interacts with headroom and settling—clipping or slow recovery can look like “sensor drift.”
• Symmetric input behavior: enables robust protection and EMI filtering while keeping the differential path balanced. Common failure path: one-sided clamps/caps destroy balance and reduce AC CMRR.

Practical takeaway: many “INA noise problems” are not random noise; they are CMRR collapse caused by broken symmetry in the analog front-end.

What this page delivers

• A selection field list (CMRR DC/AC, input CM range, noise & drift, bias/leakage, output swing, EMI/ESD robustness).
• A noise/accuracy budgeting path that maps bridge impedance and target resolution to INA requirements.
• A symmetry-first approach for protection and EMI filtering that preserves AC CMRR.
• A verification checklist (CMRR checks, temperature/warm-up drift, step response, basic EMI sanity tests).

Rule of thumb: choose the device category based on the dominant failure mode. If common-mode pickup, ground offsets, or cable EMI dominate, an INA is usually the most reliable path to stable measurements.

Strengths and the most common ways designs fail

Practical conditions that strongly favor an INA

• The sensor is remote (cable/connector), and ground potential differences cannot be guaranteed.
• The environment contains mains pickup or switching power noise that enters as common-mode.
• The signal is small and accuracy is limited by CMRR, drift, and symmetry rather than by raw gain.

Scope boundaries (what belongs on sibling pages)

• Digitally controlled gain, mux, multi-range: see the PGA page.
• High-side current sensing / wide CM monitoring: see High-Side / Differential Amplifier.
• Deep dive into chopper artifacts / 0.1–10 Hz optimization: see Low-Offset / Zero-Drift.
• Bridge excitation and ratiometric system design: see Bridge AFE Amplifier.

High CMRR is not “magic inside the chip”; it comes from how differential gain is formed while common-mode paths stay balanced across temperature, frequency, and layout parasitics.

3-op-amp vs 2-op-amp INA: what changes in real designs

• Input impedance and source interaction: bridge sensors prefer a front-end that does not load or unbalance the bridge. Architectures that keep input currents and impedance symmetric reduce “mystery” offsets and drift with cable motion.
• CMRR resilience: the easiest way to lose CMRR is to let common-mode see a different impedance on the “+” and “−” sides. Architectures that separate differential gain formation from common-mode behavior are generally more tolerant to front-end add-ons.
• Bandwidth, phase margin, and settling: architecture determines where dominant poles live and how much “room” exists for input filtering and protection. What looks stable at low gain can become sensitive once gain is increased and headroom shrinks.
• System integration tolerance: the practical choice is often the one that stays predictable after adding real-world necessities (connectors, RC filtering, ESD clamps, and imperfect layout symmetry).

Why matched resistor networks beat discrete resistors for CMRR

• Ratio accuracy matters more than absolute tolerance: common-mode cancellation depends on resistor ratios. Even “good” discrete parts can drift apart under gradients, breaking ratio balance.
• Thermal coupling keeps ratios stable: integrated networks track temperature together, so ratios stay consistent during warm-up and airflow changes.
• Parasitics are more symmetric: internal routing and parasitic capacitances are better controlled, improving AC CMRR compared to board-level, layout-dependent parasitics.
• Board repeatability improves: channel-to-channel variation shrinks when the most CMRR-critical matching is not delegated to layout and BOM scatter.

Practical hook for later sections: DC CMRR follows ratio matching; AC CMRR follows symmetry of parasitics.

Early warning: protection and EMI filtering can destroy symmetry

• Symmetry rule: anything added on one input must be mirrored on the other (series R, shunt C, clamps). Otherwise, common-mode turns into a false differential signal.
• Placement rule: the closer the parts are to the connector, the more important symmetry becomes (cable EMI excites the imbalance directly).
• Failure signature: mains hum, cable-touch sensitivity, or fixed spurs appear even when the sensor is stable—often “looks like noise” but is actually CMRR collapse.

CMRR is not a single datasheet number. It is a layered property shaped by resistor ratio matching (DC), parasitic symmetry (AC), and system-level common-mode to differential conversion (cables, shielding, and return paths).

A practical 3-layer model for “where CMRR is lost”

“Looks like noise” symptoms that often indicate CMRR collapse

• Strong 50/60 Hz or narrowband spur: frequently points to Layer 2/3 imbalance (input network or shield/return path).
• Readings change when cable routing changes: often Layer 3 (CM injection through shield/return), amplified by any front-end asymmetry.
• Channel-to-channel mismatch on the same PCB: often Layer 2 (layout parasitic mismatch or “one extra clamp/cap” on one channel).
• Worse behavior at higher gain: CMRR margins shrink and headroom becomes tighter; Layer 1 + Layer 2 issues become more visible.

Gain is a four-way trade: bandwidth, stability margin, noise mapping, and settling time. Set RG with the final sampling or control timing in mind, then add input filtering without breaking symmetry.

What RG changes (rules that match bench behavior)

• Gain ↑ → usable bandwidth ↓: higher closed-loop gain typically reduces bandwidth, making the chain slower to track fast events and more sensitive to low-frequency interference.
• Gain ↑ → stability margin becomes more fragile: added poles from RC filters, cable capacitance, or protection networks can consume phase margin and cause ringing or marginal oscillation.
• Gain ↑ → settling time requirement becomes harder: the last fraction of a percent is what matters for precision sampling; a waveform can look “close enough” on a scope while still being wrong at the sampling instant.
• Gain changes noise mapping: raising gain can help lift signal above downstream noise, but it also amplifies any front-end imbalance and increases sensitivity to CM→Diff conversion.

Input RC filtering: EMI benefit without CMRR or stability collapse

• Symmetry first: series resistors, shunt capacitors, and clamps must be mirrored on “+” and “−” so common-mode does not become a false differential signal.
• Filter goal: suppress RF and fast edge pickup while keeping the amplifier loop stable; “stronger filtering” is not better if it adds phase lag and ringing.
• Placement intent: parts near the connector act like an EMI fence; parts near the INA behave like loop-shaping elements. Both locations require symmetry, but the failure signatures differ.
• Bench signature: if only certain RC values cause oscillation or large overshoot, the dominant issue is usually phase margin reduction rather than random noise.

Settling and overshoot: how they masquerade as “noise” or “drift”

• Ringing → sample-to-sample variation: if sampling lands on different phases of a ring, the result looks like noise even with a stable sensor.
• Incomplete settling → apparent offset: residual error can be mistaken for a sensor bias shift, especially after steps, multiplexer changes, or cable disturbances.
• High gain amplifies the problem: headroom and phase margin shrink, so overload recovery and tiny imbalances become more visible.

Interaction note: precision sampling depends on consistent settling at the sampling instant; driver and sampling-network details belong on ADC driver pages.

A quick, repeatable way to pick RG and input RC

1. Define the signal bandwidth and the timing window that must be met (sampling or control).
2. Reserve settling and headroom margin for worst-case temperature, cable, and interference.
3. Select RG so closed-loop bandwidth and phase margin remain comfortable at the target gain.
4. Add input RC to knock down EMI, keeping mirror symmetry and verifying that ringing does not return.

Input common-mode range (ICMR) and output swing are coupled constraints. High gain shrinks the safe operating window, so “RRIO” alone does not guarantee linear behavior near the rails.

The most common traps in single-supply bridge front-ends

• RRIO is conditional: rail-to-rail performance depends on load, output current, and temperature; “near-rail” behavior can degrade at high gain.
• ICMR is not the supply rails: it is the window where the input stage remains linear; ground offsets and EMI can push CM outside that window.
• Overload recovery matters: once the output hits a rail, recovery can be slow and looks like drift or random steps in measured data.

Think in windows: input CM window + output swing window

• Input CM window (ICMR): the bridge common-mode point must stay inside the linear input region under worst-case temperature, ground shifts, and coupled interference.
• Output swing window: the amplified signal plus offset and drift must remain inside the output linear region under worst-case load and supply tolerance.
• High gain reduces margin: the same CM disturbance or offset that is harmless at low gain can cause clipping at high gain.

Bridge common-mode point: placement principles that prevent rail hits

• Keep CM away from ICMR edges: reserve margin for warm-up drift, airflow changes, and interference that moves the CM point.
• Center the output in the swing window: bias the output so both signal excursions and errors (offset/drift) have headroom.
• Account for ground movement: remote sensors and shields can shift the effective CM reference; margin is required even if DC checks pass.

System-level excitation and ratiometric details belong on bridge AFE pages; this section focuses on avoiding ICMR and swing violations in INA front-ends.

Two-minute headroom self-check (before layout and EMI testing)

1. Verify the bridge CM point stays within ICMR at worst-case temperature and ground shift.
2. Verify the output remains within linear swing at maximum gain, including offset, drift, and expected interference.
3. If clipping is possible, assume slow recovery and measurement artifacts; reduce gain or re-bias to increase margin.
4. Re-check with cable and protection networks included (they can shift CM and load the output).

Bridge signals are small; the noise budget sets the real limit long before “more gain” helps. Use RTI/OTI to compare noise sources on one scale, then map the total to the resolution target.

RTI vs OTI: the only way to compare apples to apples

• RTI (referred-to-input): every noise contribution is translated back to the bridge input, answering “how much input noise is allowed” for the target performance.
• OTI (referred-to-output): noise is expressed at the amplifier output, answering “how much output noise will the ADC or next stage see.”
• Practical rule: pick one reference (RTI is usually the most intuitive), do the full budget there, then convert to OTI only at the end.

en, in, and bridge impedance: which term dominates depends on the source

• Bridge thermal noise is always present: it grows with measurement bandwidth and is set by the bridge’s effective resistance seen at the input.
• Voltage noise (en) dominates more often with low-to-moderate source impedance: when the source impedance is not large, en tends to be the amplifier term that sets the floor.
• Current noise (in) becomes critical as source impedance rises: in flowing through source impedance produces an equivalent voltage noise that can quickly overtake en.
• Symmetry still matters: any impedance mismatch between “+” and “−” converts common-mode interference into differential error that behaves like extra noise.

Design hook: treat bandwidth as the first “noise switch.” Tightening the effective bandwidth often improves the total noise more reliably than chasing a slightly lower en spec.

A repeatable RTI noise budget workflow (no long derivations required)

1. Define the effective measurement bandwidth (signal band plus any averaging/filtering strategy).
2. List noise sources: bridge thermal, INA en, INA in, excitation/reference, and ADC (quantization and/or input noise).
3. Translate each contribution to RTI so all terms share the same reference point.
4. Convert density to RMS within the bandwidth for each term (bandwidth sets the total more than tiny density differences).
5. Combine RMS terms using root-sum-square to get total RTI noise, then multiply by gain to estimate OTI.
6. Verify that the resulting output noise and peaks remain inside headroom and do not trigger overload recovery.

Mapping the budget to an ADC target (path only, not driver design)

• Start from the measurement goal (stable resolution or effective bits) and translate it into an allowable input-referred RMS noise in the signal band.
• Compare allowable RTI noise to the combined RTI budget; if margin is negative, reduce bandwidth, improve the dominant noise term, or change the bridge impedance strategy.
• Keep ADC contributions as one line item in the RTI list; sampling-network and driver specifics belong on ADC driver pages.

For bridge measurements, DC accuracy is set by offset/drift and low-frequency noise more than midband specs. Warm-up and thermal gradients often dominate real-world stability.

A practical DC-accuracy “metric tree”

• Offset: the initial zero error at a defined condition (supply, temperature, load).
• Drift: how offset changes with temperature and time; gradients and self-heating matter as much as ambient temperature.
• 0.1–10 Hz noise: low-frequency wander that directly appears as “readout jitter” in weighing and pressure systems.
• Warm-up behavior: time-dependent drift after power-on as the front-end reaches thermal equilibrium.

Offset and drift: the paths that matter on real PCBs

• Thermal gradients create mismatch: when “+” and “−” paths sit at different temperatures, ratio balance degrades and offset moves even if the sensor is stable.
• Package and nearby heat sources shape the curve: LDOs, DC/DCs, and processors can heat one side of the front-end and create repeatable drift patterns.
• Airflow and touch sensitivity are clues: if readings change with airflow, enclosure state, or hand proximity, gradients—not random noise—are usually the root cause.

Bias current and leakage: hidden DC errors in high-impedance bridges

• Input bias current creates voltage drops: any series/filter resistance at the input turns bias current into differential offset.
• Asymmetry magnifies the problem: unequal input resistances or leakage paths convert a common-mode condition into differential error.
• Temperature dependence is often the real culprit: leakage typically increases with temperature, making bias-related offset appear as drift.

0.1–10 Hz noise and warm-up: how to plan stability, not just measure it

• Low-frequency noise sets “readout jitter”: wideband noise can be averaged down; 0.1–10 Hz wander often remains visible in stable loads.
• Warm-up is a system requirement: specify a warm-up interval until the drift slope reaches a steady region, and align that interval with production and field usage.
• Temperature steps must be tested separately: a sudden ambient change produces a different drift shape than power-on warm-up.

A simple verification plan that prevents “it drifts” surprises

1. Record the power-on drift curve until it reaches a stable region; define the warm-up requirement from that curve.
2. Repeat with controlled airflow changes to reveal gradient sensitivity.
3. Apply a temperature step (or enclosure open/close) and record the ambient drift response separately.
4. Log offset and drift statistics for binning and production feedback loops.

Protection and EMI filtering are not “free.” Any asymmetry converts common-mode interference into a false differential signal, collapsing AC CMRR and showing up as noise, drift, or random jumps.

What this section prevents in real installations

• Long cables that pick up RF and fast edges.
• ESD/EFT events that pass compliance but still disturb readings.
• Surge and hot-plug transients that stress input structures and shift the apparent zero.

The protection trio: series limiting, clamps, and TVS (use + side effects)

• Series limiting resistors (R): reduce transient current and tame cable-induced spikes. Side effects include added thermal noise, extra poles with input capacitance, and CM→Diff conversion if values or placement are not mirrored.
• Input clamps: steer overvoltage away from sensitive input structures. Side effects include non-linear junction capacitance and leakage that can be temperature-dependent; clamp return paths must be short and consistent to avoid injecting noise into the reference.
• TVS devices: absorb large ESD/surge energy before it enters the PCB. Side effects include significant capacitance; if only one side is protected or if return loops differ, AC CMRR can collapse immediately.

EMI symmetry rules (the checklist that keeps CM as CM)

• Differential symmetry: identical topology, values, and placement on “+” and “−”.
• Shunt-to-ground symmetry: if shunt capacitors/RC exist, both sides must see the same reference point and the same return impedance.
• Routing symmetry: same layer, same reference plane, same via count, and the same proximity to aggressors.
• Return-path symmetry: clamp and TVS currents must return in a controlled way that does not flow through sensitive measurement references.

Common failure patterns that look like “noise” but are really CMRR collapse

• One-sided capacitor or clamp: RF becomes differential error and spikes appear as random jumps.
• Matched values, mismatched grounding: both sides have caps, but returns land differently, so symmetry is still broken.
• TVS placed far from connector: energy enters the board, exciting internal loops and shifting apparent offset.
• Cable-dependent ringing: certain cable lengths or RC values trigger overshoot because phase margin was reduced by the protection network.

Minimal robustness checklist (fast to review before a prototype build)

1. Verify “+” and “−” networks are mirror images (values, topology, placement).
2. Place TVS at the connector with the smallest possible current loop.
3. Ensure clamp/TVS return currents avoid sensitive reference nodes.
4. Re-check symmetry through vias and reference transitions (same layer and reference plane whenever possible).

Datasheet CMRR is only a starting point. PCB symmetry, reference continuity, and controlled return paths decide whether common-mode interference stays common-mode from the connector to the INA pins.

Layout goals that preserve CMRR

• Make “+” and “−” see the same coupling environment (equal coupling).
• Keep both lines on the same layer and reference plane (equal reference).
• Keep return and shield currents out of sensitive references (equal return control).

Differential input routing: symmetry is more than “equal length”

• Same layer, same plane: do not split “+” and “−” across layers or reference planes unless absolutely required.
• Equal coupling: avoid placing one trace near noisy copper or edges while the other runs through a quiet corridor.
• Equal via count: vias add parasitics; unequal via usage is a direct symmetry break at high frequency.

Reference continuity: split planes are a common CMRR killer

• Avoid routing the input pair across plane gaps; return paths detour and become asymmetric.
• If a transition is unavoidable, route both lines together with the same geometry and reference transition.
• Keep the connector-to-INA segment over a solid reference plane whenever possible.

Ground and shield strategy: principles that protect the measurement reference

• Single-point bonding often helps control low-frequency ground-loop risk.
• Multi-point bonding can improve high-frequency shielding continuity in harsh RF environments.
• Regardless of the choice, ensure shield currents do not return through sensitive measurement references; keep the shield return controlled and physically separated.

Guarding: when it helps and when it hurts

• Useful for high-impedance inputs and environments with moisture/contamination that create surface leakage.
• Must be symmetric: guard geometry and reference must be consistent around “+” and “−”.
• Common failure: tying guard to a noisy reference injects interference directly into the sensitive input neighborhood.

Connector to INA: the shortest symmetric path wins

• Keep the pair short, parallel, and away from fast digital edges.
• Mirror any protection/filter elements and keep placement symmetric.
• Avoid mid-route branching, layer swapping, or one-sided detours that create unequal parasitics.

If it isn’t checked or measured, it isn’t a specification. This section turns CMRR, headroom, bandwidth/settling, noise, drift, and EMI robustness into a repeatable review-and-test flow that teams can run without guesswork.

How to use this checklist

• Design review (before layout freeze): eliminate symmetry and headroom traps on paper.
• Bench verification (first bring-up): measure CMRR, settling, and drift using minimal fixtures.
• Production logging: store gain/bias/temp points and drift statistics for binning and feedback loops.

Design review checklist — P0 (highest priority)

1. Input symmetry (RC / clamps / routing): “+” and “−” must be mirror images (same topology, values, placement, layer, and via count). Any one-sided capacitor or clamp is a direct CM→Diff converter.
2. ICMR and output headroom margin: confirm the bridge common-mode point stays inside the input common-mode range across supply tolerance, temperature, and ground shifts; verify output swing has margin at max gain without hitting saturation or overload recovery.
3. Protection side effects are budgeted: TVS/clamp capacitance, leakage, and return paths are reviewed as part of AC CMRR and drift risk—not treated as “free protection.”

Design review checklist — P1 (performance closure)

1. RG, bandwidth, and settling: gain setting is reviewed together with closed-loop bandwidth, phase margin, and settling time. Input RC filters must remain symmetric and must not push the loop into ringing or long tails.
2. Noise budget mapped to resolution (RTI): define the effective bandwidth (including averaging/filtering), compute input-referred RMS noise, identify the dominant contributor (bridge thermal, en, in, reference/excitation, ADC), and confirm margin to the stability goal.
3. Layout “last mile” checks: connector-to-INA path is the shortest symmetric route; reference planes are continuous (avoid gaps); shield currents are kept out of sensitive measurement references.

Design review checklist — P2 (reliability and production readiness)

• Warm-up time is defined: stability requirements include time-to-steady after power-on.
• Temperature plan exists: at least room + hot/cold sampling strategy is documented.
• Guarding is justified: used only for high-impedance/leakage risk, and implemented symmetrically with a clean reference.

Verification test checklist (bench, temperature, EMI)

Production logging fields (for binning and feedback)

• Identity: SN, lot, date/time, fixture ID, operator.
• Conditions: temperature point, supply, excitation/reference mode, gain setting (RG or gain code), input bias mode.
• DC metrics: offset (fixed reference convention), drift window and slope, warm-up time-to-steady.
• Noise metrics: 0.1–10 Hz noise result with measurement duration/window documented.
• CMRR: DC and selected frequency spot checks, with the same fixture definition used across builds.
• Disposition: pass/fail code plus a root-cause tag set (symmetry, headroom, settling, drift, EMI sensitivity).

Reference BOM snippets (example part numbers for prototypes)

Scope: bridge-based strain and pressure sensing only (mV-level differential signals). This section focuses on INA placement, long-cable failure modes, and a field-driven selection flow. Excitation systems, ratiometric AFE details, and integrated bridge AFE architectures belong in the Bridge AFE page.

Application pattern A — quarter/half/full bridge (INA-view only)

• Bridge output is small: mV/V-level differential signals push the system limit toward noise, drift, and common-mode rejection long before “gain” is the problem.
• INA decision points: required gain range, input common-mode point (bridge midpoint bias), and output headroom margin at max load and temperature.
• Excitation mention (point only): excitation noise can modulate directly into measurement error; selection must ensure ICMR and output swing remain safe under real excitation and ground conditions.

Application pattern B — remote sensor, long cable, and ground potential differences

• Long cables amplify risk: RF pickup, fast transient coupling (ESD/EFT), and ground shifts become normal operating conditions.
• Primary failure mode: any asymmetry in protection, filtering, or routing converts common-mode interference into a false differential signal (AC CMRR collapse).
• INA value: high CMRR (DC and AC) only matters when the external network and PCB preserve symmetry and controlled return paths.

Application pattern C — multi-channel bridges (consistency and thermal coupling)

• Consistency is often DC-limited: channel mismatch is frequently offset/drift/bias leakage, not random noise.
• EMI sensitivity differences: one channel being “worse” usually points to symmetry breaks (layout/protection) and different AC CMRR behavior.
• Selection focus: drift distribution, warm-up behavior, and bias/leakage versus temperature matter as much as typical specs.

Core selection fields (turn requirements into datasheet columns)

• CMRR (DC + AC): treat AC CMRR as a first-class spec for long cables; one “CMRR @ DC” number is not enough.
• Gain range and gain-setting method: confirm gain covers bridge output; evaluate how RG choices affect bandwidth and settling.
• ICMR and output swing: ensure common-mode bias and output headroom stay safe across supply tolerance and temperature.
• Noise (0.1–10 Hz + wideband): 0.1–10 Hz noise dominates “stable reading” perception in weigh/pressure systems.
• Offset and drift: look for max/limits and temperature behavior; typical values alone do not close risk.
• Input bias current / leakage: impacts high-Z bridges and any input series resistance or filtering networks.
• Bandwidth / settling time: must fit the system timing window; confirm test conditions for settling specs.
• EMI/ESD notes: prefer devices with clear guidance on symmetric protection/filtering and return-path control.
• Temperature grade + package thermal: self-heating and thermal gradients directly translate into drift and channel-to-channel bias.

Risk mapping (symptom → likely drivers → what to prioritize)

• Reading slowly drifts (minutes to hours): drift, warm-up behavior, self-heating, bias/leakage.
  Prioritize: drift vs temperature, warm-up time-to-steady, bias/leakage vs temperature, thermal/package notes.
• 50/60 Hz or common-mode interference dominates: AC CMRR degradation, symmetry breaks, return-path imbalance.
  Prioritize: CMRR vs frequency curve, recommended symmetric RC/clamp topology, layout symmetry constraints.
• Ringing or slow recovery with certain cable/RC choices: settling and stability interaction with the input network.
  Prioritize: settling conditions, stability guidance, input RC limitations, overload recovery behavior if available.
• High gain clips or “sticks” near rails: ICMR and output swing margins, overload recovery traps.
  Prioritize: ICMR limits, output swing vs load/supply, recovery characteristics under saturation.
• Multi-channel mismatch under the same conditions: offset/drift distribution, bias differences, thermal gradients.
  Prioritize: drift distribution/histograms, channel consistency notes, package thermal behavior and symmetric layout.
• ESD/EFT passes but readings become unstable: protection return paths, clamp leakage, TVS capacitance and asymmetry.
  Prioritize: application notes for input protection, symmetry rules, and post-stress behavior guidance.

Practical shortlist buckets (pick the risk driver first)

Vendor inquiry template (copy/paste request list)

• CMRR vs frequency curve: within the intended measurement bandwidth and key EMI-relevant points.
• Offset/drift distribution: histogram or limits across temperature (not only typical values).
• 0.1–10 Hz noise conditions: measurement window, gain, filtering, and test setup assumptions.
• Bias/leakage vs temperature: especially for high-Z bridges or when series resistors are used.
• Output swing vs load/supply: single-supply headroom behavior at maximum gain.
• Settling time conditions: step amplitude, gain, load, and input network assumptions.
• EMI/ESD notes: recommended symmetric protection/RC topology and return-path guidance.
• Temperature grade and package notes: thermal behavior, warm-up guidance, and production considerations.

Missing curves or distributions shift risk onto the system. Treat the absence of these materials as a selection penalty for long-cable and multi-channel projects.

Reference shortlist (example part numbers)