Audio Master Clocks: MCLK/BCLK/LRCK & ASRC/PLL
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Audio master clocks are not just “low phase noise”—they are a system timing contract that defines who is master, how MCLK/BCLK/LRCK stay coherent, and how switching/async inputs avoid pops, drift, and channel skew. This page turns that contract into an engineering checklist: frequency-family math, jitter impact, ASRC/PLL cooperation, distribution/layout rules, and measurable bring-up tests.
What “Audio Master Clock” means in real systems (MCLK/BCLK/LRCK)
In audio hardware, the “master” is the device that ultimately defines the sampling timebase (Fs) and enforces valid timing relationships across MCLK, BCLK, and LRCK/FSYNC. Labels alone are not enough—what matters is ownership: who drives each clock, who follows, and which block absorbs mismatch during rate changes and drift.
The three clocks: roles & what breaks first
MCLK (Master clock)
- Defines the reference for internal oversampling / digital filters / internal PLLs (codec- or SoC-dependent).
- Wrong range or unstable source often shows up as PLL unlock, long relock, or rate-change pops.
BCLK (Bit clock)
- Sets the serial transport rate for I²S/TDM: bits per slot × slots per frame × Fs.
- Mismatch typically causes data corruption, channel slip, intermittent clicks, or frame errors.
LRCK / FSYNC (Frame / sample clock)
- Marks the audio frame boundary and usually equals Fs.
- Wrong frequency or illegal transition sequence causes rate mismatch, pitch/tempo errors, or pops at switching.
Common ownership topologies (who drives what)
Codec as master
- Codec drives BCLK/LRCK; SoC/DSP follows the audio timebase.
- Best when codec dictates stable local audio timing and the rest is a client.
- Risk: awkward system-wide sync; rate changes must be carefully sequenced.
SoC/DSP as master
- SoC drives BCLK/LRCK (and often provides MCLK); codec follows.
- Best when the platform controls multi-stream routing and timing policy.
- Risk: wrong slot math or switching order causes pops/clicks and data slip.
External master clock module
- Dedicated clock source defines MCLK; downstream blocks derive or lock as needed.
- Best when low phase noise and consistent timing across devices are priorities.
- Risk: distribution/skew and supply coupling can destroy “spec-level” clock quality.
Quick checks before blaming jitter
- Confirm ownership in register/device-tree: exactly one block drives each of BCLK and LRCK.
- Verify LRCK frequency equals the intended Fs and stays stable through rate changes.
- Verify BCLK matches the configured slot width and slot count (not just “sample bit depth”).
- Avoid illegal windows during switching: do not let the system present an unsupported MCLK:Fs ratio even for a short transient.
Boundary note: protocol edge-level timing (I²S/LJ/RJ/TDM details) and PN/jitter integration math belong to dedicated pages; this section focuses on ownership and valid relationships.
Clock relationships you must get right: sample-rate families, ratios, and frame math
Audio clocking fails in predictable ways: wrong family support (44.1k vs 48k), invalid MCLK:Fs ratios during switching, or BCLK math that ignores slot width and channel count. The goal is to make every rate change and every format change remain inside supported timing envelopes.
Two sample-rate families (do not mix by accident)
- 44.1k family: 44.1 / 88.2 / 176.4 kHz (common root: 22.5792 MHz).
- 48k family: 48 / 96 / 192 kHz (common root: 24.576 MHz).
- If both families must be supported, the clock-source strategy must be explicit (dual roots, programmable source, or synthesis). Avoid “almost works” configurations that only fail on one family.
MCLK:Fs ratios (256fs / 384fs / 512fs) — selection logic
Rule 1: obey the codec’s allowed envelope
Lock reliability and clean switching are determined by whether the codec/SoC supports the ratio and the transition sequence. A “fast” MCLK is not automatically safer.
Rule 2: higher MCLK increases board-level risks
Higher frequency increases edge-rate coupling, EMI, and distribution difficulty. It can also amplify sensitivity to supply noise and layout return-path issues.
Rule 3: choose the smallest “safe” ratio
Start with the most common supported ratio (often 256fs), validate switching stability, then raise only if a specific device requirement demands it.
Frame math for BCLK (I²S / TDM): use slot width, not just bit depth
BCLK formula (engineering form)
BCLK = Fs × BitsPerSlot × SlotsPerFrame
- BitsPerSlot is often 32 even for 24-bit audio samples (padding is common).
- SlotsPerFrame is 2 for stereo I²S; it becomes N for TDM-N.
- Any mismatch between slot configuration and BCLK causes channel slip, intermittent artifacts, or frame errors.
Symptom map (fast isolation)
BCLK wrong
Channel slip, corrupted samples, intermittent clicks, or frame errors (often worsens with TDM/high channel count).
LRCK wrong or illegal switching order
Audible pops/clicks during rate change, pitch/tempo mismatch, repeated relock, or “works at 48k but fails at 44.1k”.
MCLK:Fs outside supported envelope
PLL unlock, long lock time, unreliable switching, or rare glitches that correlate with mode changes and temperature.
Practical tip: validate timing relationships first (families, ratios, slot math). “Low jitter” does not rescue an invalid relationship.
Quick BCLK examples (common configurations)
48 kHz • I²S stereo • 32-bit slot
BCLK = 48k × 32 × 2 = 3.072 MHz
48 kHz • TDM8 • 32-bit slot
BCLK = 48k × 32 × 8 = 12.288 MHz
44.1 kHz • I²S stereo • 32-bit slot
BCLK = 44.1k × 32 × 2 = 2.8224 MHz
These examples assume slot width equals 32 bits. If a platform uses 16-bit slots, the BCLK halves accordingly.
Where jitter actually hurts: DAC/ADC sensitivity and the “audible failure modes”
“Low phase noise” becomes engineering when it is tied to observable outcomes. Jitter can raise wideband noise, create discrete sidebands, worsen intermodulation, destabilize stereo imaging, or trigger pops during mode transitions. The first goal is to classify the symptom shape and identify the likely coupling path.
Scope boundaries (avoid false attribution)
- Analog degradation: noise floor rise, sidebands/spurs, IMD, stereo phase/image instability.
- Digital/format faults: slot math or ownership mistakes often cause clicks/dropouts that are not “clock quality” problems.
- Phase-noise integration windows and jitter metrics belong in Key Specs: Phase Noise & Jitter.
DAC view: timing error becomes noise / distortion
Engineering direction
Sampling-time uncertainty modulates the reconstructed waveform. The impact commonly appears as a higher noise floor, sidebands around tones, or degraded IMD.
Quick classification
- Wideband floor rise → random jitter or supply/EMI injection into clock paths.
- Discrete spurs/sidebands → PLL spurs, periodic supply ripple, or digital modulation.
Minimal test
Compare FFT at low vs high audio tones (e.g., 1 kHz vs 10–18 kHz). Track whether the issue follows tone frequency, mode switching, or power/EMI conditions.
ADC view: higher input frequency is more sensitive
Engineering direction
Sampling jitter creates an equivalent amplitude error that grows with input frequency. Even with a 20 kHz band limit, modulation and intermodulation can fold artifacts into the audible band.
Minimal test
- Hold amplitude constant; sweep tone up to 18–20 kHz.
- If high-frequency performance collapses first, prioritize clock/PLL reference paths and clock-supply isolation.
Common trap
A clean clock at the source can still fail at the endpoint if distribution return paths inject noise or create edge-related coupling into sensitive analog nodes.
Audible failure modes → first isolation step
Noise floor rise
Classify as wideband vs band-limited; correlate with PSU/EMI changes and clock distribution routing.
Sidebands / spurs
Check whether spurs move with Fs, tone frequency, or a switching frequency (PLL spur or power ripple signature).
IMD increase
Use 2-tone or multitone tests; isolate whether the effect follows clock paths or analog front-end loading.
Stereo image unstable
Look for channel-to-channel phase drift and skew; inspect fanout, skew control, and shared return paths.
Pops / clicks on switching
First rule out illegal ratio windows and buffer underflow/overflow; then investigate clock/PLL lock transitions.
Practical workflow: classify symptom shape → test correlation → lock the coupling path (source/PLL vs PSU/EMI vs distribution/return).
System architectures: synchronous islands vs asynchronous sources (USB/BT/Network)
Audio clocking becomes difficult when the system timebase is not unified. USB, Bluetooth, and network streams deliver data with their own timing behavior. A synchronous island (codec/DAC domain) requires consistent MCLK/BCLK/LRCK relationships, so an explicit boundary is required to absorb drift and short-term timing variation.
Define the domains (what must stay synchronous)
- Synchronous island: internal audio processing + codec/DAC running on a single Fs timebase with valid MCLK/BCLK/LRCK ratios.
- Asynchronous sources: USB/BT/network data arrival timing is not guaranteed to match the local Fs timebase over time.
“Who is the reference?” two practical strategies
Local audio is the master
Best local clock quality; requires ASRC and/or controlled buffering to match external stream rate without underflow/overflow.
Track external timebase
Improves system alignment with an external reference; requires PLL tracking and careful bandwidth choices to avoid importing external jitter.
Decision anchor: protect the synchronous island from uncontrolled drift while meeting end-to-end sync requirements.
Boundary building blocks (where failures show up)
ASRC
Converts from async stream timing to the local Fs domain; failures often appear as unexpected artifacts during transitions or misconfiguration.
PLL tracking (optional)
Pulls the local clock toward an external reference; failures show up as spurs/sidebands, slow lock, or instability under temperature and mode changes.
Elastic buffer / FIFO
Absorbs short-term rate differences; failures are clear: underflow/overflow → dropouts or repeated clicks.
Multi-device sync (short map, no protocol deep dive)
- Shared clock distribution: one master MCLK/LRCK distributed to multiple codecs/DACs (skew and return paths dominate outcomes).
- Master/slave chaining: one device drives BCLK/LRCK and others follow (simple, but topology-limited).
- External synchronization systems exist, but belong to dedicated timing/synchronization pages; this section focuses on the domain boundary concept.
Minimal verification: buffer occupancy stays centered over hours; rate switching produces no illegal ratio windows and no audible transients.
ASRC vs PLL: cooperation patterns that avoid pops, drift, and long relock
This is a system-control chapter. The goal is not “a better part,” but a stable architecture: asynchronous streams must cross a boundary without buffer runaway, audible transients, or repeated relock. Treat ASRC and PLL tracking as cooperating loops with clear ownership.
Responsibility split (make the system predictable)
ASRC
Converts an async data stream into the local Fs domain and absorbs short-term arrival variations without forcing the audio island to chase them.
PLL tracking
Pulls the local MCLK/Fs toward an external timebase (when required) and reduces long-term ppm drift that would otherwise push buffer occupancy to an edge.
Key rule: one loop handles long-term drift, the other handles short-term variability. Avoid “both chasing everything.”
Prefer ASRC when isolation is the priority
- Input is inherently async (USB/BT/network, multi-host streams).
- Local audio quality/stability must not depend on external timing quality.
- Frequent sample-rate switching must be smooth and predictable.
- Some latency is acceptable to keep the synchronous island coherent.
Typical failure signature
Pops during mode transitions usually point to switching state-machine issues (mute/settle/unmute) rather than “insufficiently low jitter.”
Prefer PLL tracking when external sync / low latency is required
- System must align to an external timebase (multi-device sync requirements).
- End-to-end latency budget is tight; large elastic buffering is undesirable.
- A stable external reference exists and the design can choose a conservative tracking behavior.
Typical failure signature
“Tracking too fast” imports external timing variability and can create jitter-shaped artifacts; “tracking too slow” causes buffer occupancy to drift to an edge.
Cooperation patterns (choose one, avoid control fights)
ASRC-only (local master)
Best isolation. External drift and burst variability are absorbed at the boundary; the synchronous island stays coherent.
PLL-only (track external)
Lowest architectural complexity for sync; requires careful tracking behavior to avoid importing external timing variability into MCLK.
PLL coarse + ASRC fine
PLL handles long-term ppm drift; ASRC absorbs residual short-term variability. Most robust when sync and stability must both be satisfied.
Control-fight warning: if buffer occupancy “breathes” aggressively around mid-level, the system is reacting to short-term jitter as if it were long-term drift.
Engineering criteria: map symptoms to “too fast / too slow”
Buffer drifts to overflow
Long-term ppm mismatch is not being corrected. Increase long-term tracking authority (ppm tracking) or add coarse PLL drift control.
Buffer oscillates / “breathes”
The control loop is too reactive. Reduce tracking bandwidth, increase smoothing, or widen the buffer window used by the controller.
Pops on switching
A state-machine issue: enforce mute → settle ratios/lock → unmute. Avoid reprogramming clocks during sensitive audio windows.
Long relock / slow recovery
Coarse/fine lock staging is too conservative or the reference is disturbed. Use staged locking and verify lock-detect thresholds and retry logic.
Knobs vs symptoms (no PLL math)
| Knob | Too large / too fast | Too small / too slow |
|---|---|---|
| PLL loop BW | Imports external timing variability; buffer “breathes” and artifacts become correlation-sensitive. | Slow drift correction; buffer occupancy trends toward an edge over time. |
| Buffer depth | Higher latency; switching becomes slower unless explicitly staged. | Underflow/overflow happens sooner; intermittent clicks appear first. |
| ppm tracking gain | Over-reacts to short-term variability; occupancy oscillation increases under bursty inputs. | Cannot remove long-term ppm mismatch; occupancy drifts toward overflow/underflow. |
| Smoothing / time constant | Too little smoothing behaves like “fast tracking” and amplifies burst jitter into control actions. | Too much smoothing delays drift correction; buffer trends slowly to an edge. |
| Switching state-machine | Reprogramming clocks during active audio windows → pops, partial frames, transient spurs. | Excessively slow staging → long mute time or “long relock” user experience. |
Note: PLL stability math and phase-noise integration are handled in the PLL / jitter-cleaning pages; this table only links knobs to field symptoms.
Choosing the clock source for audio: XO / TCXO / MEMS / programmable
Audio clock-source choice is driven by sample-rate family coverage, artifact risk (spurs/sidebands vs wideband floor), and real-world sensitivity to supply noise and mechanical coupling. Keep this section audio-specific and link generic oscillator taxonomy to the Reference Oscillators hub.
Frequency-family strategy (the first audio constraint)
Dual-XO
Two fixed references for 44.1k and 48k families. Simple, clean, predictable switching with a proper state-machine.
Programmable XO
Platform SKUs and flexible families. Must validate spur behavior and switching transients under real configuration flows.
Synthesis (PLL)
One reference generates multiple outputs. Favor staged lock and explicit spur checks; avoid reprogramming during active audio windows.
PN emphasis for audio (directional, not metrics math)
Closer-in behavior
More likely to appear as near-tone modulation or correlation-sensitive sidebands. Use tone tests to see whether artifacts sit close to the carrier.
Far-out behavior
More likely to raise wideband noise floor. Correlate with power/EMI and distribution return-path quality.
Metrics details and integration windows belong to the Key Specs pages; this section stays on “what shifts in the spectrum and why it matters.”
Supply / layout traps (audio failures often start here)
- Identical sources can measure differently on different boards: supply isolation and return paths can dominate endpoint cleanliness.
- Clock edges couple into sensitive analog nodes when the return path is forced through noisy regions or across plane gaps.
- Switching transients create pops when clocks are reprogrammed without a controlled mute/settle/unmute sequence.
Layout actions
Use a low-noise supply island, tight local decoupling, short clock routes, and continuous return paths; keep clocks away from high di/dt loops.
Mechanical coupling (when MEMS becomes a system choice)
- Vibration or shock can modulate some oscillator types and show up as correlation-sensitive sidebands.
- MEMS is often preferred in high-vibration platforms and field-deployed systems where robustness outranks absolute lowest PN.
- Placement and mechanical isolation can reduce modulation in sensitive builds.
Placement actions
Keep the clock source away from obvious vibration hotspots; avoid rigid coupling to high-energy actuators and fans.
Clock distribution for audio: fanout, levels, and avoiding skew-related channel artifacts
Multi-channel audio fails more often from distribution inconsistency than from the master source itself. Jitter tends to raise a noise/IM floor; skew and arrival-shape differences create channel-to-channel phase and imaging artifacts, and can make one endpoint “mysteriously worse.”
Topologies seen in audio boards (pick by predictability)
Point-to-point
Cleanest for one endpoint. Scaling to many endpoints becomes routing-heavy and fragile (length/return consistency becomes hard).
Star (fanout buffer)
Most predictable for multi-codec / multi-DAC sync. Each branch can be kept short and matched; skew is controlled by design instead of hope.
Daisy-chain
Simple routing, but it creates “sensitive nodes” (stubs, reflections, and endpoint-to-endpoint differences). One branch often becomes the “problem channel.”
Rule of thumb: if channel-to-channel consistency matters, use star fanout and match the electrical path, not just the drawn length.
How skew shows up (audible language ↔ measurable language)
Audible artifacts
- Imaging shifts (center image not stable or “pulls”)
- Phase-related timbre changes on stereo content
- Channel inconsistency that only appears at some sample rates
Measurable signatures
- Inter-channel phase difference vs frequency
- One endpoint shows worse spurs/noise under the same stimulus
- Timing edge-shape differs per branch (threshold/return-path effects)
Jitter sets the floor; skew sets the alignment. A “low PN” source cannot fix a mismatched distribution tree.
Fanout/buffer choices (audio-focused)
- Prioritize output-to-output skew stability (across supply and temperature), not only “typical jitter.”
- Treat the buffer as a noise injection point: isolate its supply and keep its return path clean so branch behavior stays consistent.
- Validate that endpoints see similar edge shapes (rise/fall and overshoot). “Equal length” is not equal if the return paths differ.
Quick verification loop
Probe the same clock node at each endpoint under the same system activity. Compare edge shape and relative arrival order; correlate “worst channel” with the noisiest return/supply neighborhood.
Levels and termination (principles only)
LVCMOS (single-ended)
Common and simple, but fast edges make return-path quality critical. Use series damping where it improves edge integrity without creating long stubs.
LVDS (differential)
Better controlled return and coupling, but requires consistent differential routing and proper termination. Avoid asymmetric stubs and split-plane crossings.
Termination rule: matching the electrical path and return path matters more than memorizing resistor values. Detailed standards belong to Output Standards pages.
Risk checklist for multi-endpoint sync
- Branches have different layer/via count → different edge shapes and delay.
- Clock route crosses a return discontinuity → one channel becomes “noisy.”
- One endpoint input load is very different → threshold timing differs.
- Fanout supply shares a noisy domain → output-to-output skew changes with activity.
Minimum acceptance criteria
Relative arrival order is stable across operating modes, and inter-channel phase error stays consistent across sample-rate changes (no “special rate” failures).
Power, isolation, and PCB layout: making “low PN” survive the real board
A low phase-noise clock source does not guarantee a clean clock at the codec or DAC pin. Board reality is dominated by supply coupling, return-path discontinuities, and high-edge-rate digital clocks (BCLK/LRCK) injecting energy into sensitive analog zones. The objective is to preserve clock integrity by controlling where currents return and where noise is allowed to flow.
Partition model (conceptual, but actionable)
Clock island
Source + fanout + critical distribution nodes. Keep supply clean and return paths continuous so branch behavior stays consistent.
Digital
SoC/links and high di/dt regions. Noise is inevitable; the design job is to keep its return currents away from sensitive references.
Analog
DAC/ADC analog, references, and low-level routing. Protect from return detours and edge-coupled fields.
The clock is not harmed by “being near digital.” It is harmed when its return is forced through digital noise to reach ground.
Clock-domain power (clean supply is an architecture choice)
- Isolate the clock island supply from high di/dt rails; local decoupling must be tight and placed to control high-frequency return loops.
- A buffer fed from a noisy digital rail often creates branch-to-branch differences (skew and edge-shape changes) under activity.
- Filters are only useful if the current return path stays local; otherwise noise bypasses the filter through the plane structure.
Practical check
If audio artifacts change with digital activity level, supply/return coupling is likely dominating over the source phase-noise number.
Routing (keep paths short and returns continuous)
Short and direct
Minimize length, via count, and layer changes so every endpoint sees similar propagation and edge shape.
Reference plane continuity
Avoid split-plane crossings. When a clock crosses a gap, the return detours and coupling into sensitive zones becomes likely.
Differential routing helps control fields and returns, but only if the pair stays symmetric and avoids discontinuities.
Return-path coupling: treat BCLK/LRCK as fast edges
The risk is not the audio-rate fundamental; it is the edge-rate. High-edge-rate clocks inject displacement and return currents that can share impedance with references and analog inputs.
Common failure mode
A “clean” MCLK becomes correlated with digital activity because return currents detour through the analog region, creating dynamic ground/reference modulation.
Fix direction
Keep clock and high-edge-rate signals on routes with continuous reference planes; enforce keepout near sensitive analog, and avoid sharing return paths with switching loops.
Pitfalls checklist + minimal verification set
Pitfalls
- Clock crosses a plane split or narrow return neck.
- Clock island shares supply/return with a switching regulator loop.
- BCLK/LRCK route adjacent to sensitive analog without a controlled return.
- One branch has extra vias/layer changes → unique edge shape and delay.
Minimal verification
- Compare endpoint clock edge shapes under low vs high digital activity.
- Check inter-channel phase stability across sample-rate switching.
- Correlate artifacts with supply/return experiments (isolate, re-route, or quiet the noisy domain).
The fastest debug path is correlation: if the spectrum changes with digital activity, coupling dominates over the source PN specification.
Bring-up & verification: what to measure first (and common measurement traps)
The fastest path to a stable audio clock chain is a three-point measurement loop: validate the source, validate the mid-chain (PLL/cleaner/fanout), then validate what the endpoint actually receives. Most “mystery jitter” and “random pops” are measurement artifacts (probe loading, ground loops, or using the wrong reference clock).
The three-point loop (measure here first)
TP1 — Source output
Confirm the clock exists and is physically correct before blaming the rest of the chain.
freq
duty
amp
edges
TP2 — After PLL/cleaner/fanout
Ensure the “processing stage” is not adding glitches, branch-to-branch differences, or activity-dependent distortion.
freq
edges
jitter-proxy
match
TP3 — At the endpoint pin
What matters is the clock seen by the codec/DAC/SoC. This is where termination, return paths, and digital coupling show up.
edges
term
mode-corr
pops
Basic connectivity (don’t skip the boring checks)
- Frequency is correct for the active sample-rate family (and stays correct after rate switching).
- Duty cycle and amplitude are within the endpoint spec with margin (probe loading can fake a violation).
- Edges do not show obvious multi-threshold crossings (ringing/overshoot that can create “double toggles”).
- Termination behavior matches the topology (no long stubs, no “mystery” reflections that only appear at the endpoint).
Debug rule: if TP1 looks perfect but TP3 looks ugly, the board is the culprit (routing, return, termination, coupling).
Functional verification (rate switching, lock, long-run, dropout)
Sample-rate switching
Verify switching produces a stable endpoint clock without clicks/pops; confirm mute/settle behavior matches system policy.
Lock time
Measure time from rate-change trigger to “no artifacts and stable operation.” Use a placeholder target (≤ X ms / ≤ X frames) to fit different designs.
Long-run drift & dropout
Run hours in worst-case digital activity; validate no buffer under/overflow, no sporadic relock, and clean recovery after input dropouts.
Common measurement traps (trap → fake symptom → fix)
Probe loading
Fake symptom: amplitude/duty looks wrong, ringing looks worse. Fix: use higher-impedance probing and compare TP1↔TP3 with the same setup.
Ground loop (long ground lead)
Fake symptom: spikes/overshoot appear that are not real. Fix: use a short ground spring / coax reference and keep the return local.
Wrong reference clock
Fake symptom: “drift/jitter is huge” because BCLK is used as if it were MCLK. Fix: measure each clock by its role (MCLK baseline, BCLK bit timing, LRCK frame).
Measuring only in quiet mode
Fake symptom: everything looks clean until real digital activity starts. Fix: repeat TP1/TP2/TP3 checks in worst-case activity mode.
Fast isolation test: if endpoint edge quality changes with digital activity, board coupling dominates over the source PN number.
Minimal bring-up path (a repeatable script)
- TP1: verify freq/duty/amp/edges at the source.
- TP2: verify no glitches and branch match after PLL/cleaner/fanout.
- TP3: verify endpoint sees clean edges and expected termination behavior.
- Run rate switching: log lock time and artifact-free settling.
- Run long-run worst-case activity: confirm no drift/buffer events.
- If failure: use correlation (activity, supply isolation, routing) to localize the layer: source vs mid-chain vs endpoint vs board coupling.
Design-to-test engineering checklist (audio-clock specific)
This checklist freezes the audio clock chain from requirements to verification so bring-up and production reuse the same logic. Each section uses reusable placeholders (X) so the template fits different platforms without rewriting the process.
1) Spec freeze (testable requirements)
Fs set
44.1/48 families
Freeze supported sample rates and switching combinations. Define which rates must be artifact-free.
ppm
≤ X
Freeze allowable frequency error and long-run drift behavior; align it with buffer and policy decisions.
switch time
≤ X
Freeze target settling/lock time and define dropout behavior (mute/holdover/recover).
2) Architecture freeze (roles and boundaries)
Master vs follower
Freeze which device owns MCLK and which blocks must track it. Document role switching and failover rules (if any).
ASRC vs PLL responsibility
Freeze the boundary: PLL handles coarse tracking/sync needs; ASRC absorbs residual drift and isolates asynchronous sources.
Timing island boundary
Freeze where asynchronous behavior is allowed (buffers/ASRC) and where strict sync is required (codec/DAC clock domain).
3) PCB freeze (make the clock survive)
power isolation
local return
Freeze clock island supply strategy and ensure return paths stay continuous through all critical routes.
clock tree
star
match
Freeze topology (often fanout star) and branch matching rules (length, vias, and return continuity).
termination
test points
Freeze termination/damping placement and reserve TP1/TP2/TP3 locations that do not degrade the signal.
4) Verify freeze (tests + pass criteria placeholders)
Waveform integrity
freq/duty/edges/termination within spec. Use placeholders: overshoot < X, ringing < X cycles, edge shape consistent across endpoints.
Switching behavior
Artifact-free switching: pops = 0. Relock/settle ≤ X (ms/frames). No abnormal re-lock loops.
Long-run worst-case
Run hours with worst digital activity: dropout rate < X/hour, no buffer under/overflow events, and stable inter-channel behavior.
Feedback loop: fail → locate layer (Spec / Architecture / PCB / Verify setup) → fix → re-verify using the same script.
Applications & IC selection notes (Audio Master Clocks)
This section covers architecture-driven selection (not a product list): choose the clock source strategy, decide whether ASRC/PLL cleaning is required, and plan distribution for multi-device audio. Part numbers below are reference starting points for datasheet lookup and field verification—always confirm package, output standard, voltage, frequency options, and availability.
A) Typical systems (map the clock problem first)
USB Audio Interface
Async host clock + local audio island. Common risks: drift-driven buffer events and rate-change pops.
async source
ASRC/buffer
AV Receiver
Multi-input switching (HDMI/network/local). Common risks: family switching and “hitless” transitions.
dual-family
switch policy
Smart Speaker
Wireless/network jitter and system activity can modulate clock edges on real boards.
activity-corr
power/layout
Pro Audio ADC–DAC Chain
Multi-channel coherence is sensitive to skew/phase drift across endpoints (audible as imaging/phase artifacts).
multi-device
skew control
B) Decision inputs (3 knobs that drive everything)
Fs family
single / dual
Dual-family support typically pushes toward dual XO, programmable XO, or synthesis with verified switching behavior.
async source
USB / BT / Net
If the input timebase is not the audio island timebase, ASRC/buffer policy defines stability more than “nice PN numbers.”
multi-device
fanout / skew
Multiple codecs/DACs typically require fanout topology and endpoint-to-endpoint verification (not just source probing).
C) Clock-source choice (dual XO vs programmable vs synthesis)
Choose based on family coverage, switch behavior, and board survival (power/layout/termination).
Dual XO (22.5792 + 24.576 MHz)
Best when dual-family support is mandatory and deterministic switching is preferred.
Example part numbers
- Crystek CCHD-957 (audio-grade clock oscillator family; choose 22.5792/24.576 MHz option)
- NDK NZ2520SD (low phase-noise oscillator family; choose target frequency option)
- Abracon ASV/ASTX oscillator families (frequency options available; verify noise grade and output)
Switching note: validate mute/soft-ramp + lock/settle targets (≤ X ms / ≤ X frames).
Programmable XO (platform SKUs)
Best when multiple SKUs/ratios exist and clock frequencies must be configured over I²C/SPI or straps.
Example part numbers
- SiTime SiT5356 (programmable, jitter-optimized oscillator family; verify interface and frequency plan)
- SiTime SiT8208 (programmable oscillator family; verify jitter grade vs audio requirements)
- Renesas/IDT 5P49V6965 (programmable clock generator; verify output standard and phase noise targets)
Bring-up requirement: treat frequency reprogramming as a mode switch—verify TP2/TP3 edges and artifact-free transitions.
Synthesis (PLL/cleaner-derived clocks)
Best when the system must track an external reference or generate multiple related clocks with controlled behavior.
Example part numbers
- Silicon Labs Si5341 (jitter attenuator/clock cleaner; verify output standard and loop profiles)
- Silicon Labs Si5340 (clock generator/cleaner family; verify jitter/phase noise vs audio target)
- Texas Instruments LMK04828 (high-performance clock jitter cleaner/fanout class; verify complexity vs audio needs)
Validation focus: switching/lock time, activity-correlated spurs, and endpoint edge integrity (TP3).
D) Need ASRC? (and where it belongs)
ASRC is usually preferred when
- The source timebase is inherently asynchronous (USB/BT/network streaming).
- The audio island must stay stable even when the source drifts or drops out.
- Low-latency lock-to-external is not the top priority (or can be handled coarsely elsewhere).
Failure symptoms → tuning direction
Buffer under/overflow → tracking too slow/too fast, buffer depth mismatch, or bad rate-change policy.
Pops/clicks on transitions → missing mute/soft-ramp window or lock/settle not complete before unmute.
Imaging instability → skew/endpoint edge issues; validate clock distribution and TP3 edge integrity.
Example ASRC part numbers
- Texas Instruments SRC4392 (ASRC + audio interface functions; verify system partition)
- Texas Instruments SRC4192 (ASRC-focused; verify I/O formats and clocking)
- AKM AK4137 (sample rate converter family; verify supported formats/rates)
- Cirrus Logic CS8422 (SRC family; verify interface and system clocking needs)
Placement rule: keep ASRC at the boundary between asynchronous ingress and the synchronous audio island.
E) Need a cleaner/PLL? (where to put it)
Placement patterns (choose by system intent)
- External-sync priority: PLL tracking near the ingress boundary, then verify clean handoff into the audio island.
- Audio-quality priority: place cleaning close to the synchronous island (protect TP3 edges from board coupling).
- Two-stage: coarse follow (boundary) + local cleanup (island) when both sync and quality are strict.
Example cleaner/PLL part numbers
- Silicon Labs Si5341 (jitter attenuator; verify profiles and outputs)
- Silicon Labs Si5340 (clock generator/cleaner family; verify requirements)
- Texas Instruments LMK04828 (cleaner/fanout class; verify board complexity)
- Texas Instruments CDCE6214-Q1 (clock synthesizer family; verify noise and outputs for audio use)
Verification anchor: if TP2 looks good but TP3 changes with system activity, layout/power coupling dominates.
F) Multi-device distribution (fanout & skew control)
Topology guidance (audio practical)
- Star fanout is commonly the safest for multi-endpoint coherence.
- Avoid long stubs and keep return planes continuous (skew issues often look like “soundstage drift”).
- Define an endpoint-to-endpoint skew budget (Δt < X) and validate it under worst-case activity.
Example fanout / distribution part numbers
- Texas Instruments CDCLVC1102 / CDCLVC1104 (low-skew clock buffer family; verify voltage/output)
- Texas Instruments LMK00304 (low-additive-jitter fanout buffer class; verify outputs)
- Renesas/IDT 5PB1108 (fanout buffer family; verify output type and jitter)
DFT note: reserve TP3 near at least two endpoints to confirm branch match and skew under load.
G) Go deeper (keep this page lean)
Use these links to avoid turning this section into a generic catalog:
XO (Crystal Oscillator) — fundamentals & practical selection boundaries
PLL / Jitter Cleaner — loop intent, lock behavior, and spur hygiene
Distribution & Fanout — output standards, termination, skew budgeting
Key Specs — phase noise, jitter windows, stability, and spur masks
Rule: decisions are made by inputs (family/async/multi-device); confidence is earned by verification (TP2/TP3 + switching + long-run).
Recommended topics you might also need
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FAQs (Audio Master Clocks)
Short, actionable troubleshooting within this page boundary. Each answer is a fixed 4-line, measurable format: Likely cause / Quick check / Fix / Pass criteria.
Why do I still hear pops/clicks when the clocks look “correct” on the scope?
Likely cause
Unmute happens before the audio domain is settled (PLL lock/ASRC ratio/buffer boundary), causing a phase/amplitude discontinuity even if frequency “looks right.”
Quick check
Correlate the pop timestamp with: (1) codec lock status transition, (2) ASRC ratio update events, (3) buffer level crossing a threshold. Probe at the codec clock pin (TP3), not only the source (TP1).
Fix
Add a deterministic switch policy: mute → switch/lock → wait “lock stable” → soft-ramp gain → unmute. Gate unmute on both lock-stable and buffer-in-range.
Pass criteria
No audible pops/clicks over X consecutive mode switches; lock flag remains stable; FFT shows no new discrete artifacts above X dBFS during transitions.
Sample-rate switching works, but relock takes seconds—what’s the first knob to check?
Likely cause
Acquisition dynamics are constrained: loop bandwidth/fast-lock profile is too conservative, or lock-detect gating requires a long “stable time.”
Quick check
Log “lock acquired” timestamp vs switch command; compare profiles (narrow vs wide BW if available). Check whether relock time is dominated by PLL acquisition or by firmware “wait stable” logic.
Fix
Use a two-stage profile: wide BW (or fast-lock) during acquisition → narrow BW for steady-state. Reduce lock-detect “stable” window only after validating pop-free unmute sequencing.
Pass criteria
Relock time < X ms and artifact-free transitions across X switches; no unlock counter increments; buffer stays in-range.
USB audio drops out occasionally—how to tell buffer underflow vs clock drift?
Likely cause
Underflow is usually a scheduling/throughput problem; drift is usually a feedback/ratio-tracking problem. Both look like “dropout” but leave different signatures in buffer telemetry.
Quick check
Log buffer level over time and overlay with: (1) USB isochronous error counters, (2) measured ppm estimate (ASRC ratio / feedback value). Underflow often shows sudden dips; drift shows slow ramp to a boundary.
Fix
For underflow: increase buffering and prioritize audio/USB threads. For drift: tune ASRC/feedback loop (update rate, limits, smoothing) and ensure the audio island is the true timing master.
Pass criteria
0 dropouts over X hours; buffer level remains within [L, H] band; error counters remain flat.
ASRC is enabled, yet noise floor rises—what clock-domain leak is most common?
Likely cause
Clock edges leak through the board, not the math: BCLK/LRCK return currents and clock-island supply noise modulate analog paths (activity-correlated “jitter-like” sidebands).
Quick check
Run a single-tone FFT and toggle system activity (CPU load / RF on/off). If sidebands/noise floor follows activity while Fs is constant, the dominant path is power/ground coupling. Probe clock-island rails near XO/PLL and codec PLL pins.
Fix
Harden the clock island: separate low-noise LDO, add local filtering (RC/FB/LC as appropriate), ensure continuous return plane, and use series-R at the driver to reduce edge-induced coupling (without violating timing margins).
Pass criteria
Activity on/off changes noise floor by < X dB; no new correlated sidebands above X dBFS; stable across X hour runs.
MCLK is very low jitter, but channel-to-channel phase sounds “off”—where does skew sneak in?
Likely cause
Skew is introduced after the “good” source: fanout topology, unequal trace delay, different return paths, or endpoint PLL/divider differences create inter-channel phase error.
Quick check
Measure endpoint-to-endpoint timing (same probe setup) at two codec/DAC clock pins (TP3A/TP3B). Also check LRCK alignment at endpoints (a shared MCLK does not guarantee shared frame alignment).
Fix
Use star fanout with a low-skew buffer, length-match critical branches, keep reference plane continuous, and enforce a single master for LRCK/BCLK generation when coherence is required.
Pass criteria
Endpoint skew < X ps/ns under worst-case activity; stable imaging/phase across X hours; no periodic re-alignment events.
Why does using a programmable XO sometimes worsen spurs in the audio band?
Likely cause
Spur mechanisms can change with configuration: internal fractional synthesis/dividers, I²C activity coupling, and supply/ground modulation can place discrete tones in-band.
Quick check
Compare DAC FFT spurs across (1) different XO output frequencies, (2) different power rail noise conditions, and (3) I²C traffic on/off. Spurs that move with configuration imply synthesis; spurs that track activity imply coupling.
Fix
Use an “integer-friendly” frequency plan when possible, lock configuration (avoid dynamic reprogramming during playback), and harden XO supply/return isolation. Validate at the codec pin (TP3), not only at the XO output.
Pass criteria
Audio-band discrete spurs remain below X dBFS across all supported Fs/families and power modes; no new config-dependent tones appear after long-run testing.
Why does the system sound fine at 48 kHz but not at 44.1 kHz?
Likely cause
The 44.1k family path is misconfigured: wrong MCLK family (or ratio), incorrect BCLK math, or a faulty family-switch policy (XO switch / PLL profile / reset sequence).
Quick check
In 44.1k mode, measure actual MCLK frequency at TP3 and confirm expected ratio (e.g., 256fs/512fs). Verify BCLK = Fs × (bits per slot) × (channels/slots). Compare register dumps between 48k and 44.1k.
Fix
Correct the family mapping table and enforce deterministic switch sequencing (mute → switch → lock → wait stable → ramp → unmute). If dual-family is required, use dual XO or verified programmable frequency sets.
Pass criteria
Comparable performance (noise/spurs/artifacts) across both families; 0 mode-switch failures over X consecutive switches; no lock/unlock oscillation.
BCLK/LRCK edges look clean, but the codec reports PLL unlock—what should I probe first?
Likely cause
The codec sees a different signal than the scope: amplitude/common-mode/overshoot/undershoot at the codec pin, or supply noise at the codec PLL domain triggers false unlock.
Quick check
Probe at the codec clock input pin with a low-capacitance probe and a short ground spring. Check VIH/VIL margin, duty cycle, and overshoot/undershoot. Read unlock counters and correlate with system activity and rail ripple.
Fix
Improve endpoint integrity: series-R near the driver (not at the load), correct termination, and decouple/quiet the codec PLL supply. Avoid routing across split planes; keep return continuous.
Pass criteria
Unlock counter stays at 0 over X hours and X switches; codec input meets voltage/duty specs; no artifact bursts during activity peaks.
Changing power rails changes “jitter-like” artifacts—what supply coupling path is typical?
Likely cause
Supply noise modulates edge timing (XO/PLL) or contaminates thresholds at the receiver (codec PLL), often through shared regulators, shared return currents, or DC/DC magnetic/ground injection.
Quick check
Compare spur/noise changes with rail ripple measured at (1) XO/PLL supply pins, (2) codec PLL supply, and (3) analog reference rails. If artifacts track specific rails or DC/DC load steps, coupling is confirmed.
Fix
Give the clock island a dedicated low-noise regulator and local filtering; keep clock return paths out of noisy ground corridors; increase local decoupling at codec PLL pins; keep DC/DC and its hot loop away from clock routes.
Pass criteria
Within rail tolerance ranges, artifact level changes by < X dB; no new tones appear; long-run stability with unlock/errors = 0.
Why does adding series R improve stability but cause intermittent I2S errors?
Likely cause
Series-R fixed overshoot/ringing, but slowed edges enough to reduce setup/hold margin at the receiver (especially with longer routes or heavy capacitive loads).
Quick check
Sweep R in steps and record error rate/unlock counters. Measure rise/fall time at the receiver pin and compare to the interface timing margin. If errors increase as edges slow, timing margin is the limiter.
Fix
Place series-R at the driver, choose the minimum value that controls ringing, reduce route length/stubs, and adjust drive strength/termination. If margins are tight, consider a different signaling standard (e.g., differential) for long runs.
Pass criteria
0 framing/CRC/unlock events over X hours; receiver edges meet minimum slew/duty requirements; ringing controlled without reducing timing margin below X%.
How do I validate “clock quality” without a phase-noise analyzer? (practical proxy tests)
Likely cause
The biggest risk is trusting the wrong proxy (measuring the source only, or measuring under non-representative system activity) and missing endpoint-coupled artifacts.
Quick check
Use proxy tests at the audio output: (1) single-tone FFT for sidebands/spurs, (2) idle/no-signal noise floor, (3) activity correlation (CPU/RF on/off), (4) A/B compare at TP3 (endpoint) across clock options.
Fix
Standardize a proxy test plan: fixed tone, fixed gain, fixed load, worst-case system activity, and endpoint probing (TP3). If possible, add a controlled jitter injection experiment to verify sensitivity trends.
Pass criteria
Proxy metrics meet targets: noise floor within X dB, sidebands below X dBFS, and results are consistent across repeated runs and system activity states.
Two devices share MCLK but still drift apart over hours—what assumption is wrong?
Likely cause
Sharing MCLK does not guarantee a shared frame/word timebase: LRCK/BCLK may be generated independently, resampling may occur, or software clock correction differs between devices.
Quick check
Confirm which device generates LRCK/BCLK in each domain. Measure LRCK frequency/phase at both devices over time, and log any resync/restart events. If drift persists with identical LRCK sources, check hidden async paths (ASRC/PLL domains).
Fix
Establish a single master for LRCK/BCLK (or distribute them coherently), and eliminate untracked async conversions between devices. If long-run alignment is required, add an explicit alignment/monitoring mechanism and periodic correction strategy.
Pass criteria
Relative drift < X samples over X hours; no resync events; measured LRCK phase remains within the defined alignment window under worst-case activity.
