Ethernet/SyncE PHY Reference Clocks (25/125/156.25 MHz)
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Ethernet/SyncE PHY clocks are a system timing chain problem: separate HF jitter (link margin) from LF wander/holdover (sync quality), then validate the clock at A/B/C points (source → post-cleaner → at-PHY) so field alarms map to a measurable cause and a fixable knob.
Definition & scope: Ethernet / SyncE PHY clocks (25/125/156.25 MHz)
Ethernet/SyncE PHY clocks are the reference clock chain that feeds PHY/switch clock pins and their internal clock trees (source → cleaner/DPLL → fanout/distribution → PHY endpoints). This page focuses on engineering decisions that determine clock quality on real boards, not protocol-level history.
- Act as the timing reference for PHY/PCS/SerDes clock trees.
- Enable frequency synthesis and line-rate-derived timing inside the PHY/switch.
- In SyncE, carry traceable frequency quality across the timing chain.
- Data link OK: eye/BER margin is mostly sensitive to high-frequency jitter.
- Sync quality OK: SyncE quality/holdover is dominated by low-frequency wander.
- No deep protocol text (no PTP/1588, no network SSM/ESMC deep dive).
- No clause-by-clause standards transcription.
- Only board/system engineering: budgets, clock-tree, layout, and verification hooks.
A key practical point is that the same 156.25 MHz may be “good enough to link” yet still fail “telecom-grade SyncE quality” when wander/holdover is not engineered and validated end-to-end.
Where these frequencies come from: 25 vs 125 vs 156.25 (and what they drive)
The same “clock number” is not a design requirement by itself. What matters is which device pin/domain consumes it, how it is synthesized (XO vs DPLL-derived), and whether the target is “link margin” or “telecom-grade SyncE quality”.
Common source path: crystal XO / TCXO; sometimes disciplined or re-generated by a cleaner.
Engineering stress: supply-noise sensitivity and board coupling can dominate even with a “good” XO.
Common source path: derived from 25 MHz via ×5, or generated by a cleaner output profile.
Engineering stress: multiplication paths increase sensitivity to reference and supply noise injection points.
Common source path: cleaner/DPLL output (tracking or cleaning profile); sometimes derived from 25 MHz via ×6.25.
Engineering stress: tighter jitter expectations and longer synthesis chains expose board-level coupling and loop-BW mistakes.
- 25 → 125 (×5): cost-effective platform approach; ensure the multiplier chain does not amplify supply/ground coupling.
- 25 → 156.25 (×6.25): common in cleaner-based designs; choose loop bandwidth and profiles to avoid passing low-frequency wander into the output.
- Clean-heavy vs track-heavy outputs: “clean” can improve eye margin while “track” protects SyncE traceability; mixing them without a plan causes field-only failures.
- Boundary note: higher SerDes-centric references (e.g., beyond these three anchors) should be handled in the SerDes clock subpage to avoid content overlap.
SyncE quality in practice: what EEC/SEC imply for your design
EEC/SEC requirements translate to a frequency-quality target that must remain valid from the clock source to the PHY pins. In engineering terms, this splits into two coupled paths: high-frequency jitter (short-term timing noise impacting link margin) and low-frequency wander/holdover behavior (long-term stability impacting SyncE quality).
- HF jitter path: determines eye/BER margin and sensitivity to board-level coupling.
- LF wander path: determines long-term SyncE quality and holdover drift during input disturbances.
- Coupling knob: cleaner/DPLL loop bandwidth controls how much input noise is tracked vs cleaned.
- Reference stability: temperature behavior and long-term drift set the holdover baseline.
- Loop BW & holdover mode: choose a tracking/cleaning profile that matches the SyncE objective.
- Supply/ground injection: LDO noise, shared returns, and digital coupling can create phase modulation.
- Thermal gradients: placement and airflow affect drift repeatability and warm-up behavior.
- Distribution & return: fanout, termination, and reference-plane continuity decide “at-pin” quality.
- Locks fine, but quality fails: wander/holdover is not meeting the system objective.
- Jitter looks small, holdover is poor: stability is limited by source drift, thermal gradients, or holdover configuration.
- Bench OK, field fails: state transitions, supply noise, or distribution injection dominates outside the lab setup.
- Define HF jitter pass criteria in a specified integration window tied to link margin.
- Define LF wander/holdover pass criteria over time scales tied to SyncE quality objectives.
- Verify at three locations: source → post-cleaner → at-PHY pin.
Two budgets you must separate: High-frequency jitter vs low-frequency wander
Passing an “integrated jitter” number does not prove SyncE quality. High-frequency jitter and low-frequency wander are measured with different windows, different time scales, and different pass criteria. Mixing them creates the most common “bench OK, field fails” scenario.
- Typically evaluated as integrated jitter from a phase-noise curve.
- Strongly influenced by supply noise injection, coupling, fanout, and termination.
- Best validated at the PHY pin, not only at the cleaner output.
- Evaluated over time scales (wander metrics and holdover drift behavior).
- Dominated by reference stability, loop bandwidth choices, and thermal gradients.
- Must include holdover events and mode transitions in the test plan.
- Wrong location: measure source → post-cleaner → at-PHY to catch distribution injection.
- Wrong window: define HF integration windows and LF time scales explicitly (do not reuse one number).
- Ignored PLL drift/state: log DPLL mode, loop BW, input events, and holdover state alongside results.
- Classify the symptom: link margin issue (HF) vs quality/holdover issue (LF).
- Pick the right window/time scale; define the measurement locations (source/post-cleaner/at-PHY).
- Walk the chain to find the injection owner: source stability, cleaner configuration, or distribution/return coupling.
Clock source choices: XO/TCXO/OCXO/MEMS vs recovered timing
Source selection should start from the system objective: link margin (high-frequency jitter) and/or SyncE quality (low-frequency wander and holdover behavior). The source type sets the baseline, while cleaner configuration and board-level injection often determine the at-pin result.
- Data link OK: prioritize phase noise / integrated jitter and board coupling immunity.
- Sync quality OK: prioritize stability, temperature behavior, and holdover drift.
- Both: assign ownership: source sets stability baseline; cleaner sets track/clean split; PCB sets injection risk.
- Source baseline: stability trend, warm-up behavior, and intrinsic noise floor.
- Cleaner behavior: loop bandwidth, profile (track/clean), and holdover strategy.
- Board injection: supply noise, thermal gradients, and distribution/return integrity.
- Rule: a good datasheet source does not guarantee good at-PHY pin clock quality.
Primary risk: supply/ground sensitivity and board coupling dominate at-pin results.
Quick check: compare post-cleaner vs at-PHY pin jitter; large deltas imply distribution injection.
Upgrade trigger: margin collapses across temperature or under supply disturbance.
Primary risk: “stable source” assumptions hide holdover/profile issues downstream.
Quick check: thermal step behavior and recovery at the reference input and after the cleaner.
Upgrade trigger: longer holdover targets or strict long-term quality requirements.
Primary risk: thermal design and gradients break repeatability even with a strong device baseline.
Quick check: warm-up repeatability and drift vs board thermal environment.
Upgrade trigger: uncontrolled temperature gradients or long holdover duration targets.
Primary risk: discrete spurs and different coupling patterns compared with crystal sources.
Quick check: spectrum scan for spur signatures and sensitivity to supply filtering.
Upgrade trigger: tight phase-noise masks or severe link margin constraints.
Primary risk: input quality variations + wrong cleaner profile creates field-only quality failures.
Quick check: output behavior during input events (loss/restore/quality change) and mode transitions.
Upgrade trigger: unstable inputs require dual references, alarms, and controlled switching.
Detailed oscillator fundamentals (XO/TCXO/OCXO/MEMS internal architecture and device-level deep dives) belong to their dedicated subpages. This section stays at the system level: trade-offs, failure signatures, and verification entry points.
Cleaning & tracking: DPLL / jitter attenuator loop bandwidth strategy
Loop bandwidth is the boundary between tracking and cleaning. Inside the bandwidth the output follows input timing changes (protecting frequency transfer); outside the bandwidth the output is dominated by the cleaner’s own noise and filtering (protecting low jitter).
- Optimizes: input tracking and frequency transfer behavior.
- Risks: passes more low-frequency wander into the output.
- Verify: input events do not cause quality failures or unexpected state transitions.
- Optimizes: balance between jitter cleaning and quality tracking.
- Risks: mode thresholds/state machines can create field-only failures.
- Verify: profile switching is controlled and observable under real events.
- Optimizes: low integrated jitter for link margin.
- Risks: less responsive tracking; holdover and re-lock behavior can dominate quality.
- Verify: input loss/restore produces predictable behavior within system thresholds.
- Contributors: source stability, thermal gradients, and selected holdover mode.
- Event coverage: input loss/restore, reference switching, warm-up, and supply disturbances.
- Observability: record DPLL mode/state, loop BW profile, and alarms alongside measurements.
Distribution to PHYs: fanout, skew control, redundancy, and hitless switching
A strong source and a well-configured cleaner do not guarantee a strong at-PHY clock. Distribution is where load interaction, return-path integrity, and switching events can amplify jitter or create intermittent failures. The objective is a clock tree that is replicable to N PHYs, skew-bounded, and event-safe under main/backup scenarios.
- Output level: match PHY expectation (LVCMOS/LVDS/HCSL/LVPECL) and the board termination plan.
- Load interaction: each output has its own “at-pin” quality; avoid assuming identical behavior across ports.
- Termination consistency: mismatched terminations create reflections that look like jitter and degrade margin.
- Power integrity: fanout is a common injection point; isolate supplies and keep returns tight.
- Intra-board: length mismatch, channel-to-channel variation, termination differences, and return asymmetry.
- Inter-board: connectors/cables, temperature gradients, and supply-domain differences add drift.
- Practical rule: define an allowable relative arrival window and verify it across temperature and events.
- Monitor: missing-pulse, frequency offset, lock state, and quality alarms drive switching decisions.
- Mux: glitch-free/hitless behavior must be defined by system thresholds, not by marketing terms.
- Cleaner integration: switching interacts with loop BW/profile; validate the combined behavior.
- Hitless required: services cannot tolerate retraining or clock gaps; switching must remain within event thresholds.
- Short disturbance allowed: systems can retrain quickly and recover deterministically with bounded impact.
- Observability: log switch reason, input quality, DPLL mode/profile, and alarm state for every event.
This section stays in the PHY clock distribution view. Large crosspoint architectures and multi-domain clock routing belong to a dedicated crosspoint/switch page.
Signal integrity for PHY clocks: levels, terminations, and coupling paths
PHY clock failures on real boards often come from mismatch (levels/terminations), return-path breaks, or noise injection into the oscillator/PLL. The goal is not general high-speed SI theory, but a clock-chain-specific checklist that maps each coupling path to a measurable symptom.
- Differential: better immunity to common-mode noise, but relies on symmetry and correct termination.
- Single-ended: simpler, but highly sensitive to return-path integrity and ground bounce.
- Decision rule: choose the level/standard that matches the termination and return-path capability.
- Standard match: output swing/common-mode must match the PHY input expectation.
- Termination plan: keep it consistent per output; mismatches create reflections that degrade margin.
- Stub control: minimize via count and branching; stubs look like extra “random jitter” in practice.
- Short & straight: minimize length and discontinuities to reduce reflection and coupling.
- No plane breaks: crossing splits/slots breaks return current and creates phase modulation.
- Avoid parallel aggressors: keep distance from noisy clocks/data and switchers.
- Mechanism: supply/ground noise modulates XO/PLL phase and shows up as jitter/sidebands.
- Mitigation: quiet LDO, supply domain separation, and tight local decoupling/returns.
- Tell-tale: problems appear under load/temperature even when bench waveforms look clean.
- BER/eye margin degrades: check HF jitter window, terminations, and crosstalk near the clock routes.
- Intermittent unlock after events: check mux/monitor thresholds, state transitions, and return-path breaks.
- Temperature-only failures: check thermal gradients, holdover behavior, and supply sensitivity.
- Only multi-output gets worse: check fanout loading per output and per-port termination consistency.
EMI & SSC coexistence: when SSC helps and when it breaks timing
Spread-Spectrum Clocking (SSC) is a practical way to reduce narrowband EMI peaks (down-spread is common), but it can undermine timing quality if the clock domain must meet tight jitter or telecom-grade synchronization goals. The decision is not a single toggle: SSC behavior depends on the clock domain, the cleaner/DPLL profile, and what the system treats as valid wander vs a fault.
- Peak reduction: spreads energy so narrowband peaks drop, improving EMI margin.
- Low effort: often a configuration option at the clock source or generator.
- Best fit: non-timing-critical domains where the link is tolerant to modulation.
- Telecom sync domains: modulation can interact with wander/quality evaluation.
- Tight jitter domains: modulation may erode margin depending on jitter window and chain behavior.
- Multi-PLL chains: modulation can be passed, reshaped, or misclassified by downstream loops.
- Tracking-heavy: SSC is likely treated as “valid input motion” and gets propagated.
- Clean-heavy: SSC may be suppressed, but mode switching and alarms must be validated.
- Hybrid: behavior changes across conditions; verify across events (switch/thermal/load).
- HF check: compare integrated jitter at the same point (post-cleaner and at-PHY).
- LF check: confirm quality/holdover state and alarms do not “chatter”.
- Event check: verify behavior under switching, temperature sweep, and input disturbance.
Monitoring, alarms & switchover hooks: what to expose to system firmware
Redundancy only works in the field when the clock chain is observable. Firmware needs a minimal, stable set of status signals to classify conditions (warning vs fault), trigger safe switchover, and log enough context to make intermittent timing issues reproducible. The focus here is board-level implementation: registers, alarms, counters, and a clear decision boundary.
- Lock state: loss-of-lock / locked / acquiring.
- Ref presence: missing pulse / ref valid.
- Holdover: active/inactive and entry reason.
- Input selected: main vs backup.
- Quality level: a stable grade indicator (implementation-defined).
- Offset indicator: frequency offset state / threshold crossing.
- Loop profile: track/clean/hybrid and current mode.
- Switch reason: coded cause (loss, degrade, manual).
- Temperature snapshot: captured on events for correlation.
- Warning: quality degraded but still locked → log + optional policy adjustments.
- Fault: loss-of-lock/ref missing/over-limit → switchover or protection action.
- Stability: add hysteresis/hold time to avoid alarm chatter and ping-pong switching.
- Pre-check: confirm backup ref present + quality acceptable.
- During: capture event timestamp and state machine step.
- Post-check: confirm lock stable and alarms settle within policy limits.
- Header: timestamp, event type (loss/restore/switch).
- Context: selected input, quality level, lock state, loop profile, temperature.
- Outcome: holdover entered, post-event alarms, any subsequent switching.
Verification & measurement: lab tests that correlate with field failures
Field issues rarely come from a single number. Correlation improves when measurements close the loop across three physical points: source (reference quality), post-cleaner (profile + loop behavior), and at-PHY (distribution + coupling + return path). Separate the evidence into two budgets: high-frequency jitter (eye/BER margin) and low-frequency wander/holdover (sync quality stability).
- Point A — Source: baseline reference behavior (XO/TCXO/OCXO/MEMS or recovered input). Used to assign noise ownership.
- Point B — Post-cleaner: confirms loop profile (track vs clean vs hybrid), spur behavior, and how input quality propagates through the bandwidth split.
- Point C — At-PHY: the deliverable clock. Captures fanout additive noise, termination mistakes, crosstalk, ground-return breaks, and supply injection.
Interpretation rule: B good + C bad → distribution/coupling. A bad + B good → cleaner hides input (verify holdover/events).
- Measure: integrated jitter in the system-defined window + PN shape (noise floor vs discrete spurs).
- Where: always compare A, B, C. A single-point pass can miss fanout/PCB coupling.
- Stimulus: toggle SSC states (allowed domains only), inject supply ripple, step load, and change fanout enable patterns.
- Spur sanity: if a spur moves with load/SSC/supply, treat it as a coupling signature, not “random jitter”.
- Holdover entry/exit: force reference loss; record frequency drift trend vs time at B and C.
- Temperature overlay: repeat with controlled thermal steps; log temperature + profile + control words for correlation.
- Quality state stability: verify alarms do not chatter during marginal inputs; confirm hysteresis and timers behave as intended.
Avoid standards deep-dive here. Use the system budget to set thresholds (placeholders below) and validate repeatability.
- Main↔backup switching: trigger manual and fault-injected switching; observe phase step / gap at C.
- Lock reacquisition: validate expected time-to-stable; confirm alarms are latched/cleared deterministically.
- Domain isolation: verify SSC or noisy domains do not perturb the sync-critical clock path across the mux/cleaner boundary.
- Probe ground loop / long pigtails → compare with differential probing → remove loop area & re-check spur movement.
- Triggering on recovered clocks / hidden loops → re-run with explicit reference selection & loop state frozen.
- Over-averaging → capture worst-case excursions (event-driven) and correlate with alarm counters.
- Single-point testing → enforce A/B/C comparison to avoid mis-assigning root cause.
- Goal: e.g., “Clock at PHY meets BER/eye margin and remains stable across reference loss & recovery.”
- Setup: instrument → DUT; measure at A/B/C; log temperature and profile/state.
- Stimulus: SSC toggle (allowed domains), load step, reference degrade/loss, main↔backup switching.
- Pass (HF): integrated jitter @C < [J_HF_budget]; no new discrete spurs above [spur_limit].
- Pass (LF): holdover drift @C < [drift_budget] over [time]; alarms stable (no chatter).
- Pass (events): switching transient < [event_budget]; recovery time < [T_recover].
Engineering checklist + Applications & IC selection notes
This section is the handoff artifact: a design-review checklist, a spec/budget checklist, scenario buckets, and production hooks. Part numbers below are starting points for datasheet lookup and evaluation; final selection must be driven by the system budgets (HF jitter, LF wander/holdover, events, temperature, and EMI domain policy).
- Define domains: sync-critical vs non-critical (SSC allowed only where explicitly permitted).
- 3-point observability: reserve probe pads for A/B/C; add firmware telemetry for loop/profile/alarms.
- Redundancy: main + backup, clock-detect/monitor, glitch-free or hitless switching policy, and failure logs.
- Distribution discipline: controlled impedance, short routes, continuous reference plane, correct termination, and fanout power isolation.
- Source examples: SiTime SiT1602 (XO), SiTime SiT5156 (TCXO).
- Cleaner/Gen (if needed): Skyworks/SiLabs Si5342/Si5344 (jitter attenuating multiplier).
- Distribution examples: TI LMK1C1104 (LVCMOS fanout), TI LMK00304 (multi-standard differential fanout).
- Local oscillator examples: SiTime SiT5156 (TCXO) or SiTime SiT5711 (Stratum-grade OCXO class). Quartz OCXO example: Abracon AOCJY1 series.
- Network synchronizer / DPLL examples: ADI AD9545, Renesas 8A34001, Microchip ZL30772, Skyworks/SiLabs Si5345.
- Policy: SSC off in sync-critical domain unless proven safe by A/B/C testing; tracking vs cleaning profile must be explicit and logged.
- Distribution: prefer differential fanout with explicit termination; TI LMK00304 as a multi-standard fanout example.
- Glitch-free mux example: Renesas 580-01 (glitch-free clock mux; use as main/backup selector where appropriate).
- Telemetry: expose lock state, active ref, holdover state, alarms/counters, and temperature snapshots for field correlation.
Suggested split: 100% line tests (fast go/no-go + alarms) vs sampled characterization (deep PN/jitter). Store configuration/threshold versions and expose event counters for diagnosis.
- SiTime XO example: SiT1602 (e.g., SiT1602BC-72-30S-12.000000)
- SiTime TCXO example: SiT5156 (e.g., SiT5156AI-FK-33E0-25.000000X)
- SiTime OCXO example: SiT5711 (e.g., SiT5711A-KW-0009)
- Abracon OCXO example: AOCJY1-10.000MHZ-E-SW (10 MHz class; multiply/translate as needed)
- ADI network synchronizer: AD9545
- Renesas ClockMatrix system synchronizer: 8A34001
- Microchip jitter attenuator / synchronizer family: ZL30772 (family: ZL3077x)
- Skyworks/SiLabs jitter attenuating clock multiplier: Si5345 (family: Si5342/44/45)
- LVCMOS fanout buffer: TI LMK1C1104
- Multi-standard differential fanout/translator: TI LMK00304
- Glitch-free mux: Renesas 580-01
- Missing-pulse / watchdog building block: ADI LTC6993-1
- Integrated monitors (preferred): use DPLL/cleaner status for LOS/LOLOCK/holdover + counters
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FAQs (SyncE / Ethernet PHY clocks) — troubleshooting without widening the main text
Each answer is intentionally short and executable. The first split is always HF jitter (eye/BER margin) versus LF wander/holdover (sync quality). Use the 3 measurement points consistently: A=source, B=post-cleaner, C=at-PHY.
My link is stable, but SyncE quality alarms still happen—what’s the first “wander vs jitter” check?
Likely cause: LF wander / holdover drift violates quality criteria while HF jitter still allows a clean data eye.
Quick check: Measure freq error vs time at C (long gate) and compare to integrated jitter at C; verify cleaner state (track/holdover) and alarm counters.
Fix: Tighten input qualification + hysteresis/timers, tune tracking/holdover profile, and reduce LF injection (thermal gradients, reference pulling, supply noise into the control loop).
Pass criteria: Holdover/wander metric @C < [LF_budget] over [T_window]; alarms stable (no chatter); HF jitter @C remains < [HF_budget].
Cleaner output jitter looks great, yet PHY occasionally loses lock—what should I probe first?
Likely cause: The deliverable clock at C intermittently degrades (termination/coupling/return-path) even if B looks clean.
Quick check: Probe C with the same method used at B; capture “good vs fail” events; compare ringing/edge integrity and correlate to fanout enable patterns, traffic, and rail noise near fanout/PHY.
Fix: Correct output standard + termination, enforce continuous reference plane, reduce stubs/vias, add dedicated low-noise supply for fanout, and increase spacing/guarding from aggressors.
Pass criteria: No PHY re-lock events over [T_run]; jitter/edge quality @C stays within [HF_budget]; event counters remain flat during stress (load/traffic/temp).
Enabling SSC reduced EMI but increased timing alarms—how to tell if loop BW is the culprit?
Likely cause: SSC modulation lands inside the tracking bandwidth, so it propagates as LF wander (or triggers quality logic) even if HF jitter stays low.
Quick check: Toggle SSC on/off and compare (1) wander/holdover alarms, (2) control-word/phase-error activity, and (3) freq error trend at C. If alarms follow SSC rate/envelope, BW coupling is confirmed.
Fix: Disable SSC in sync-critical domain, isolate SSC to non-critical domains, or switch to a profile that rejects SSC in the LF budget (re-tune tracking BW + qualification thresholds).
Pass criteria: With SSC enabled where allowed, alarms remain stable; freq error @C stays within [LF_budget]; no new SSC-correlated components exceed [spur_limit].
Why does lock pass at room temperature but fail across temperature—what to log and compare?
Likely cause: Temperature changes shift the dominant LF contributors (oscillator stability, thermal gradients, supply sensitivity) or change loop state/qualification behavior.
Quick check: Log and compare (same timestamps): temperature, active reference, profile (track/holdover), control word / phase-error summary, alarm counters, and freq error trend at C.
Fix: Reduce thermal gradients (placement, airflow), isolate oscillator/cleaner supplies, re-tune qualification thresholds, and validate warm-up/settling before declaring “lock good”.
Pass criteria: Across [Temp_range], lock remains stable; drift slope @C < [LF_budget]; alarm counters do not increase under a defined temperature profile.
I meet jitter at the cleaner output, but fail at the PHY pin—what are the top 3 coupling paths?
Likely cause: Additive noise and modulation are injected between cleaner and PHY (distribution path), not inside the cleaner.
Quick check: Compare B vs C under identical conditions; if only C worsens, prioritize these paths: (1) supply injection into fanout/PHY clock input, (2) crosstalk from high-speed lanes, (3) return-path discontinuity (plane split/stub/via).
Fix: Dedicated low-noise rail for fanout, tighter spacing/guarding, shorter controlled-impedance routes, continuous reference plane, and correct termination at the PHY interface.
Pass criteria: |B−C| (HF jitter or spur level) < [Delta_budget]; ringing/overshoot at C < [SI_limit]; no event-correlated alarm increments.
Why does switching from XO to TCXO not improve holdover as expected—what dominates drift now?
Likely cause: The system drift is no longer oscillator-limited; thermal gradient, supply pulling, or tracking/holdover configuration dominates.
Quick check: Force true holdover (remove/qualify out the reference) and measure drift trend at C; compare (a) oscillator-alone behavior at A vs (b) system behavior with cleaner active.
Fix: Reduce temperature gradients near the oscillator, harden the low-noise supply, and ensure the cleaner enters the intended holdover state (profile + qualification + timers) instead of “quietly tracking” a poor input.
Pass criteria: Holdover drift slope @C improves to < [LF_budget] over [T_window], and remains consistent across [Temp_range].
Fanout added—why did jitter worsen even with “low-jitter buffer”?
Likely cause: Additive jitter is amplified by supply noise, wrong termination/standard, or reflections; the buffer spec alone does not guarantee at-PHY performance.
Quick check: Measure at C with fanout enabled vs bypassed; scope for ringing/overshoot; measure fanout rail noise and correlate spur movement with load/traffic.
Fix: Use the correct output standard + termination, shorten/stiffen routes, isolate fanout supply (dedicated LDO + local decoupling), and place fanout close to the PHY clock pins.
Pass criteria: Fanout-on additive delta at C < [Delta_budget]; ringing amplitude < [SI_limit]; no new discrete spur > [spur_limit].
How to quickly tell “measurement artifact” vs real phase noise increase on the board?
Likely cause: Probing, grounding, triggering, or averaging creates “phantom” spurs/jitter that do not exist at the DUT node.
Quick check: Re-run the same node with (1) differential probing, (2) a second instrument or method, and (3) a short ground path; if the anomaly follows the probe setup rather than DUT conditions, it is an artifact.
Fix: Minimize loop area, avoid hidden recovered-clock loops, lock down measurement bandwidth/filters, and validate with an A/B/C consistency check.
Pass criteria: Results are repeatable across two setups within [Repeat_tol]; spur/jitter trends track DUT stress (load/SSC/temp), not probe geometry.
Why does recovered timing look fine until traffic pattern changes—what should I verify in tracking mode?
Likely cause: Recovered reference quality changes with traffic, and the tracking loop follows it (or triggers qualification), impacting LF stability or event behavior.
Quick check: During two traffic patterns, log: input-quality status, phase-error/control-word activity, reference selection changes, and freq error trend at C. If the loop metrics track traffic, the recovered input is not stationary.
Fix: Tighten input qualification rules, limit tracking BW (or move to hybrid profile), and define a deterministic holdover policy for degraded recovered references.
Pass criteria: Across defined traffic patterns, quality state is stable; drift @C < [LF_budget]; no event/alarm bursts occur at pattern boundaries.
What’s the minimal production test to catch “bad clock trees” without full PN equipment?
Likely cause: Many “bad clock trees” fail due to wiring/termination/supply/selection mistakes that can be detected with fast functional checks.
Quick check: At C: (1) frequency accuracy (counter), (2) lock/holdover alarms (status), (3) switchover event capture (scope), (4) rail-noise sanity near fanout/PHY, and (5) A/B/C consistency spot-check on sampled units.
Fix: Add test pads for A/B/C, implement a firmware self-test (force holdover, force switch, log counters), and gate shipment on stable alarms + frequency windows.
Pass criteria: Freq error @C within [Freq_window]; no unexpected alarms; switchover transient within [Event_budget]; sampled deep PN/jitter matches golden within [Golden_tol].
Why does redundancy switchover cause a transient hit even with “glitch-free mux”?
Likely cause: “Glitch-free” prevents runt pulses, but does not guarantee phase-continuous (hitless) switching; downstream PLL/PHY may react to a phase step or gap.
Quick check: Capture C during switchover; quantify phase step/gap and measure reacquisition time; correlate with alarm counters and PHY lock transitions.
Fix: Pre-align references (phase/frequency), use a hitless-capable architecture (dual-path + phase alignment), or holdover-bridge the transition and relax switching thresholds to avoid chattering.
Pass criteria: Switchover phase step/gap @C < [Event_budget]; recovery time < [T_recover]; no service-impacting lock loss under defined switching tests.
What pass criteria should I record to correlate field failures (top 5 metrics)?
Likely cause: Field failures become un-debuggable when only “lock yes/no” is logged; correlation needs HF, LF, and event evidence tied to temperature and profile state.
Quick check: Ensure firmware can log (timestamped): active ref, profile (track/holdover), temperature, alarm counters, and event counters during stress and real traffic.
Fix: Record these 5 metrics as the minimum set: (1) integrated jitter @C, (2) worst spur level @C, (3) holdover drift slope @C, (4) switchover phase step/gap @C, (5) alarms/events counters + profile state + temperature.
Pass criteria: Store the above with thresholds: jitter @C < [HF_budget]; spur < [spur_limit]; drift slope < [LF_budget]; phase step/gap < [Event_budget]; counters stable under defined stress.
Notes: Replace bracketed placeholders ([HF_budget], [LF_budget], …) with system budgets. Keep A/B/C probe pads and telemetry counters for correlation.
