Rate family: 1.000 or 1/1.001
Outputs: {27, 74.25, 148.5} or {74.1758, 148.3516} (representative)
Genlock: {black burst / tri-level / 10 MHz / network-derived} (as applicable)
Jitter window: RMS jitter = X fs, integration [A..B] Hz, condition = [locked/holdover]
Switching: hitless required? {yes/no}; allowed phase transient = [Y]
            

• Better phase alignment to genlock and faster correction of reference phase drift.
• More reference noise passes into the output; output jitter becomes reference-limited.

• Output jitter is improved (more VCO-like), especially in the cleaning region.
• Slower tracking; phase error can accumulate during disturbances, reference steps, or long holdover intervals.

1. Goal: prioritize tracking (phase alignment) vs cleaning (lowest jitter).
2. Reference quality: characterize the source + front-end event timing stability.
3. Endpoint tolerance: define acceptable phase error and jitter window at the endpoint.
4. Scenarios: lock, switchover, reference loss/recovery, and mode transitions.

• Target rates must cover both 1.000 and 1/1.001 families without changing the reference strategy.
• Integer multiply/divide chains cannot land on required rates (after platform constraints are applied).
• Mode switching requires flexible stepping rather than fixed integer ladders.

• A fixed rate family is acceptable (only 1.000, or only 1/1.001).
• Reference selection can be adjusted to allow integer landing (platform-level flexibility exists).
• Lowest spur risk is prioritized over frequency agility.

• Spur positions or density change with fraction ratio / control word updates.
• Spur families appear only in fractional modes; integer modes look significantly cleaner.
• Mitigation direction: adjust PFD/reference rate, modulator mode, fractional denominator, or loop partition (track vs clean).

• Spur spacing or movement correlates with reference frequency or with reference distribution changes.
• Spur often remains even when fractional settings are unchanged.
• Mitigation direction: improve reference isolation, reduce injection paths, and re-check loop bandwidth for reference noise ingress.

• Spurs appear only when a specific divider stage is enabled or when a clock path is routed through certain blocks.
• Spur behavior correlates with configuration of intermediate clocks, not the final output setting alone.
• Mitigation direction: re-plan divider usage, reduce unnecessary intermediate toggling, and verify power/ground isolation between stages.

• Change fractional ratio inside one PLL
• Change reference source (house ref / 10 MHz / network-derived)
• Change output route (fanout / mux / crosspoint)

• Lock policy: allowed unlock? if yes, maximum recovery time.
• Phase continuity: phase-continuous required or phase-step allowed.
• Verification: measure lock events + phase step + spur change before/after switching.

• Routing is long or crosses noisy regions; endpoint edge timing is sensitive.
• Multi-endpoint distribution demands stronger noise immunity and repeatability.
• The receiving domain is high-speed or tightly timed (serializer/reclock boundaries).

• Routing is short, controlled, and local; return path is continuous.
• The endpoint tolerance window is wide enough and termination is unambiguous.
• Fanout count is limited and the topology avoids long stubs.

• Termination placed incorrectly → ringing/overshoot → compare near-source vs near-receiver waveform.
• Differential CM bias missing/shorted → unstable edge timing → verify CM network and receiver bias expectation.
• Return path discontinuity (slot/split) → common-mode conversion → inspect routing crossings and reference plane cuts.

• Impedance target defined (trace + receiver expectation)
• Termination position defined (near RX unless architecture dictates otherwise)
• Differential common-mode requirements satisfied
• Return path continuous (no slot crossings)
• Probe method minimizes measurement-induced artifacts

• Unequal path lengths (trace + vias + connectors)
• Fanout output mismatch and loading differences
• Mux/crosspoint routing asymmetry

1. Architecture first: reduce branching layers and long stubs.
2. Layout second: length-match and keep return paths symmetric.
3. Trim last: use programmable delay/phase only as a controlled escape hatch.

• Multiple endpoints require controlled loading and edge repeatability
• Level translation across standards is required (LVCMOS/LVDS/CML)
• Skew must be bounded across branches

• Routing flexibility, redundancy, or test bypass is needed
• A controlled switching method is available (glitch-free / defined relock)
• Phase continuity requirement is explicitly defined and verified

• Reduces peak EMI by spreading spectral energy.
• Often helpful when a platform faces regulatory or margin pressure.

• Introduces intentional modulation (phase/frequency), changing the “jitter language.”
• In phase-aligned chains (genlock / strict phase continuity), SSC is commonly a hard conflict.

• Platform EMI margin pressure may motivate SSC on the USB3 clock branch
• The goal is peak reduction, not improved timing purity

• SSC must be gated to USB3 only; it must not propagate into SDI/video/genlock branches.
• If branch scoping is not possible, the safer default is SSC OFF until the tree is re-architected.

• Treat the PLL/cleaner supply as a noise-sensitive analog rail (use low-noise regulation and local filtering).
• Keep reference inputs and clock outputs away from high di/dt regions (DC/DC switch node) and aggressive high-speed zones (USB3 lanes).
• Keep return currents predictable; prevent switching currents from sharing the clock return path.

• Correlate endpoint jitter/spurs with power-state changes and with aggressor activity (USB3 active vs idle).
• Compare “before/after” waveforms near receiver and verify the same clock source can appear cleaner after distribution fixes.

• Quick check: REF present + correct family (1/1.001) → profile matches output rate
• Action: confirm reference conditioning/termination and loop BW/holdover mode
• Pass criteria: lock time < ____ s; no lock loss across ____ cycles

• Quick check: verify SSC is OFF on SDI/Video branches; confirm loop profile is not “USB3 SSC profile”
• Action: inspect distribution skew + termination; check reference noise injection vs loop BW
• Pass criteria: phase step = 0 or < ____ ps after switching/lock events

• Quick check: correlate spurs/jitter with USB3 active vs idle and with DC/DC load transients
• Action: re-check return path continuity + keep-out from aggressors; review fractional/1.001 synthesis spurs
• Pass criteria: spur disappears or drops below ____ dBc; SDI error symptom absent over ____ hours

• Phase alignment becomes the top KPI (multi-device coherence)
• Redundancy switching must be controlled (avoid phase steps)
• Holdover matters when the house reference is disturbed

• Loop BW decision is still “track vs clean” (plus switch scenarios)
• Distribution must bound skew and prevent SSC leakage into phase-critical branches

• Low jitter is often the top KPI in standalone mode
• When genlock is used, lock time and phase behavior matter at connect/disconnect
• Thermal gradients can shift behavior; holdover/compensation becomes visible

• Frequency family control (1/1.001) and profile management remain mandatory
• Clean distribution and power-noise control still dominate endpoint jitter

• Skew control becomes explicit (multi-channel alignment)
• Distribution fanout/crosspoint choices matter more than the source oscillator
• Aggressor correlation is common (USB3/DDR activity near clock routes)

• Budget chain remains: ref → cleaner → fanout → endpoint
• Termination and return-path continuity still define real-world jitter