Zero-Delay Buffers (ZDB) are phase-alignment tools: they lock a selected feedback output to the input reference to deliver low-skew, domain-consistent clocks.
The key to success is not “zero propagation delay”, but a clean feedback topology, correct loading/termination, and verification at the receiver with a defined jitter/skew budget.
What is a Zero-Delay Buffer (ZDB)?
A Zero-Delay Buffer (ZDB) is a clock distribution device that uses a feedback-aligned control loop to make a chosen output edge track the input reference edge (phase alignment), while providing multi-output fanout with low inter-output skew.
What a ZDB is great at
Reference-to-output phase alignment (by feedback): aligns the input reference to a defined feedback output path—useful when multiple domains must see a consistent clock edge relationship.
Low output-to-output skew (as a distribution root): provides a clean, repeatable fanout point to feed FPGA/SoC domains, converters, and PHYs with consistent arrival times (PCB routing still matters).
Clock-tree control point: offers a structured way to define “the clock edge that everything aligns to,” especially when a single source must serve multiple subsystems.
What a ZDB does NOT mean
Not “physical zero propagation delay”: real pin-to-pin delay exists; “zero-delay” is about phase relationship achieved by the feedback loop under lock.
Not automatically a jitter cleaner: the output jitter depends on input jitter, the device’s additive jitter, and its jitter transfer behavior; it should not replace a dedicated jitter attenuator when jitter reduction is the primary KPI.
Not a programmable phase-stepper: if the design requires deterministic ps–ns phase steps for calibration/alignment, a dedicated delay/phase device is the correct category.
Common misconceptions (fast corrections)
“The scope shows delay, so ZDB is wrong.”
ZDB targets phase alignment referenced through the feedback output path, not removal of all propagation delay. Measurement reference points and probe loading can change the observed edge position.
“All outputs are perfectly aligned by definition.”
The feedback loop aligns the feedback output path to the input reference. Other outputs are designed for low skew, but board-level routing, loading, and terminations still create real skew.
“ZDB reduces jitter, so no cleaner is needed.”
ZDB output jitter is a combination of input jitter transfer and additive jitter. If jitter reduction is the requirement, select by jitter transfer/phase-noise plots or use a dedicated jitter attenuator.
Terminology (consistent wording for the rest of this page)
Phase-aligned
The feedback output edge maintains a fixed phase relationship to the input reference edge while locked.
Propagation delay
Physical pin-to-pin delay through silicon + package + PCB. It exists even when phase is aligned.
Skew
Edge-to-edge timing difference between two outputs at the measurement points (includes PCB and loading effects).
Additive jitter
Extra timing noise contributed by the device itself, measured at the output beyond what the input already carries.
Diagram: Where a ZDB sits in a clock tree (feedback-aligned distribution root)
When to choose ZDB (and when NOT to)
ZDB selection is best driven by the primary KPI. If the KPI is phase alignment and low skew fanout, ZDB is a strong fit. If the KPI is jitter reduction, programmable phase stepping, or hitless switching, another clock category is usually the correct root component.
Use ZDB if the design needs…
Reference-to-endpoint phase alignment (at least to a chosen “anchor” branch) so multiple domains observe a consistent clock edge relationship.
Low output-to-output skew from a single distribution root to feed multiple devices/subsystems with repeatable arrival times.
Clock-tree definition and repeatability: a clear alignment point that simplifies timing closure across boards or subsystems.
Avoid ZDB if the primary goal is…
Reducing RMS jitter / phase noise to improve converter SNR or SerDes margin: select a jitter attenuator/clock cleaner as the key component.
Deterministic phase steps (ps–ns) for calibration: select a programmable delay/phase device designed for controlled phase trims.
Hitless main/backup switching: select a glitch-free clock mux for failover without runt pulses.
Simple replication only (no phase-alignment KPI): a standard fanout buffer is usually sufficient.
30-second self-check (pick the right root component)
What is the acceptance metric?
If the pass/fail is skew (ps) and edge relationship across branches, ZDB is aligned with the KPI. If the pass/fail is RMS jitter inside an integration window, a clock cleaner is typically the primary choice.
If the system uses SSC or has strict jitter masks, selection must explicitly check jitter transfer behavior. If redundancy and alarms are required, include monitor/mux functions in the clock-tree architecture (without relying on ZDB alone).
Navigation hint (no deep dive here):
For jitter reduction, see the Jitter Attenuators / Clock Cleaners page. For hitless switching, see Glitch-Free Clock Mux. For phase stepping, see Programmable Delay / Phase.
Diagram: Quick decision tree (ZDB vs fanout vs cleaner vs delay vs mux)
How ZDB works: feedback-aligned phase compensation
Key idea (3 truths)
A ZDB aligns an input reference edge to a selected feedback output path using a closed-loop phase correction mechanism.
The loop forces the FB output to match the input phase under lock; other outputs are designed for low skew but are not individually servoed.
Lock behavior (bandwidth, lock time, mode) determines how the ZDB tracks phase wander and how much input noise is transferred to the outputs.
Closed-loop workflow (compare → control → align → distribute)
1) Compare
A phase detector compares REF_IN against FB_OUT (typically through a divider) and generates a phase error signal.
2) Control
The control path (charge pump / filter or equivalent) converts phase error into a stable control quantity for the internal timing core.
3) Align
The timing core (PLL/DLL-style implementation) adjusts phase so the FB path edge aligns to the input reference edge while locked.
4) Distribute
A low-skew output network fans out the aligned clock to multiple ports; board routing and loading still contribute to real skew.
Engineering meaning (the alignment anchor)
Alignment is enforced on the selected FB output path. Choosing the FB output effectively defines “the system anchor edge”.
Other outputs inherit low skew by design, but their real timing includes PCB length, terminations, loading, and measurement points.
The feedback path quality (short, controlled, clean return) directly impacts stability and repeatability of phase alignment.
Common modes (phenomenon → engineering impact)
1× / 2× / N×
Frequency scaling changes where the loop operates and how noise maps to the output; selection must be validated using jitter transfer/phase-noise plots at the intended rate.
Bypass
Some implementations bypass parts of the loop or the core path; phase alignment behavior may change. Always verify lock indication and edge relationship under the intended mode.
Free-run
When reference quality is lost, the output continues with internal timing behavior; phase relationship is no longer guaranteed and will drift.
Holdover
Short disturbances can be bridged with improved continuity, but long-term phase/frequency drift still depends on implementation and conditions.
Feedback (FB) selection: define the alignment anchor correctly
Hard rules
Anchor the most timing-critical branch: choose FB from the domain that must be phase-referenced (often the primary FPGA/SoC clock domain).
Keep FB clean and lightly loaded: avoid stubs, heavy fanout, or non-ideal terminations on the FB branch.
Make FB routing the most controlled path: short, controlled impedance, clean return, no reference-plane slots.
Where “alignment error” really comes from
Internal residual: divider/output path mismatch, internal noise, and control loop residual phase error.
Jitter & phase-noise behavior in ZDB (what gets better, what can get worse)
Three conclusions to avoid the most common mistake
ZDB output jitter is not “one number”: it is the sum of input jitter shaped by jitter transfer plus the device’s additive jitter floor (and any deterministic terms).
Loop bandwidth sets the track vs filter trade-off; the offset region near loop BW can show peaking, which may worsen jitter even when “typical RMS jitter” looks fine.
Budget and compare jitter only with the same integration range and measurement conditions as the endpoint requirement; otherwise results are not comparable.
Break the problem into four measurable parts
Input jitter / phase noise
Noise already present on the reference. Any spread-spectrum modulation, supply-coupled wander, or upstream synthesis spurs belong here.
Jitter transfer
The frequency response that maps input phase noise to output. This is where loop bandwidth and any peaking show up.
Additive jitter floor
Noise contributed by the ZDB itself. At some offsets, this term dominates even with a clean input.
DCD (duty-cycle distortion)
Edge symmetry error that can appear as timing margin loss. It is not random jitter, but it can impact endpoints sensitive to edge placement.
Loop bandwidth: what “tracks” and what “filters”
In-band: output phase follows the loop’s controlled behavior; low-frequency wander may be tracked rather than removed.
Out-of-band: the loop no longer corrects phase; output behavior is dominated by the device noise floor plus residual input coupling.
Near loop BW: check for peaking. Peaking can worsen phase noise at specific offsets and inflate integrated RMS jitter.
Define the endpoint KPI: RMS jitter window, jitter mask, or timing margin (setup/hold) requirements.
Lock down the integration range: use the same offset limits and filters used by the endpoint spec and by the datasheet jitter number.
Start from input noise: map the reference PN/jitter into the same window.
Apply jitter transfer: identify offset regions that track, attenuate, or peak; do not assume flat behavior.
Add the floor: include additive jitter/PN floor; verify whether it dominates at high offsets.
Separate deterministic terms: DCD and spurs/SSC modulation should be validated with explicit pass/fail criteria.
Datasheet must-read items
Jitter transfer / phase-noise plots (look for loop BW and peaking).
Additive jitter with the stated integration range and output format.
DCD / edge symmetry specs and measurement conditions.
Supply sensitivity notes and recommended filtering (PI affects phase noise).
Diagram: Jitter transfer vs offset frequency (loop BW, in-band/out-of-band, floor, peaking)
Skew, phase alignment, and duty-cycle distortion (DCD)
Start by locking down the measurement definition (otherwise numbers are not comparable)
Skew measurement point: driver pin, receiver pin, or probe tip — select one and keep it consistent.
Edge and threshold: define rise/fall edge and the same threshold (Vth) for all channels.
DCD definition: duty-cycle target/spec and the window used to measure tHIGH vs tLOW.
Output-to-output skew: where it comes from
Inside the IC: output path mismatch and distribution network imbalance.
On the PCB: trace length mismatch, impedance/termination differences, and reflection-driven edge movement.
Loading: different receiver input capacitance and biasing move the edge crossing time.
Measurement system: channel delay mismatch and inconsistent thresholds can masquerade as “skew”.
Input-to-output phase alignment: what “aligned” really means
Under lock, the loop minimizes phase error between REF_IN and the selected FB output path (often via a divider).
Residual alignment error includes divider/loop residual and FB trace/termination effects.
Alignment is enforced on the FB path; other outputs depend on internal matching plus PCB routing.
DCD (duty-cycle distortion): why it matters and how to read it
DCD shifts the effective edge position and reduces timing margin at endpoints sensitive to edge symmetry (DDR, sampling clocks, SERDES-related references).
Datasheets may specify Duty Cycle (e.g., 45–55%), DCD (ps), or separate rise/fall timing; confirm load and termination conditions.
Board reflections can “create” apparent DCD by altering the threshold crossing time differently on rising vs falling edges.
Feedback topology & PCB routing (the #1 real-world success factor)
The feedback loop quality determines whether “phase alignment” exists on the real board
The FB output choice defines the alignment anchor for the entire clock tree.
Poor FB routing injects reflection and delay uncertainty into the loop, causing drifting skew or unstable lock behavior.
Using the FB branch as a heavy fanout path turns the “measurement edge” into a moving target.
FB output selection: a practical priority ladder
Most timing-critical domain: the clock branch that must hold a defined phase relationship to the reference.
Most uncertain link: the branch with the longest path or most variability that benefits from being the alignment anchor.
Most stable load/termination: the branch with clean termination and predictable edge shape.
Best routing opportunity: shortest, least-via path with a continuous return reference.
Rule of thumb
Choose FB from the branch that should be “the system anchor edge”, then protect that branch from stubs, heavy loading, and return-path discontinuities.
Do (make FB predictable)
Keep FB short, straight, and impedance-controlled; minimize vias.
Maintain a continuous return reference; avoid plane splits and slots.
If a split is unavoidable, keep the FB stub the shortest branch and keep the anchor edge clean.
Use the FB branch as a light-load “measurement edge”, not a heavy fanout node.
Keep termination consistent and predictable for the FB-selected output standard.
Don’t (the common failure patterns)
A T-split with a long stub before returning to FB.
FB routing across reference-plane discontinuities (plane split/slot).
Long parallel runs next to switching nodes or noisy rails.
Using the FB output to drive multiple receivers with uncertain terminations.
Adding ad-hoc test points/jumpers that create impedance steps on the FB path.
The 5 most common pitfalls (expand for quick diagnosis)
1) FB output used as a heavy fanout node
Symptom: “locked” but skew drifts with loading or when a receiver is connected. Quick check: compare alignment with and without the heavy load on the FB branch. Fix: keep FB branch lightly loaded; move fanout after the anchor, or create a dedicated anchor branch.
2) Long stub on the FB branch
Symptom: alignment appears sensitive to probing, temperature, or small routing changes. Quick check: inspect TDR/edge shape for reflection near the threshold crossing. Fix: shorten the stub; ensure the anchor edge sees a clean, terminated path.
3) FB trace crosses a plane split / slot
Symptom: intermittent jitter/skew spikes or mode-dependent instability. Quick check: locate the return path discontinuity under the FB trace. Fix: reroute over a continuous reference plane; avoid crossing split boundaries.
4) Termination differences across outputs (especially the FB-selected output)
Symptom: DCD and skew degrade when the receiver or termination changes. Quick check: compare edge crossing time under different terminations. Fix: standardize termination on the anchor path; keep endpoint conditions close to datasheet test conditions.
5) Measurement definition drift (probe delays mistaken as skew)
Symptom: skew changes when channels are swapped or when different probes are used. Quick check: run a same-signal-to-two-channels test to quantify channel delay mismatch. Fix: calibrate channel delays and keep threshold/edge definition fixed for all measurements.
Diagram: FB loop routing — correct vs wrong (stub, split plane, heavy load)
Output standards, terminations, and loading effects
One diagram, three rules (why terminations and loading change skew/jitter in practice)
Termination → reflection → threshold-crossing drift: a “clean” edge at the receiver produces stable phase/skew numbers.
Load is not just resistance: input capacitance (and probe capacitance) slows edges and shifts crossing time.
Uneven loading breaks predictability: a heavily loaded output can inflate output-to-output skew even when the IC’s typical skew is low.
LVCMOS vs differential (LVDS/HCSL/LVPECL): what matters for ZDB results
LVCMOS (single-ended): large swing and stronger sensitivity to return-path inductance; SSN/ground bounce can shift edge timing under simultaneous switching.
LVDS (differential): receiver-side 100 Ω termination stabilizes edge shape; asymmetric routing/loading can still move crossing time.
HCSL/LVPECL (differential): termination style affects return current and reflection; mismatch shows up as phase measurement drift and DCD changes.
What “wrong termination” looks like in timing results
Symptom
Phase/skew numbers drift with probe choice, cable length, or small routing differences.
Quick check
Inspect the waveform near Vth: ringing or multiple crossings often translate into “effective jitter”.
Fix
Apply the intended termination, minimize stubs, and keep the receiver/load consistent with the system configuration.
Fanout loading allocation (template) and acceptance checkpoints
Capture per output
Standard (LVCMOS/LVDS/HCSL/LVPECL)
Termination style and location
Equivalent load (R + input capacitance)
Trace length and stub presence
Acceptance examples (X/Y are system-derived)
Skew impact: Δt_skew (heavy-load vs light-load) < X ps
Phase drift: phase measurement drift < Y ps across “probe present/absent”
Waveform sanity: single threshold crossing at Vth (no Vth re-crossing)
Measurement reminder: probe capacitance is a load
A probe can slow edges and move threshold crossing time. Use consistent probing methods, record the probe/load condition, and avoid comparing results measured under different loading.
Diagram: driver → line → receiver (common terminations and loading)
Power integrity, PSRR, and EMI/SSC interactions
How supply noise becomes phase noise (practical view)
Supply ripple can modulate sensitive internal delay/control nodes in PLL-based devices. That modulation shows up as small edge-position movement at the outputs (effective phase noise/jitter). Low-noise rails and correct local decoupling are required to reproduce datasheet timing performance on the board.
The “power 3-piece kit” (actionable)
Low-noise LDO (or clean rail)
Feed PLL/analog rails from a low-noise source; keep switching ripple away from the most sensitive supply pins.
Bead / π filter (isolation)
Add impedance between noisy rails and sensitive nodes; prevent high di/dt currents from sharing the same path as the PLL rail.
Local caps (minimum loop)
Place decoupling right at the supply pins, keep the loop tight, and route the return over a continuous reference plane.
Datasheet must-read checkpoints (PSRR and test conditions)
Supply sensitivity / PSRR-related curves (or jitter vs supply ripple notes, if provided).
Recommended power filtering and decoupling networks for PLL/analog rails.
Jitter/skew test conditions (rail voltage, termination, loading, and measurement setup).
Operating modes that change loop behavior (bypass/holdover/free-run) and their power sensitivity.
SSC boundary (keep it evidence-based)
Confirm whether SSC is passed through, reshaped, or attenuated by checking device documentation for “SSC support / pass-through / modulation transfer”.
If a downstream clock domain must not see SSC, treat SSC as a configuration boundary: disable SSC on that chain or isolate with the appropriate clock function block.
Acceptance template: verify SSC depth/rate at the receiver remains within system allowance under the locked operating mode.
Simultaneous switching can inject supply/ground movement that shifts threshold crossing time. A quick isolation test is to hold unused outputs static and compare jitter/skew; if results improve, reduce simultaneous switching intensity, strengthen local decoupling, and keep return paths continuous.
Clean: where jitter/PN must be reduced before distribution.
Align: where phase alignment is defined (ZDB feedback output is the reference).
Distribute: where fanout and routing constraints dominate skew.
One ZDB vs multi-stage distribution (when the tree must branch)
Single-stage ZDB: best when endpoints are local, fanout count is modest, and “which output is aligned” is unambiguous.
Multi-stage: preferred when endpoints are far apart, the board is partitioned (RF/ADC vs digital), or when a second level must absorb routing/termination variability.
Anti-pattern: using a ZDB as an unlimited root while ignoring upstream quality, loading balance, and return-path integrity.
Multi-domain alignment strategy (define what “aligned” means)
Hard-aligned domains
Domains that require a fixed phase relationship or deterministic edge arrival (synchronous sampling / tight edge alignment).
Low-skew domains
Domains that only need low output-to-output skew (phase may be arbitrary but must be consistent and stable).
Frequency-only domains
Domains that only require accurate frequency; phase can drift without violating function.
Owner: which block is responsible (system / board / device configuration)
Redundancy skeleton (architecture only)
Use monitoring (missing pulse / frequency offset / lock detect) to decide when a reference is unhealthy.
Insert a switch block for main/backup selection; when hitless behavior is required, the switch must be glitch-free (implementation details belong to the mux page).
Decide the switching layer: switching near the root impacts more domains; switching deeper limits blast radius but may complicate domain management.
Diagram: layered clock tree with optional cleaner, monitoring, and redundancy paths
Bring-up & measurement: how to verify skew and jitter correctly
Three things that must match (otherwise numbers are not comparable)
Same reference point: pin-to-pin, connector-to-connector, or testpad-to-testpad — define it and keep it constant.
Same loading: receiver connected, termination in place, and identical probing/fixture condition.
Same acquisition method: multi-channel simultaneous vs single-channel sequential; keep trigger and bandwidth consistent.
Skew measurement steps (1–2–3–4)
Define the measurement points (and document them): probe pads, connectors, or pins — do not mix.
Prefer simultaneous acquisition: use a multi-channel instrument to avoid channel-to-channel timebase ambiguity.
Keep trigger/threshold consistent: identical Vth, bandwidth limit, and acquisition settings across channels.
Freeze the loading condition: termination and receiver state must match the real system state you are validating.
Jitter / phase-noise checklist (make the number meaningful)
Integration range: RMS jitter depends on the frequency-offset window — always record the window.
Instrument noise floor: verify the measurement is not dominated by instrument/fixture limits.
Probe/fixture impact: probing can add capacitance and noise; compare only when probing is identical.
Mode matters: bypass/free-run/holdover can change transfer behavior and apparent jitter.
Common traps (most bring-up mistakes live here)
Long ground leads (adds inductance) → ringing near Vth → false “jitter”.
Probe capacitance changes edge rate and crossing time → skew appears to drift.
Long coax / uncontrolled stubs create reflections that look like timing noise.
Different bandwidth/threshold/trigger settings across channels invalidate comparisons.
Debug flow (symptom → top 3 checks)
No lock / no output
Power rails and mode pins (correct operating mode)
Feedback path continuity and loading on the feedback output
Input reference frequency/amplitude within allowed range
This chapter turns the ZDB topic into an execution-ready list. The goal is not “pretty clocks”, but
repeatable phase alignment + low skew under real PCB loading, real power noise, and real measurement constraints.
A) Before schematic: requirements & budgets
Define the objective: input↔output phase alignment (ZDB) vs output fanout vs jitter cleaning (not ZDB).
Set a skew budget: Δt(skew) < X ps (X comes from endpoint timing margin / setup-hold window).
Set a jitter budget: choose the integration range used by the endpoint spec (SerDes / ADC / FPGA I/O).
Pick output standards early (LVCMOS/LVDS/HCSL/LVPECL) to avoid “late-stage termination surprises”.
Decide SSC policy: which clock chains may carry SSC, and which must be SSC-free.
B) Schematic: feedback, modes, and protection pins
Select the feedback output intentionally: align the most timing-critical domain (or the longest/most sensitive path).
Keep the FB path “clean”: avoid placing FB on a heavily loaded output; do not share FB with stubs.
Review mode pins: bypass / free-run / power-down behavior; confirm safe behavior when REF is missing.
Plan output enables: bank-level OE can simplify bring-up isolation and production A/B tests.
Add test hooks: a dedicated measurement pad for REF, FB, and at least 1–2 representative outputs.
C) PCB: routing, returns, and supply isolation
Route the FB loop short and single-purpose: controlled impedance, no forks, minimal vias, solid return.
Match output lengths only where it matters (same domain / same receiver class); avoid “blind matching everywhere”.
Terminate correctly per standard; avoid stubs that create reflections → edge jitter → “fake phase drift”.
Place decoupling at each VDD pin with tight loop area; isolate analog PLL supply if the part provides VDDA.
Keep switching nodes away (buck SW, motor PWM, fast GPIO bundles). Clock return integrity beats “nice-looking traces”.
D) Bring-up & production: verify what matters
Lock confirmation: verify REF present, outputs toggling, and “lock stable” across temperature and supply corners.
Skew verification: measure with consistent reference points; do not mix probes/cables without calibrating delay offsets.
Jitter verification: use the same RMS window as the endpoint spec; account for instrument floor and probing noise.
Corner checks: heavy-load vs light-load outputs, max toggle SSN cases (especially LVCMOS).
Production screen: frequency / lock / representative skew sample / temperature soak sample (fast but meaningful).
These part numbers are provided to speed up datasheet lookup for ZDB power/edge integrity validation.
Selection must follow the system budget and the ZDB datasheet recommendations.
Use value as a starting point; tune by waveform at the receiver and the line impedance.
Applications & IC selection notes (ZDB-focused)
ZDB selection is not about chasing a single “ps” number. It is about aligning the right domain through the right feedback topology,
then preserving that alignment through standards, loading, power integrity, and verification.
A) Multi-domain FPGA/SoC clock distribution
Align the domain that defines the global timing reference (fabric / DDR PHY / converter sampling edge).
Use OE banking to isolate domains during bring-up and to reduce simultaneous switching noise.
Measure skew at the receiver pins, not at “convenient pads”.
B) Data-acquisition boards (synchronized sampling)
Keep the FB path representative: align the sampling-clock path that is most sensitive to phase error.
Route differential clocks tightly and keep terminations correct to avoid reflection-induced edge jitter.
Verify the RMS jitter window required by the sampling performance target.
C) Server / storage reference clock fanout with ZDB mode
Choose “ZDB/Fanout” buffers that explicitly specify ZDB mode behavior and SSC compatibility.
Pay attention to output standards (HCSL) and on-chip terminations to avoid board-level resistor sprawl.
Validate with the platform’s jitter mask and measurement method (instrument floor matters).
Selection dimensions (what to screen first)
Alignment & skew
Output-to-output skew (and the test condition).
How feedback is formed (external FB pin vs internal pad feedback).
Banking/OE options for isolating domains.
Jitter behavior
Additive jitter / phase-noise plots (not a single headline number).
Jitter transfer / tracking behavior vs offset frequency.
SSC pass-through / spread-compatible statements.
I/O standards & power
Output standard and termination expectations (LVCMOS/LVDS/HCSL/LVPECL).
Supply partitioning (VDDA vs VDD) and recommended filtering.
Fail-safe behavior on missing REF / power-down states.
When NOT to use ZDB
If the primary goal is jitter attenuation/cleanup (rather than phase alignment), prioritize a jitter attenuator/cleaner class device instead of forcing a ZDB to act like one.
ZDB part-number examples (starting points only)
The list below is intentionally mixed: classic LVCMOS ZDBs for general clock distribution and modern “ZDB/Fanout” buffers for platform reference clocks.
Always confirm lifecycle, package, and the measurement conditions used for skew/jitter in the datasheet.
Vendor
Part number
Outputs / standard
Notes (ZDB-relevant)
Official link
Renesas
2305A / 2305B
1:5, LVCMOS
Classic PLL ZDB; small package; good for simple clock trees.
Practical rule: treat FB routing and measurement setup as first-class design objects.
Most “ZDB didn’t work” cases are FB contamination, loading asymmetry, or measurement-induced artifacts.
These FAQs are designed to close long-tail debugging without expanding the main text.
Every answer follows the same 4-line, testable structure: Likely cause / Quick check / Fix / Pass criteria.
1Why is my “zero-delay” output still phase-shifted on the scope?›
Likely causeZDB aligns the feedback output to the input reference (after divider/mode effects). “Zero” is not physical propagation delay, and the compared nodes may not be the aligned pair.
Quick checkConfirm the device is locked (LOL/LOCK pin or status). Measure REF vs FB output using the same instrument channel setup (same probe type, same cable delay calibration).
FixUse the intended FB output as the alignment anchor (and keep it lightly loaded). Verify mode (1×/2×/N×/bypass) and divider settings match the clock plan.
Pass criteriaAfter lock, the measured phase difference between REF ↔ FB output is stable and within ≤ X ps over the intended temperature/supply range (X derived from system timing margin).
2Why do outputs have different skew even with the same trace length?›
Likely causeSkew at the receiver is dominated by loading/termination/return-path differences and reflection-induced threshold crossings—not just copper length. Internal output path mismatch can add a smaller baseline.
Quick checkCompare waveforms at the receiver: look for ringing/overshoot and multiple threshold crossings. Swap two outputs onto the same load/receiver (if possible) to see if the problem follows the routing/load.
FixUnify termination strategy per standard, eliminate stubs, keep reference planes continuous, and avoid heavy loading on one branch. Match electrical conditions (standard + termination + load) before matching length.
Pass criteriaWith matched electrical conditions, output-to-output skew at the receiver pins is ≤ X ps (X from endpoint setup/hold margin), and does not change by more than Δ ≤ Y ps across load/temperature corners.
3Why does skew change when I probe the clock?›
Likely causeThe probe adds capacitance, inductive ground loop, and/or impedance discontinuity, changing edge shape and the time the waveform crosses the receiver threshold (“measurement-induced skew”).
Quick checkCompare readings using (a) 10× passive probe, (b) low-C active probe, and (c) coax + proper termination (50 Ω where appropriate). If results move, the probe is part of the circuit.
FixMeasure with a consistent, low-loading method and calibrate channel/cable delays. Prefer receiver-side measurement points with controlled impedance and minimal stubs.
Pass criteriaChanging the measurement method changes the reported skew by ≤ X ps, and the chosen method produces repeatable results (repeatability σ ≤ Y ps over N captures).
4Why does enabling SSC change the measured jitter/skew?›
Likely causeSSC intentionally modulates frequency, so edge position “moves” over time. Measurement window, triggering, and integration range can convert SSC modulation into apparent jitter/skew changes.
Quick checkMeasure with identical conditions: same trigger strategy, same time gate, and the same RMS jitter integration band. Verify whether the ZDB mode is SSC pass-through or reshapes modulation.
FixIf SSC must be present, validate that the device and endpoints tolerate it; otherwise disable SSC on sensitive chains. Use measurement modes designed for modulated clocks (consistent gating and reference).
Pass criteriaWith SSC enabled, the endpoint spec is still met: jitter/skew remain within budget (e.g., RMS jitter ≤ X ps over the defined band; skew drift ≤ Y ps over the defined observation time).
5Why does one output look noisier than others (same buffer)?›
Likely causeThat channel has a different load/termination/routing environment (heavy load, longer stub, worse return path), or it is in a bank with higher simultaneous switching noise (SSN).
Quick checkSwap the suspect output with a “good” output while keeping the same routing/load (if feasible). Measure supply noise near the buffer during worst-case toggling to correlate with phase noise/jitter increase.
FixNormalize termination/load, reduce stubs, improve return path continuity, and strengthen local decoupling / supply isolation. Avoid placing the feedback output on a noisy/heavy-loaded channel.
Pass criteriaChannel-to-channel jitter difference is ≤ X ps (same integration band), and waveform integrity at the receiver meets overshoot/ringing targets (e.g., no multiple threshold crossings).
6Why does the ZDB fail to lock intermittently at power-up?›
Likely causeREF amplitude/quality is marginal during ramp, mode pins are floating, reset/enable timing violates requirements, or supply noise/undervoltage causes the PLL to miss acquisition.
Quick checkScope REF and supply rails at power-up. Log LOCK/LOL transitions across repeated cold starts. Check that configuration pins have explicit pull-ups/pull-downs and that REF is stable before release.
FixStabilize REF and supplies (use recommended filtering/LDO), fix pin strapping, and sequence enable/reset per datasheet. If provided, use a clean lock-detect gate before enabling sensitive endpoints.
Pass criteriaCold-start lock success is 100% over N cycles; lock time is ≤ X ms; no false lock-loss events in the observation window.
7Why does changing load/termination move my measured edge timing?›
Likely causeTermination changes reflection behavior and edge slope, shifting the moment the waveform crosses the threshold (“timing by threshold crossing”), which appears as edge timing movement.
Quick checkAt the receiver, check for overshoot/ringing and double crossings. Compare the same node with correct vs incorrect termination to isolate reflection-driven timing errors.
FixImplement standard-correct termination, minimize stubs, and add small series damping where appropriate to critically damp the edge without violating amplitude/common-mode limits.
Pass criteriaEdge timing at the receiver is insensitive to minor termination/load variation: Δt change ≤ X ps, and the waveform shows a single clean threshold crossing per edge.
8Why does the feedback output choice change the whole tree alignment?›
Likely causeA ZDB aligns the selected FB output to the input. Changing the FB output changes the alignment anchor and moves the phase of other outputs relative to that anchor.
Quick checkMeasure phase offsets of multiple outputs relative to REF for FB option A vs FB option B. If the FB output stays closest to REF while others shift, the anchor effect is confirmed.
FixChoose the FB output that represents the timing-critical domain (or the cleanest/most stable path). Keep FB routing short, stub-free, and lightly loaded.
Pass criteriaThe critical domain meets the alignment target (REF↔critical output ≤ X ps), and non-critical domains stay within their skew budget (Δt ≤ Y ps).
9Why does supply ripple show up as “phase wander”?›
Likely causeSupply noise couples into the PLL/VCO/control path, creating low-frequency phase modulation (wander) or discrete spurs correlated with ripple frequency.
Quick checkMeasure rail ripple near the device under load and correlate its frequency with observed phase wander/spurs. Temporarily power from a low-noise source to see if wander reduces.
FixUse a low-noise LDO (per recommendation), add bead/π filtering where appropriate, improve local decoupling loop area, and isolate the clock supply/return from switching current loops.
Pass criteriaPhase wander peak-to-peak is ≤ X ps over the defined observation time, and ripple-correlated spurs fall below the system’s allowed limit (e.g., spur amplitude ≤ Y dBc if applicable).
10Why is duty-cycle distortion worse after routing across layers?›
Likely causeLayer transitions and asymmetries (via stubs, return discontinuities, unequal rise/fall loading) distort edge symmetry, increasing DCD at the receiver.
Quick checkCompare rise vs fall times and high vs low pulse widths at the receiver. Check for return-path breaks (plane splits, slots) near layer transitions.
FixReduce layer transitions on timing-critical paths, keep return planes continuous, and maintain symmetric routing/termination for the chosen standard. Remove or backdrill via stubs when needed.
Pass criteriaMeasured duty cycle at the receiver meets the endpoint tolerance (e.g., DCD ≤ X% or duty error ≤ Y ps at the target frequency).
11Can a ZDB be used as a jitter cleaner? What’s the quick tell?›
Likely causeZDBs are optimized for phase alignment / low skew, not guaranteed jitter attenuation. Depending on loop behavior, they may track input jitter rather than clean it.
Quick checkLook for a datasheet jitter transfer / attenuation plot and a clear “jitter cleaner” positioning. If the plot/claim is absent, assume it is not a cleaner and validate experimentally.
FixIf jitter cleanup is the primary goal, use a dedicated jitter attenuator/cleaner in the hierarchy, then use ZDB/fanout devices for alignment/distribution.
Pass criteriaAt the endpoint, total RMS jitter is ≤ X ps over the specified integration range, with margin (guardband) across PVT corners.
12What’s the fastest production test to catch bad ZDB behavior?›
Likely causeProduction time is limited, so the test must target failure modes that dominate escapes: no lock / unstable lock / skew out of spec / ripple-coupled wander.
Quick checkRun a minimal screen: (1) frequency present, (2) lock indicator stable, (3) representative skew check on a fixed fixture, (4) quick rail sanity near the device under worst-case toggling.
FixStandardize the fixture and cable delays, define a golden board baseline, and enforce consistent measurement windows. Add a temperature-soak sample plan if the application is timing-sensitive.
Pass criteriaScreen completes within takt time; lock pass rate is 100%; sampled skew is ≤ X ps; no lock-loss events during the observation window (e.g., T ≥ Y s).
Note: X/Y thresholds must be derived from the system timing/jitter budget and verified at the receiver pins under representative loading.
