DSC — Digital Signal Controllers
Index of device/link classes, modulation/encoding, EQ & CDR, clocking, key specs, design hooks, protocol mappings, test & validation, quick cheats, and selection tips for SerDes/backplane/display/camera/Die-to-Die links.
Device / Link Classes
Low–Mid-Speed SerDes (0.5–6 G)
In-vehicle/industrial camera & display bridges; AC-coupled with 8b/10b or self-clocking codes.
Multi-Gbps (6–32 G NRZ)
PCIe Gen3, SATA, HDMI 2.0, JESD204B with CTLE + TX pre-emphasis.
High-Speed Backplane (25–56 G PAM4/NRZ)
25G/100G/200G-KR with FEC and adaptive EQ.
Ultra-High-Speed Display/Camera
DP/HDMI 2.1, MIPI D/C-PHY, SLVS-EC; lane aggregation and deskew.
Cable Extender / Protocol Bridge
Camera→FPGA, SoC→Display with retiming/reshaping (retimer/redriver).
Die-to-Die / Chiplet SerDes
UCIe/BoW/proprietary PHYs for short-reach, low-power, deterministic latency.
Modulation & Encoding
NRZ (PAM2)
Simpler and often more noise-robust; common ≤28 G.
PAM4
2 bits/UI; requires FEC/stronger EQ/tighter jitter—50G/100G mainstream.
Line Coding
8b/10b, 64b/66b, 128b/130b and scrambling—balance clocking vs overhead.
Link Training / Adaptation
Adaptive TX FFE, RX CTLE/DFE with alignment/comma markers.
Equalization & CDR
TX FFE (Pre/Post Cursor)
Cancel channel ISI via pre-/post-cursor taps.
RX CTLE
Boost highs / tame LF tails with programmable poles/gains.
RX DFE
Use past decisions to cancel post-cursors; guard against error propagation.
Clock Data Recovery (CDR)
Lock, align and track jitter with proper loop bandwidth for JTOL.
Retimer vs Redriver
Retimer re-samples/cleans jitter; redriver adds EQ/gain only.
Clocking & Reference
Reference Clock (SSC/Non-SSC)
External/embedded; SSC cuts EMI but eats jitter budget.
Jitter Budget
Total jitter = RJ + DJ; directly impacts UI eye and BER.
Embedded vs Out-of-Band
Embedded (PCIe/Ethernet) vs D-PHY with separate clock lane.
Key Specs & Selection
Line Rate & Coding
Effective throughput = rate × coding efficiency (128b/130b ≈ 98.46%).
Eye Opening & BER
Target BER (e.g., 1e-12/1e-15); PAM4 multi-eye templates.
Jitter & JTOL
Random/periodic/DDJ metrics and CDR tracking capability.
Channel Budget
Nyquist insertion loss, return loss, NEXT/FEXT across PCB/connectors/cables.
EQ Range
TX tap counts + RX CTLE/DFE depth and step granularity.
Latency & Determinism
Fixed-latency options, alignment markers and deskew FIFOs.
Power / Voltage / Thermal
mW/Gbps; PAM4 tends higher power—mind package thermals.
ESD / EMI
Port ESD levels, radiated/conducted margins and SSC support.
Design Hooks & Pitfalls
Channel Modeling
Estimate S-params; fN=DataRate/2 (NRZ) or /4 per PAM4 eye.
Ref Clock Cleanliness
Phase-noise/jitter passes into CDR; avoid PSU spurs in CDR BW.
AC Coupling & Common-Mode
Cap sizing by min transition density; meet RX common-mode range.
Termination & Impedance
100 Ω diff, length/impedance match; simulate vias/connectors.
Routing & Return Path
Tightly coupled pairs, continuous reference; symmetric via pairs.
EQ Tuning Order
RX CTLE → TX FFE fine → RX DFE; avoid noise over-equalization.
Multi-Lane Sync
Length-match + deskew FIFOs; keep byte boundaries via markers.
EMI Suppression
Shielding/chassis GND, SSC, TX swing/slew control, CM chokes.
Power Integrity (PI)
Split domains; clean analog with LDO; dense local decoupling.
Compliance Hooks
PRBS/BERT, eye templates and training/register script exports.
Protocols & Scenarios
Camera → Processor
SLVS-EC/MIPI C/D-PHY or GMSL/FPD-Link; consider retimers and coax PoC.
ADC/DAC Front-End (JESD204B/C)
Subclass 0/1/2; deterministic latency and multi-channel phase align.
Backplane / Rack Ethernet
25/50/100G-KR with RS-FEC and adaptive EQ for margin.
Peripherals: PCIe/SATA/USB3/DP/HDMI
Choose cables/connectors and plan certification tests.
Die-to-Die / Chiplet
Short-reach, low-swing links targeting latency/power/area.
Test & Validation
PRBS & Stress Injection
PRBS7/9/11/23/31 and SJ/RJ to validate JTOL and recovery.
Eye & Bathtub
UI vs BER plots to assess closure probabilities.
Channel S-Parameters
S21/S11/Sdd/Scc for insertion/return/crosstalk; de-embed & EQ estimates.
Compliance Suite
PCIe/HDMI/DP/JESD official templates with archived records.
Quick Cheats
UI (Unit Interval)
UI = 1/DataRate (NRZ); PAM4 shares UI per eye but tighter levels.
Effective Throughput
NRZ@10G + 64b/66b ≈ 9.846 Gbps; PAM4@25G/lane → ~50 Gbps raw.
Nyquist Loss Guidance
≤20–28 dB at Nyquist eases convergence (protocol/EQ dependent).
Tuning Order
RX CTLE → TX FFE → RX DFE; track eye/BER and save golden regs.
How to Choose
Link Length / Medium
PCB vs twinax/coax/twisted pair—consult vendor channel budgets.
Protocol Compatibility
PCIe presets, HDMI EQ profiles and JESD subclasses.
Power / Thermal
mW/Gbps & θJA; PAM4 often needs stronger cooling.
Toolchain
Models/S-params, reg scripts, auto-training APIs and BERT/eye tooling.
Reliability
ESD, temp grades (industrial/auto) and long-term supply plans.
