SoC / Application Processor Systems
Core architectures, memory & boot, graphics/video/AI, high-speed I/O, OS & software, security & reliability, power & thermal, packaging & HW design, applications, key specs, and design hooks.
Cores & Architecture
ARM Cortex-A Series
Out-of-order, multi-level cache, MMU; mainstream for industrial HMI and edge compute.
x86 SoC Platforms
Rich PC/industrial ecosystem with PCIe, graphics and storage; HMI, gateways, edge servers.
RISC-V High-Performance
RV64GC + Vector with custom ISA options spanning low power to high compute.
Heterogeneous Multi-Core
big.LITTLE scheduling and DSP/MCU companions for real-time vs. application split.
SoC Interconnect (AXI/ACE/CHI, CCN/CMN/NOC)
Plan coherency, bandwidth and latency across fabrics and mesh interconnects.
Memory & Boot
DDR Controller
Data rate/width, ECC options and SI with length matching for DDR3/4/LPDDR4/5.
Non-Volatile Boot
XIP/high-speed boot via NOR/OSPI; bad-block management for NAND; eMMC/SD options.
Cache & Coherency
SMP/AMP configurations with shared/private cache policies.
Secure Boot / ROM Bootloader
Signatures/hashes, anti-rollback and root-of-trust hardening.
Graphics / Video / AI
GPU Graphics
2D/3D UI, compositor pipelines and multi-display layouts.
Video Codec (VPU)
H.264/H.265/AV1 encode/decode lanes, 4K/8K frame rates and low-latency modes.
NPU / AI Accelerator
TOPS, INT8/FP16, operator coverage/SDK and heterogeneous scheduling.
Display/Camera I/O
MIPI DSI/CSI, HDMI/DP, LVDS/eDP with ISP and image enhancement.
High-Speed I/O & Connectivity
PCIe Controller
Root complex/endpoint roles, switching/expansion and NVMe/accelerator support.
Ethernet MAC & TSN
1G/2.5G/10G with PTP hardware timestamping and embedded switching/TSN.
USB (2.0/3.x/Type-C/DRD)
Host/device/OTG modes, UASP storage and camera support.
General Peripherals
I²C/SPI/UART/I³C, SDIO/QSPI/OSPI for management and peripheral bridging.
Industrial Field Interfaces
CAN-FD and safety-island offload via external controllers/bridges.
OS & Software Stack
Linux / Yocto / Buildroot
Mainline/LTS kernels, driver stacks, DeviceTree and PREEMPT_RT.
RTOS & Virtualization
RTOS on Cortex-R/M companions; KVM/Xen/ACRN for partitioning and determinism.
Secure Runtime (OP-TEE / TrustZone-A)
Split secure/normal worlds for key storage and security services.
Containers & Edge
Lightweight orchestration and remote fleet ops/OTA.
Security & Reliability
TrustZone-A / TEE
Trusted execution with secure storage, key management and trusted updates.
Crypto & Identity
TRNG, RSA/ECC, TPM/SE for TLS, secure boot and measured boot.
Functional Safety Ready
Lockstep/safety islands with ISO 26262/IEC 61508 collateral.
Reliability (ECC/RAS)
DDR ECC, parity, error injection and system RAS features.
Power & Thermal
PMIC Cooperation (Sequencing & DVFS)
Multi-rail order/soft-start/shutdown with dynamic voltage/frequency scaling.
Power Domains & Clocks
Local power-gating/clock-gating and standby wake sources.
Thermal Design
TJ/θ metrics, throttling policies and cooling (airflow/heatsink).
Packaging & HW Design
Packaging (BGA/LGA/Fan-Out)
Ball pitch/stack/escape strategies with SI/PI planning.
DDR Layout/Eye
Length matching/impedance/fly-by; simulate corners and margins.
High-Speed Differential (PCIe/USB/SerDes)
Insertion/return loss budgets, crosstalk and reference-clock cleanliness.
EMI/ESD & Isolation
Power-tree/ground partitioning and interface isolation/protection.
Application-Focused
Industrial Gateway / Edge
GbE + TSN, containerized workloads, hardware crypto acceleration.
Robotics / Machine Vision
Multi-CSI with VPU/NPU, real-time scheduling and TSN switching.
HMI / Multimedia
Multi-4K display, GPU composition, touch/voice interfaces.
IVI / Domain Controller
PCIe storage/accel, automotive Ethernet/buses and safety collateral.
Energy / Power Automation
Multiple NICs with PTP/SyncE and ruggedized reliability.
Key Specs & Selection
Compute & Memory
Freq/core count, DMIPS/MHz, L2/L3 sizes, DDR rate/width/ECC.
Multimedia & AI
GPU/VPU/NPU performance, codec formats/frame-rates and AI TOPS/ops.
I/O
PCIe lanes, USB/Ethernet count & rates, display/camera ports.
Security
Secure boot/TEE, crypto engines, TPM/SE and lifecycle support.
Power & Thermal
TDP/peaks, DVFS strategies and thermal solutions.
Supply & Ecosystem
Mainline support, BSP completeness, 10–15y longevity and docs/community.
Design Hooks & Pitfalls
First-Article DDR Bring-Up
SI sims + training; read/write eye, fly-by and length calibration.
Power-Up Sequence & POR
PMIC sequencing/reset trees, brown-out and wake scenarios.
Storage Endurance & FS
eMMC/NAND bad-blocks, wear and journaling (UBI/EXT4 params).
Secure Chain
Cert/key injection, debug-port lockdown and OTA rollback plans.
Realtime & Determinism
PREEMPT_RT tuning, CPU affinity/isolation and IRQ pinning.
Fleet / DevOps
Monitoring/logging, A/B images and device identity management.
Compliance & Certification
EMI/safety plus Ethernet/PTP/TSN/USB/HDMI conformance plans.
Quick Pairings
Edge-AI Gateway
Cortex-A76/A55 big.LITTLE + NPU, 2×GbE TSN, NVMe over PCIe, Yocto and TPM.
Multi-Screen HMI
Quad Cortex-A53 with GPU/VPU, dual DSI/eDP, touch, secure boot and quiet PMIC.
Industrial Vision
RISC-V/ARM multi-core, multi-CSI-2, VPU/NPU and TSN switch with HW timestamping.
Automotive Domain Controller
Cortex-A78AE/lockstep, LPDDR4-ECC, PCIe switch, automotive GbE and ASIL docs.
