Open-drain fits multi-voltage domains and large fan-out; each domain uses its own pull-up and wired-OR is easy. Push-pull is acceptable only in a single, well-controlled domain with verified VIH/VIL margins across temperature. Budget rise time versus C_bus and confirm the sink capability; never cross-drive domains with push-pull.

Combine trip accuracy, measurement jitter, ripple, and temperature drift into a single margin. As a rule of thumb, set V_hys ≥ 1.5× ripple peak-to-peak. Specify both V_IT− and V_IT+ budgets and verify under slow ramps and extremes; release timing must remain consistent at worst-case corners.

t_GLITCH targets microsecond-scale events such as connector bounce, EFT spikes, and load-step induced transients. Use pulse injection to sweep amplitude and width over the B–C µs range and log RESET jitter. Acceptance is zero spurious edges and a minimum blocked pulse width greater than the worst observed disturbance.

Measure worst-case startup for clock oscillation, PLL lock, regulator settling, storage initialization, and peripheral discovery at extreme temperatures. Multiply the slowest observed time by 2–5× for t_RST(min). Ensure t_Delay aligns the unified release point so the system never starts “half awake.”

Slow dv/dt accentuates reference drift and comparator dynamics, increasing chatter near thresholds. Increase V_hys, lengthen t_GLITCH, and consider more conservative t_Delay. Validate specifically at 0.1–0.3 V/ms; segment fan-out or reduce C_bus when rise-time becomes marginal.

Insert ESD protection and a series-R/RC on the MR trace; never wire MR directly to a general GPIO. Enable debouncing and a long-press state machine, and apply startup-inhibit until clocks and rails are stable. Route away from switching nodes and control return paths to limit ground bounce coupling.

Use per-domain pull-ups, limit C_bus, and add buffering for long traces or heavy loads. Verify 10–90% rise time versus the tightest receiver VIH requirement and EMI goals. Confirm sink capability for worst pull-up values and scale margins when adding connectors or off-board wiring.

Create a single authority by wired-OR or active-OR of all relevant PG signals, then add a deterministic delay block. Size the delay to the slowest stabilizing domain—clock, PLL, or power group. The goal is one authoritative release, not competing sources with conflicting polarities or timings.

Convert reference/comparator drift in ppm/°C into millivolts at the rail, then add ripple and ADC/jitter terms to form V_margin. Validate V_IT−/V_IT+ across the temperature matrix and document worst-case corners. Keep release timing stable under combined dv/dt and temperature stress.

Use push-pull in a single domain with low C_bus when you need a sharp edge, minimal delay, or cannot tolerate pull-up variability. Before use, verify that every receiver tolerates the asserted level across temperature and supply corners, and confirm the design does not require wired-OR behavior.

Treat the external supervisor as the higher-level arbiter. Its release must occur after internal BOD/POR thresholds and timing are safely met. Align polarities and ensure the external release window encompasses the slowest internal path so there is no oscillation or partial initialization.

Match output type and I_sink, V_IT−/V_IT+ accuracy, V_hys, t_Delay, t_RST(min), and t_GLITCH(min), plus MR features, I_q/drift, package, and AEC-Q grade. After field matching, re-run the full validation matrix to confirm behavior under dv/dt, temperature, noise, and fan-out stress.