Reset Delay & One-Shot Guide for Multi-Rail Power-Good

Q: Why does an external RC delay drift more on slow power ramps?

Slow ramps increase effective R·C because dielectric absorption is more visible and comparator thresholds are crossed gradually. The “k” factor grows versus step inputs, stretching t_DELAY. Validate at 0.1 V/ms across temperature corners; if release is late, choose a tighter delay bin or a programmable delay to calibrate.

Q: When should I choose PG-OR vs PG-AND?

Pick PG-OR when any critical rail arriving first should start pre-release, then unify with a fixed t_DELAY. Choose PG-AND when all mandatory rails must be good before release—safer but slower. With random arrivals, size t_DELAY ≥ P95(Δt) plus guard and add t_blank to suppress short glitches.

Q: How do I avoid conflicts between reset stretch and WDT grace?

Make the stretch window shorter than WDT grace minus file system/stack mount time and margin: t_stretch ≤ t_WDT_grace − t_mount − margin. If a WDT IRQ can occur early, gate one-shot generation on a “mount-done” flag or add a brief compress window to avoid double resets.

Q: How should a one-shot mask re-triggers against button bounce?

Debounce before the one-shot and add a re-trigger mask ≥ worst-case bounce. Detect edges, not level, and guarantee a minimum pulse width t_OS. Use a parallel timer for long-press detection; never rely on repeated one-shots caused by bouncing keys to avoid multi-reset behavior.

Q: How do I prevent back-power when converting OD to push-pull across domains?

Prefer OD with pull-up into the receiving domain. If PP must cross domains, insert a series resistor and a Schottky clamp to the lower-voltage rail, or buffer with a tolerant Schmitt receiver. Verify leakage in power-off states to avoid back-power through ESD structures or protection diodes.

Q: With random rail arrivals, which statistic should size t_DELAY?

Measure the inter-arrival Δt distribution across builds and conditions, then choose t_DELAY ≥ P95(Δt) + guard. If boot latency matters, stretch early rails and compress late ones to a unified release; add t_blank to ignore <5 ms PG spikes and chatter.

Q: How do I buffer and partition a large reset fanout?

Segment by domain and buffer near the loads. Use Schmitt inputs and OD with near-end pull-ups to keep rise times short; shorten or segment long traces. Budget total line capacitance and verify t_rise against VIH; create per-domain branches where load characteristics differ.

Q: External RC vs I²C/OTP programmable delay—how to pick for consistency?

External RC is inexpensive and flexible but varies with temperature/aging and dielectric spread. I²C/OTP provides tighter fleet alignment and easier bin control but requires a configuration flow. For volume builds, prefer I²C/OTP; keep RC for prototyping or coarse bins, with a defined write window.

Q: How do I keep t_OS inside target across −40…125 °C?

Characterize the one-shot core over temperature; specify [t_min, t_max] and a re-trigger mask. If RC-based, use stable dielectrics and derate values; for digital one-shots, lock the reference clock. Validate with worst-case bounce and long-press waveforms at temperature corners.

Q: How should I choose t_blank and thresholds when PG glitches are frequent?

Start with t_blank ≥ longest observed glitch (often 5–10 ms) and add hysteresis or a Schmitt front-end. Place blanking before the release arbiter to suppress both pre- and post-release spikes. Log filtered events to confirm that field glitch frequency is trending down.

What It Solves

Multi-Rail Arrival Uncertainty

Principle: Release reset only after rails are jointly “good”, then add a unified delay to decouple rail skew from system bring-up.

Action: Compute Δt = max(t_PG,i) − min(t_PG,i); set t_DELAY ≥ P95(Δt)+margin. Use PG-OR for pre-release tagging, unify at RESET.

Validation: Randomize ramp (10/1/0.1 V/ms). Verify release jitter ≤ t_jitter-max; no double-release events.

Pre-WDT Grace & Stretch/Compress

Principle: Give slow peripherals and filesystems deterministic room before watchdog supervision kicks in.

Action: Stretch when PG is early but init is slow: set t_HOLD ≥ t_init(max). Compress when PG is late but system is fast: unify releases to a single gate.

Validation: Measure init milestones (CLK lock, storage ready). Confirm WDT starts after hold window.

Button Noise / One-Shot Debounce

Principle: Convert noisy edges into a single deterministic reset pulse immune to bounce.

Action: Choose t_OS ≥ t_bounce,max + margin and implement re-trigger masking. Add input t_blank for ESD/EMI blips.

Validation: Inject 0.5/1/2/5/10 ms bursts—expect single reset, no chattering.

Traceable Reset Events

Principle: Record minimal event set to identify the true initiator of a reset.

Action: Log source={PG-OR|MR#|WDT-IRQ} + timestamp + rail_mask. Harden storage (brownout-safe).

Validation: Brown-out replay; ensure logs survive partial power loss or fail gracefully.

Key Definitions

Timing Terms

t_PG (PG valid), t_RESET-assert (reset low), t_HOLD (stretch), t_DELAY (release delay), t_OS (one-shot pulse), t_blank (glitch blanking).

Rule: t_DELAY aligns releases; t_HOLD preserves system grace; t_OS > input bounce; t_blank > P99(glitch).

Output Type & Level

Open-Drain (domain-flex, wire-OR) vs Push-Pull (strong edges). Pull-up must match the receiver domain (1.2/1.8/3.3/5 V).

Don’t: push-pull across domains without buffers; avoid back-power/ESD clamps conduction.

Validation Angles

Ramps 10/1/0.1 V/ms; temp −40/25/85/125 °C; V_DD ±10%; glitch 0.5–10 ms. Measure jitter and ensure single-shot behavior.

Logs: source + timestamp + rail_mask; resilient to brown-out.

Delay / One-Shot Families

Fixed Delay (internal RC / laser-fused bins)

When: Volume builds that need tight lot-to-lot repeatability and no external parts.

Choose: Select by Delay-bin (e.g., 40/80/120 ms). Prefer “longer-bin + compress” over “short-bin + hope”.

BOM note: “Reset delay bin = 80 ms (±10%) or next longer; allow cross-brand pin-compat.”

Programmable Delay (RC / I²C·PMBus / OTP)

RC: t ≈ k·R·C, with k drifting vs temp/slope. Combine tolerances: σ² = σR²+σC²+σk².

I²C/PMBus/OTP: best for fleet consistency; define power-on default and program timing (avoid premature release).

BOM note: “Delay via register 0x1A, code=0x07 (100 ms), locked in OTP for MP; dev builds allow I²C override.”

One-Shot Pulse (comparator+RC / monostable)

Design: edge detector → monostable; add re-trigger mask and input t_blank for EMI/ESD blips.

Rule: t_OS ≥ t_bounce,max + margin and t_OS ≤ t_system_budget.

BOM note: “One-shot 30–50 ms; mask re-triggers within t_OS; input t_blank ≥ P99(glitch).”

Stretch vs Compress Strategy

Stretch when PG is early but init is slow → set t_HOLD ≥ t_init(max); watchdog starts after hold.

Compress when PG is late but system is fast → unify to a single release gate; avoid long “dead-ready” time.

Executable Formulas

RC sizing: pick R·C = t_target/k, where k∈[0.6,1.3] by ramp & temp; verify 3σ corners.
Register bins: choose the next longer bin → trim by compress; log programmed value to NVM for FA.

Multi-Rail Strategy Matrix (PG-OR / PG-AND)

Topology & Upgrade Path

Single → Dual → Multi-rail: add only one decision block per step to keep validation manageable and readable.

PG-OR vs PG-AND

PG-OR: any critical rail first → pre-release prep, then unify at RESET with delay; good for asymmetric rails.

PG-AND: all must-rails valid → release; more robust but slower; good for symmetric or strongly coupled peripherals.

Statistical Sizing

Measure Δt = max(t_PG,i) − min(t_PG,i) across ramps/temps; set t_DELAY = P95(Δt) + margin; per temp-zone if needed.

Glitch / Jitter Control

Set t_blank ≥ P99(glitch-width) and t_blank < t_OS/2 to avoid conflicts with the one-shot window.

Validation Matrix (Lab-ready)

Ramp: 10/1/0.1 V/ms · Temp: −40/25/85/125 °C · VDD: −10%/Typ/+10% · Glitch: 0.5/1/2/5/10 ms.

Pass if release jitter ≤ target, no double-release, and PG-OR/AND path behaves deterministically under injected glitches.

Interfaces, Fanout & Level Domains (OD/PP, Pull-up, Back-Power)

Open-Drain First (Cross-Domain Friendly)

Anchor the level to the receiver domain with a pull-up; supports wire-OR and avoids pushing current into a lower V_DD.

Rule: Pull-up to the most restrictive receiver (e.g., 1.8 V). Verify VIH(min) at the destination. Typical R_pull=10–47 kΩ by load/cable.

Rise-time: τ = R_pull·C_load; ensure 2.2·τ ≤ edge budget (e.g., ≤100 µs).

Push-Pull Boundaries & Safeguards

Use PP only in a single domain when sharp edges are mandatory. Cross-domain PP risks back-power via ESD diodes or clamps.

Mitigation: Series resistor 22–100 Ω + Schottky to VDD_RX; or convert to OD at source and pull-up at receiver.

Design note: Ensure PP never drives above VDD_RX during RX brown-out.

Fanout (Reset Tree)

For multiple targets, use a buffer/fanout IC (Schmitt input; OD/PP-configurable outputs) to avoid edge slowing.

Budget C_total=Σ(C_in,i+C_trace). Select R_pull so that 2.2·R_pull·C_total ≤ t_rise,max.

Topology: Supervisor → Schmitt buffer (level domain) → leaves.

ESD/EMI & False-Trigger Immunity

Long reset lines / external buttons: add RC deglitch/debounce and Schmitt input.

Blanking: t_blank > P99(glitch width) and t_blank < t_OS/2 to avoid window conflicts.

Back-Power Avoidance Checklist

Any net crossing domains: default to OD + pull-up to receiver.
PP across domains must include series R + Schottky to VDD_RX.
Failing domain must not sink current via protection diodes (measure I<100 µA).
Board DRC: enforce “OD-to-receiver-domain” rule on reset nets.

P5-1 · Pull-up Resistor Sizing

Given C_total and target rise-time t_rise, choose R_pull ≤ t_rise/(2.2·C_total). Add noise margin → pick 10–47 kΩ practical range.

P5-2 · Cross-Domain PP Safeguard

R_series=33–68 Ω limits surge; Schottky (anode→net, cathode→VDD_RX) clamps overshoot and blocks back-power during RX brown-out.

P5-3 · Fanout Buffer Choice

Input: Schmitt; Output: OD or selectable OD/PP; t_pd ≤ 50–150 ns. Ensure total chain jitter fits reset budget.

Validation Matrix

Cable: 5/30/80 cm; Harness types; Temp −40/25/85 °C; Inject EMI 0.5/1/2/5/10 ms.

Pass: no false resets; t_rise/t_fall within budget; no back-power > 100 µA during brown-out.

BOM Remark Template

“RESET output = OD; pull-up to 1.8 V (10 kΩ) at receiver; Schmitt input at buffer; cross-domain PP (if any) requires 47 Ω series + Schottky to VDD_RX.”

Parameters & Design Recipes (RC, Error Budget, Re-trigger)

RC Delay Approximation

Model: t ≈ k·R·C; k varies with slope/temperature/input topology.

Empirical k: 0.6–1.3 (lower at fast ramps/low temp; higher at slow ramps/high temp).

3σ Error Budgeting

Contributors: R and C tolerances, temp drifts (α_R, α_C), aging Δ, and σ_k.

Combine as σ_total² = σ_R² + σ_C² + σ_k² + σ_temp² + σ_aging². Design so t stays within [t_min, t_max] with ≥99.7% coverage.

One-Shot & Re-trigger Mask

Pulse width: t_OS ∈ [t_min, t_max].

Mask: ≥ t_bounce,max (10–30 ms typical). Add input t_blank > P99(glitch), but keep t_blank < t_OS/2.

Budget: Ensure t_OS ≤ system allowance to avoid blocking bring-up.

Programmable Delay (I²C/PMBus/OTP)

Power-on default: keep safe hold (e.g., 100 ms).

Write timing: program after clock/NVM stable; avoid early release.

Locking: OTP for MP; dev keeps register override; record final code to NVM for FA.

Worked Example — 200 ms Target

k_nom=0.9 → R·C ≈ 0.222 s. Try C=1 µF (post-bias 0.7–0.85 µF), R≈261 kΩ (E96). If 3σ violates window, move to 280–330 kΩ or raise C to 1.5 µF and lower R.

Validate across ramps (10/1/0.1 V/ms), temps (−40/25/85/125 °C), aging (HTS 168 h).

Executable Recipes

P6-1 · RC back-solve: R·C = t/k_nom → pick E24/E96 + temp/aging headroom.
P6-2 · 3σ design: translate drifts to σ; iterate R/C or switch to programmable bins.
P6-3 · One-shot mask: mask ≥ t_bounce,max + margin; prove single pulse under injected glitches.
P6-4 · Register binning: choose longer bin then compress; log final code in NVM.

BOM Remark Template

“RC delay: R=274 kΩ (E96), C=1.5 µF X7R (post-bias ≥1.1 µF), k_nom=0.9; 3σ passed. Dev: I²C code 0x08 (120 ms) override allowed; MP: OTP lock.”

Validation & Mass Production

Operating Matrix

Ramp rates: 10 / 1 / 0.1 V/ms (±5% jitter); include ultra-slow to amplify RC error.
Temp × Volt: −40/25/85/125 °C × −10% / Typ / +10%.
PG glitches: 0.5 / 1 / 2 / 5 / 10 ms at pre-/post-release windows.
Button bounce: 10–30 ms to verify single one-shot.

Measurement & Logs

Track t_PG,i, t_RESET-assert, t_HOLD, t_DELAY, t_OS, t_blank.

Release jitter metric: P95−P5(t_RELEASE) ≤ t_jitter-max.

Log: Ramp(set/actual) · Temp · Volt · Bin/Reg · C_total · Tags(PG-OR/AND, MR#, WDI) · Pass/Fail + scope ID.

Executable Steps

Slope scan: 3 ramps × 3 volts × 4 temps; N≥20 per point → jitter distribution.
Slow ramp & DC-bias: vary dielectric/cap (1.0/1.5/2.2 µF) to see k/C effects.
Glitch sweep: inject 0.5→10 ms near release; t_blank must suppress all.
Button+EMI: one-shot must single-fire; t_OS in window.
Back-power: brown-out RX domain; I_back ≤ 100 µA.

Pass Criteria

Release jitter: P95−P5 ≤ target (single-rail ≤5 ms; multi-rail ≤10–15 ms).
Single action: one press → one reset (N≥100, 0 error).
One-shot window: t_OS ∈ [t_min, t_max] (e.g., 30–50 ms).
Glitch immunity: 0.5–10 ms PG glitches fully blocked by t_blank.
Back-power: I_back ≤ 100 µA; no reverse-lighting.
Lot consistency: 3 lots pass with different capacitors/vendors.

BOM Remark Template

“Delay-bin = 200 ms ±15%; t_blank = 5 ms; one-shot = 40 ms; OD output, pull-up to 1.8 V; PG-OR aggregate; I_back ≤ 100 µA.”

Cross-Brand Selection & Migration

Anchor Features

Delay-bin (fixed) · External RC (continuous) · I²C/OTP (programmable) · Output (OD/PP) · MR#/WDI · AEC-Q100.

Pick timing method → check level/fanout → confirm automotive grade.

Migration Path

Pin-to-Pin: same package/pins; verify jitter & back-power.
Functional prox.: choose longer bin → compress at release.
Param gap fix: add series R + Schottky (PP⇄OD), buffer for fanout, adjust t_blank/thresholds.

TI

TPS3808 — External CT for adjustable delay; easy reuse of one RC formula across SKUs.
TPS3890 — Precision threshold + configurable delay (often with CT); variants for OD/PP outputs.
TPS3850 — Supervisor + Watchdog; supports delay + window WDT for pre-WDT grace + one-shot combo.
TPS386000 — Multi-rail supervisor; ideal for PG-OR/AND aggregation and unified release.

ST

STM7032 / 705 / 708 — Fixed delay bins, low quiescent; good for tight-consistency MP.
STM6705 — Button management/debounce variants; stable MR# → one-shot path.
STM1815 — µP reset, fixed delay; broad supply, suitable as volume anchor.

NXP

MC339xx-derived reset devices — Threshold + delay options aligned with NXP power/body ECUs.
P3T + monitor combo path — Temperature-aware reset strategy (temp-gated delay / lock).

Renesas

ISL880xx / ISL884x — Low-Iq supervisors with multiple delay options; portable from portable to auto-lite.
R3152x — Tighter env. ratings and thresholds across series; good automotive alignment.

onsemi

NCP301 / NCP302 — Fixed-delay voltage monitors; mature supply for delay-bin anchoring.
NCP308 / NCP306 — Adjustable/strengthened timing variants; useful for hard-edge power rails.

Microchip

MCP130 / MCP131 · MCP111 / MCP112 — Simple fixed delays; BOM-minimal fallback devices.
MCP809 / MCP810 · MCP101x — POR / reset families with rich threshold bins for p2p swaps.

Melexis

MLX803xx platform reset/monitor block — Automotive SoC ecosystem; reuse for aligned reset policies.

Migration Notes

When P2P unavailable: pick next-longer bin, compress at release; convert PP→OD with series R + Schottky, add buffer to restore edge.

BOM Remark (Short)

“Delay-bin 200 ms ±15%, OD output to 3.3 V; PG-OR unified stretch 100 ms; AEC-Q100 G1 required.”

Small-Batch Procurement Hooks

Sample Kit (150–500 ms)

Fixed delay ×2 bins (≈200 ms / ≈400 ms).
Programmable ×1 (External RC or I²C/OTP).
One-shot ×1 (debounce + single-fire reset).
Use “longer bin → compressed release” as universal fallback.

Risk Checklist & Fixes

Delay-bin mismatch → write a tolerance strategy (longer-bin + unified release).
PP-only output → cross-domain/back-power risk → add series R + Schottky or switch to OD + pull-up in RX domain.
External RC → temp/aging not budgeted → apply 3σ stack & dielectric selection (X7R/X5R/Tant/Film).
Programmable → default-on/when-to-write unclear → hold-reset-before-write or write-then-release script.

CSV Template (Copy & Use)

Fields cover delay method, output domain, level compat, and automotive grade.

Brand,PN,Delay-bin(ms),Output(OD/PP),VDD(V),VIH/VIL(V),AEC-Q100(Grade),t_blank(ms),one-shot(ms),MR#/WDI,RC?(Y/N),P2P?(Y/N),Notes
TI,TPS3808,Prog(CT),OD,1.8–6.0,0.6/1.2,G1,5,40,MR#/WDI,Y,N,"RC formula reuse across SKUs"
ST,STM1815,200,PP,2.7–5.5,0.7VDD/0.3VDD,G2,5,40,MR# only,N,Y,"Fixed bin; volume anchor"
onsemi,NCP302,400,OD,2.3–10,0.65VDD/0.35VDD,G2,5,40,MR# only,N,Y,"OD simplifies cross-domain"
Microchip,MCP131,200,PP,2.7–5.5,0.8VDD/0.2VDD,–,5,40,–,N,Y,"Simple POR reset"
Renesas,ISL884x,Prog(OTP),OD,1.8–5.5,0.7VDD/0.3VDD,G1,5,40,WDI,Y,N,"Programmable fleet consistency"

Need a cross-brand short list aligned to your rails and fanout?

Submit your BOM (48h cross-brand)

Edge Cases

Slow Ramp + Low Temp

At −40 °C with 0.1 V/ms, effective C ↑ and k ↑ → t_DELAY stretches.

Test: dielectric swap (1.0/1.5/2.2 µF; X7R/X5R/Tant/Film).
Fix: tighter bin or programmable, add t_blank; use longer-bin→compressed release.

Reset Tree Fanout

Large fanout slows the edge and causes misinterpretation at far nodes.

Test: add line capacitance / long-trace model; observe t_rise vs thresholds.
Fix: Schmitt buffer, OD + near-end pull-up, shorten/segment fanout.

Two-Stage Stretch

Peripherals need reset-hold → release → secondary stretch for handshake.

Test: PG-AND with peripheral ready gating.
Fix: one-shot ×2 or delay + one-shot; finish FS/stack mount before exit.

Manual Reset Long/Short

Bounce/long-press can re-trigger.

Test: 10–30 ms bounce + 0.5–2 s long-press.
Fix: pre-debounce + one-shot min width + re-trigger mask ≥ max bounce.

Brownout / UV Chatter

Short cycles near thresholds induce reset oscillation.

Test: inject 0.5/1/2/5/10 ms PG glitches before/after release.
Fix: t_blank + PG latch; switch OR/AND strategy if needed.

Documentation & Handoff

Event Logging (minimal field set)

Fields: { ts, source, rail, action, t_delay_ms, t_os_ms, result }
source: PG_OR / PG_AND / MR# / WDT_IRQ / BROWNOUT
rail: VDD_CPU · VDD_IO · VDD_ANA · ...
result: RELEASED / STRETCHED / COMPRESSED / DENIED
Tip: buffer at edge gateway and merge with FAULT counters.

{"ts":"2025-11-08T09:12:31Z","source":"PG_OR","rail":"VDD_IO","action":"RELEASED","t_delay_ms":220,"t_os_ms":40,"result":"STRETCHED"}
{"ts":"2025-11-08T09:15:02Z","source":"MR#","rail":"GLOBAL","action":"ASSERT","t_delay_ms":200,"t_os_ms":40,"result":"SINGLE_SHOT"}

Traceability (what to record)

Delay-bin: target vs measured at 25 °C (e.g., 200 ms → 207 ms).
Output: OD/PP; Pull-up: value/domain/location (near/far).
RC: R/C part numbers, tolerance, dielectric (X7R/X5R/film), empirical k range.
Temp sampling: −40/25/85/125 °C stats of t_DELAY / t_OS (P50/P95).

Handoff Package (what to include)

Timing captures: 10/1/0.1 V/ms, annotate t_blank / t_delay / t_os.
Scope scripts: channel map, triggers, cursors; CSV export naming rules.
BOM CSV: template below; Alternatives: P2P, delay-bin tolerance, OD↔PP fixes.
Versions & signature: hw_rev / fw_rev / reset_profile_rev + digest.

BOM CSV Template (copy/paste)

Brand,PN,Delay-bin(ms),Method(Fixed/RC/I2C/OTP),Output(OD/PP),PullUp(kΩ@V),VDD(V),VIH/VIL(V),t_blank(ms),t_os(ms),AEC-Q100(Grade),MR#/WDI,Rail(s),Notes
TI,TPS3808,Prog(CT),OD,10@3.3,1.8–6.0,0.6/1.2,5,40,G1,MR#/WDI,VDD_IO,"RC formula & k-range"
ST,STM1815,200,Fixed,PP,–,2.7–5.5,0.7VDD/0.3VDD,5,40,G2,MR#,GLOBAL,"Fixed bin; production anchor"
onsemi,NCP302,400,Fixed,OD,22@3.3,2.3–10,0.65VDD/0.35VDD,5,40,G2,–,VDD_IO,"OD is cross-domain friendly"
Renesas,ISL884x,Prog(OTP),OD,10@3.3,1.8–5.5,0.7VDD/0.3VDD,5,40,G1,WDI,VDD_CPU,"Programmable consistency"
Microchip,MCP131,200,Fixed,PP,–,2.7–5.5,0.8VDD/0.2VDD,5,40,–,–,GLOBAL,"Simple POR reset"

Need a manufacturing handoff pack and cross-brand alternatives?

Submit your BOM (48h cross-brand)

Frequently Asked Questions

Why does an external RC delay drift more on slow power ramps?

Slow ramps increase effective R·C because dielectric absorption is more visible and comparator thresholds are crossed gradually. The “k” factor grows versus step inputs, stretching t_DELAY. Validate at 0.1 V/ms across temperature corners; if release is late, choose a tighter delay bin or a programmable delay to calibrate.

When should I choose PG-OR vs PG-AND?

Pick PG-OR when any critical rail arriving first should start pre-release, then unify with a fixed t_DELAY. Choose PG-AND when all mandatory rails must be good before release—safer but slower. With random arrivals, size t_DELAY ≥ P95(Δt) plus guard and add t_blank to suppress short glitches.

How do I avoid conflicts between reset stretch and WDT grace?

Make the stretch window shorter than WDT grace minus file system/stack mount time and margin: t_stretch ≤ t_WDT_grace − t_mount − margin. If a WDT IRQ can occur early, gate one-shot generation on a “mount-done” flag or add a brief compress window to avoid double resets.

How should a one-shot mask re-triggers against button bounce?

Debounce before the one-shot and add a re-trigger mask ≥ worst-case bounce. Detect edges, not level, and guarantee a minimum pulse width t_OS. Use a parallel timer for long-press detection; never rely on repeated one-shots caused by bouncing keys to avoid multi-reset behavior.

How do I prevent back-power when converting OD to push-pull across domains?

Prefer OD with pull-up into the receiving domain. If PP must cross domains, insert a series resistor and a Schottky clamp to the lower-voltage rail, or buffer with a tolerant Schmitt receiver. Verify leakage in power-off states to avoid back-power through ESD structures or protection diodes.

With random rail arrivals, which statistic should size t_DELAY?

Measure the inter-arrival Δt distribution across builds and conditions, then choose t_DELAY ≥ P95(Δt) + guard. If boot latency matters, stretch early rails and compress late ones to a unified release; add t_blank to ignore <5 ms PG spikes and chatter.

How do I buffer and partition a large reset fanout?

Segment by domain and buffer near the loads. Use Schmitt inputs and OD with near-end pull-ups to keep rise times short; shorten or segment long traces. Budget total line capacitance and verify t_rise against VIH; create per-domain branches where load characteristics differ.

External RC vs I²C/OTP programmable delay—how to pick for consistency?

External RC is inexpensive and flexible but varies with temperature/aging and dielectric spread. I²C/OTP provides tighter fleet alignment and easier bin control but requires a configuration flow. For volume builds, prefer I²C/OTP; keep RC for prototyping or coarse bins, with a defined write window.

How do I keep t_OS inside target across −40…125 °C?

Characterize the one-shot core over temperature; specify [t_min, t_max] and a re-trigger mask. If RC-based, use stable dielectrics and derate values; for digital one-shots, lock the reference clock. Validate with worst-case bounce and long-press waveforms at temperature corners.

How should I choose t_blank and thresholds when PG glitches are frequent?

Start with t_blank ≥ longest observed glitch (often 5–10 ms) and add hysteresis or a Schmitt front-end. Place blanking before the release arbiter to suppress both pre- and post-release spikes. Log filtered events to confirm that field glitch frequency is trending down.

What hidden AEC-Q100 checkpoints apply to reset/delay paths?

Expect ESD/EMI-induced mis-triggers, temperature drift of t_DELAY/t_OS, and supply dips causing chatter. Provide corner data and latch-up immunity notes, showing blanking suppresses brief PG spikes. Batch-sample delay bins across temperatures to demonstrate stability for automotive grades.

How should the BOM document tolerance when swapping delay bins?

Declare an explicit strategy: “use the next longer bin with compressed release,” or “shorter bin with one-shot stretch.” Record OD/PP and pull-up domain, t_blank and t_OS. Flag whether pin-to-pin is true and re-test the Δt distribution before production release.

Reset Delay & One-Shot

Reset Delay & One-Shot

What It Solves

Multi-Rail Arrival Uncertainty

Pre-WDT Grace & Stretch/Compress

Button Noise / One-Shot Debounce

Traceable Reset Events

Key Definitions

Timing Terms

Output Type & Level

Validation Angles

Delay / One-Shot Families

Fixed Delay (internal RC / laser-fused bins)

Programmable Delay (RC / I²C·PMBus / OTP)

One-Shot Pulse (comparator+RC / monostable)

Stretch vs Compress Strategy

Executable Formulas

Multi-Rail Strategy Matrix (PG-OR / PG-AND)

Topology & Upgrade Path

PG-OR vs PG-AND

Statistical Sizing

Glitch / Jitter Control

Validation Matrix (Lab-ready)

Interfaces, Fanout & Level Domains (OD/PP, Pull-up, Back-Power)

Open-Drain First (Cross-Domain Friendly)

Push-Pull Boundaries & Safeguards

Fanout (Reset Tree)

ESD/EMI & False-Trigger Immunity

Back-Power Avoidance Checklist

P5-1 · Pull-up Resistor Sizing

P5-2 · Cross-Domain PP Safeguard

P5-3 · Fanout Buffer Choice

Validation Matrix

BOM Remark Template

Parameters & Design Recipes (RC, Error Budget, Re-trigger)

RC Delay Approximation

3σ Error Budgeting

One-Shot & Re-trigger Mask

Programmable Delay (I²C/PMBus/OTP)

Worked Example — 200 ms Target

Executable Recipes

BOM Remark Template

Validation & Mass Production

Operating Matrix

Measurement & Logs

Executable Steps

Pass Criteria

BOM Remark Template

Cross-Brand Selection & Migration

Anchor Features

Migration Path

TI

ST

NXP

Renesas

onsemi

Microchip

Melexis

Migration Notes

BOM Remark (Short)

Small-Batch Procurement Hooks

Sample Kit (150–500 ms)

Risk Checklist & Fixes

CSV Template (Copy & Use)

Edge Cases

Slow Ramp + Low Temp

Reset Tree Fanout

Two-Stage Stretch

Manual Reset Long/Short

Brownout / UV Chatter

Recommended topics you might also need

Documentation & Handoff

Event Logging (minimal field set)

Traceability (what to record)

Handoff Package (what to include)

BOM CSV Template (copy/paste)

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Accepted Formats

Attachment

Frequently Asked Questions