USB ↔ UART/I2C/SPI/Ethernet/PCIe Bridge IC Guide
← Back to: USB / PCIe / HDMI / MIPI — High-Speed I/O Index
This page turns USB↔{UART/I²C/SPI/ETH/PCIe} bridging into an executable system contract: pick the right USB role/class/driver first, then validate buffers, transaction semantics, power/reset, and NVM configuration with measurable pass criteria.
The goal is predictable enumeration, deterministic transactions, and stable throughput/latency across hosts and production lots—without drifting into PHY/SI or Type-C details.
What This Page Covers: USB Bridge Reality Map
Practical focus: bridge ICs that expose UART / I²C / SPI / Ethernet / PCIe-facing functions over USB, optimized for field debug, manufacturing attach, and minimal-firmware integration.
- Enumeration + OS driver is the primary success factor for bridges (more than raw link speed).
- End-to-end throughput/latency is defined by USB class + endpoint type + buffering/transaction model + host scheduling.
- “Fast on paper” still fails in practice if deployment requires fragile drivers, unstable power/reset behavior, or non-reproducible configuration.
- USB class & driver strategy (deployability vs capability)
- Endpoint choice, buffering model, timeouts, and flow control
- EEPROM/strap configuration lifecycle and manufacturing consistency
- Board integration contracts (power/reset/port behavior) and bring-up test ladder
- Field triage: what to log, where to measure, how to isolate layers
- USB PHY signal integrity (eye/jitter/SI) → USB PHY (2.0/3.x/4)
- Type-C / PD / Alt-Mode routing and policy → Type-C Orientation & Signal MUX
- USB hubs and downstream scheduling details → USB Hub Controller
- Redrivers/retimers and high-speed channel EQ → USB Redriver / Retimer
- Ethernet PHY, magnetics, and cable compliance (PHY-side) → Ethernet PHY
- PCIe protocol training, compliance, SI/SerDes internals → PCIe PHY / SerDes
- Host OS priority: Windows / Linux / macOS / Android (driver availability dominates deployability).
- Driver posture: class-compliant (lowest friction) vs vendor driver (highest capability).
- Data shape: command/control (HID/CDC) vs high-volume payload (bulk) vs network attach (ECM/NCM/RNDIS).
- Performance goal: low-latency stability (p99) vs sustained throughput (MB/s) vs CPU budget.
- Target-bus constraints: UART flow control / I²C atomicity & timeouts / SPI CS & phase / Ethernet PHY attach / PCIe power/reset states.
Taxonomy: Bridge Types by USB Role and Endpoint Class
A bridge should be classified by USB role (Device/Host/DRD), then by USB class + driver posture, and finally by endpoint transfer type. This prevents scope drift and keeps performance expectations measurable.
- Device-role bridge (most common): plugs into a host and enumerates as a function (CDC/HID/ECM…). Target-bus actions (UART/I²C/SPI/MAC control) live behind the bridge.
- Host-role design: drives USB peripherals; typically belongs to USB host controller/hub topics rather than USB-to-X bridges. → USB Host/Device/DRD Controller
- DRD: implies OTG/Type-C ecosystem coupling; treat as boundary and route to Type-C/PD topics.
- CDC-ACM: serial console/logging and scripting
- HID: command/control with broad driver availability
- MSC: storage-like workflows for provisioning/transfer
- ECM/NCM: Ethernet over USB for service ports
- Custom transaction semantics (batching, atomic writes, special GPIO)
- Tighter latency control or higher throughput in specific workloads
- Trade-offs: driver distribution, signing, lifecycle maintenance, policy restrictions
- Installability: “works on a clean PC” vs “requires admin + signing + rollout process”.
- Observability: standard classes often integrate into existing OS tools; vendor stacks may require special logging.
- Stability posture: suspend/resume, hot-plug, and error recovery behavior must be verified per OS.
- Security posture: driver distribution is part of the product attack surface (policy, certificates, update paths).
Architecture Baseline: Data Path, Buffers, and Latency Budget
Performance must be defined by system-measurable metrics rather than headline USB link rates: throughput, end-to-end latency, jitter, host CPU, and drops/retries. The same accounting framework applies to UART/I²C/SPI/Ethernet/PCIe bridge variants.
- Throughput: sustained payload rate ≥ X for Y minutes (include payload size distribution).
- Latency: p50/p95/p99 transaction RTT ≤ X at payload Z (separate control vs data plane).
- Jitter: (p99 − p50) ≤ X or p99/p95 ratio ≤ X under steady load.
- Host CPU: ≤ X% at throughput Y (identify copy/interrupt hotspots).
- Errors: drops/retries/timeouts ≤ X per 10^N transactions; recovery ≤ X s after hot-plug/suspend.
- Host: app timestamps, driver queue depth, copy count (if visible).
- USB EP: transfer size histogram, service interval, timeout counters.
- Bridge FIFO: watermark hits, backpressure events, underrun/overrun.
- Target bus: transaction time, retry/NAK counts, clock-stretch or CS timing.
- Device: response time and busy windows (if observable).
- Small packets at high rate: low throughput yet high CPU/interrupt overhead.
- Frequent control/status polling: control plane starves bulk payload service.
- Host scheduling granularity: periodic jitter even when the channel is clean.
- Unbounded buffering: FIFO absorbs bursts but creates long tail latency without backpressure.
- First check: payload size histogram (small packets dominate?).
- Then check: endpoint type and service interval (bulk vs interrupt patterns).
- Fix direction: batching, fewer polls, bounded FIFO with backpressure.
- First check: host CPU% vs throughput curve (copy/interrupt hotspots).
- Then check: userspace polling frequency and buffer sizes.
- Fix direction: larger transfers, fewer syscalls, reduce control chatter.
- First check: timeout/retry counters and queue depth growth.
- Then check: target-bus NAK/stall patterns and FIFO watermark hits.
- Fix direction: align timeouts, add bounded backpressure, remove busy-loop retries.
- Throughput: sustained ≥ X for Y minutes (payload size noted).
- Latency: p99 RTT ≤ X ms at payload Z.
- Jitter: (p99−p50) ≤ X ms under steady load.
- Host CPU: ≤ X% at throughput Y.
- Errors: drops/retries/timeouts ≤ X per 10^N.
- Recovery: hot-plug or suspend/resume recovery ≤ X s; no configuration drift after reboot.
USB ↔ UART Bridges: Console, Manufacturing, and Robustness
USB-UART bridges should be evaluated as a deployable interface (driver posture), a lossless data path (flow control and buffering), and a field-robust device (hot-plug and sleep/resume behavior). The goal is predictable console access and manufacturing attach under stress.
- Lowest deployment friction (standard class, common OS support).
- Console/logging and manufacturing scripts using standard serial tools.
- Acceptable capability set: basic serial, stable enumeration, predictable recovery.
- Custom low-latency modes, batching, or extra features beyond CDC behavior.
- Controlled software distribution (signing/rollout process is available).
- Long-term driver lifecycle ownership is acceptable.
- RTS/CTS: required for bursty logs and non-lossy console requirements.
- Baud accuracy: divisor rounding and tolerance must match the target’s clock error budget.
- Break/marking: handle break conditions and edge cases used by bootloaders.
- Ring buffer watermarks: define when to assert backpressure vs when to drop.
- Bounded latency: avoid “infinite queue” behavior that causes long-tail delay.
- Overflow accounting: expose counters for overrun/underrun and host-side backlog.
- p99 latency ≤ X ms at burst load.
- drops/overruns ≤ X per 10^N.
- recover ≤ X s after unplug/replug and suspend/resume.
- Hot-plug: enumeration must be repeatable; no “ghost ports” or delayed teardown.
- Suspend/resume: ports should return without manual resets; timeouts must be bounded.
- Port identity changes: COM numbering or device path changes must be handled by manufacturing scripts.
- Contention: exclusive open conflicts (multiple tools competing for the port) should be detectable.
USB ↔ I²C/SPI Bridges: Timing, Atomicity, and Determinism
USB is scheduled and packetized, while I²C/SPI transactions are timing-sensitive and semantics-heavy. A bridge must define an explicit transaction model: what constitutes atomicity, where timeouts apply, how ACK/NACK or CS boundaries map into USB bulk, and what determinism means under load.
- Atomicity: each record must execute as one uninterrupted bus transaction.
- Timeouts: must be defined per record (bus-level) and per batch (USB-level) with clear precedence.
- Status codes: NACK/timeout/arb-lost (I²C) and mode/CS faults (SPI) must be distinguishable.
- Determinism: queue depth, batching size, and scheduling must bound p99 latency and tail behavior.
- Symptom: register read returns wrong bytes or “works sometimes”.
- First check: record flags include repeated-start; not split into two USB requests.
- Fix direction: use a single record covering write-addr + read data with repeated-start.
- Symptom: occasional long stalls, then bursts complete.
- First check: stretching budget and per-record timeout (bus-level).
- Fix direction: set a strict bus timeout; surface timeout code distinct from NACK.
- Symptom: “write succeeded” but device state does not change.
- First check: per-record status includes addr-NACK vs data-NACK.
- Fix direction: fail fast on NACK; avoid silent retries that hide root cause.
- p99 register transaction RTT ≤ X ms at batch size Y.
- addr-NACK/data-NACK/timeouts are uniquely reported; no “success without ACK”.
- after timeout, bus recovery completes ≤ X s and subsequent reads are consistent.
- Must-match: CPOL/CPHA, bit order, word size.
- First check: default mode after reset and persisted config (EEPROM if used).
- Fix direction: enforce mode per record; reject ambiguous “auto” behavior.
- Symptom: “write ok, readback wrong” for page or burst operations.
- First check: keep-CS flag for multi-byte bursts; CS toggle timing is not accidental.
- Fix direction: use keep-CS for a burst record; constrain maximum record length.
- Option A: auto-segmentation (convenient, can break atomicity).
- Option B: host segmentation (more work, preserves semantics).
- Fix direction: make the segmentation rule explicit and testable.
- burst read/write is atomic with keep-CS; readback matches ≥ X% over Y cycles.
- mode mismatch produces a distinct error; no silent “garbage data looks valid”.
- p99 burst transaction RTT ≤ X ms at payload Z.
- Atomic unit: one record equals one uninterrupted bus transaction.
- Timeout: per record timeout applies first; batch timeout is a transport guard.
- Status: return per record code + optional read payload; preserve ordering.
- Queue depth: cap in-flight records to bound tail latency.
- Max batch size: use batching to reduce overhead, but enforce p99 limits.
- Rate limiting: avoid busy-loop retries; expose counters for backpressure.
USB ↔ Ethernet Bridges: Class Choice, PHY Attachment, and Performance
USB-to-Ethernet bridges are selected first by USB class/driver posture (deployment risk), then by MAC-to-PHY attachment (interface constraints), and finally by performance knobs (throughput vs CPU and tail latency). PHY/magnetics/layout details intentionally belong to the Ethernet PHY page.
- Best fit: class-based deployments aiming for predictable integration.
- Key lever: packet aggregation and scheduling to reduce CPU overhead.
- Risk note: validate target OS posture early; do not assume universal parity.
- Best fit: environments where RNDIS is a known requirement.
- Key lever: keep control-plane chatter bounded to protect tail latency.
- Risk note: treat as a policy-driven choice, not a default.
- Best fit: controlled software stack with performance/features as priority.
- Key lever: custom batching/interrupt moderation and offload exposure.
- Risk note: driver signing, rollout and lifecycle ownership are mandatory.
- If installation must be minimal and cross-platform risk is high, start from class-based options.
- If throughput/CPU targets require custom behavior and software is controlled, vendor paths can be justified.
- Integrated PHY: simpler board bring-up; still validate class/driver posture.
- External PHY: bridge provides MAC; board routes a MAC-PHY interface.
- MAC-only constraints: interface timing and clocking must match the chosen PHY topology.
- RMII: lower pin count; tighter clocking assumptions.
- RGMII: higher bandwidth; timing alignment must be clear.
- SGMII: serialized MAC-PHY link; validate link/clocking requirements.
- Aggregation: larger effective packets reduce per-packet overhead.
- Interrupt moderation: merge interrupts to reduce CPU spikes and jitter.
- Offloads (if available): checksum or segmentation offload can cut CPU cost.
- sustained throughput ≥ X for Y minutes.
- p99 packet latency ≤ X ms under load.
- host CPU ≤ X% at throughput Y.
- link flap recovery ≤ X s; no silent drops.
USB ↔ PCIe Bridges: What’s Real, What’s Actually a PCIe↔USB Controller
“USB ↔ PCIe” is often misunderstood. The most common requirement is to add USB ports to a PCIe system—which is a PCIe-to-USB Host Controller (xHCI) use case. External PCIe expansion and USB4/TBT belong to different ecosystems and should be routed to their dedicated pages.
- What it actually is: PCIe-to-USB Host Controller (xHCI).
- Quick discriminator: the system needs new USB root ports visible to the OS.
- Decision output: select by lanes/Gen, port count, NVM/firmware, reset behavior.
- What it actually is: cabled PCIe / external PCIe subsystem.
- Quick discriminator: the goal is to carry PCIe out of the chassis to another box.
- Decision output: route to the “Cabled PCIe / External Boxes” page.
- What it actually is: different stack with its own certification and routing rules.
- Quick discriminator: requirements mention USB4/TBT, alt-mode tunneling, or platform certification.
- Decision output: route to the USB4/TBT topic page (out-of-scope here).
- Clocking: reference expectations must match platform policy (no guessing in late bring-up).
- Reset sequencing: define POR vs warm reset behavior; avoid “half-initialized ports”.
- Power budget: confirm port-power strategy and inrush limits at the system level.
- NVM requirement: know whether a valid image is required for enumeration.
- Update strategy: define field update rules and version traceability.
- Factory consistency: treat configuration as a controlled artifact (hash/version).
- Warm reset: ports return to a known-good state within a bounded time.
- Port identity: stable port mapping reduces driver rebind surprises.
- Error surface: failures should expose counters/events, not silent disappear/reappear loops.
- cold boot enumeration success ≥ X% across Y cycles.
- warm reset recovery ≤ X s with stable port mapping.
- hot-plug attach/detach recovery ≤ X s, no repeated re-enumeration storms.
- PCIe link training / equalization / compliance → PCIe PHY/SerDes & compliance pages.
- USB SI / Type-C routing / port protection → USB PHY / Type-C / protection pages.
- External PCIe and USB4/TBT → their dedicated topic pages.
Configuration Without Firmware: EEPROM/Straps, IDs, and Behavior Control
“Minimal firmware” is only practical when configuration is treated as a controlled artifact. EEPROM/straps/NVM determine identity and behavior: VID/PID, descriptor strings, default modes, GPIO states, and port mapping. Production success depends on a golden image, verification, and traceability—with a recovery plan for corruption.
- VID/PID: controls OS binding and driver selection.
- Strings/Serial: stable identifiers for fleet management.
- Default class/mode: prevents wrong driver match at first boot.
- Port mapping: stable interface ordering reduces re-enumeration surprises.
- Default behaviors: boot mode, link policy, and recovery policy knobs.
- GPIO defaults: strap-like behavior for system integration.
- Power strategy: default suspend/remote-wake behavior and port power policy.
- Error recovery: bounded retry vs safe-fallback mode after repeated failures.
- Version field: enables field identification and RMA triage.
- Corruption: wrong IDs or invalid descriptors can break enumeration.
- Drift: different batches ship with different images and behave inconsistently.
- No traceability: field issues cannot be mapped to a known configuration version.
- Freeze: version + hash; treat as a release artifact.
- Change control: avoid per-line “minor edits” without a new version.
- Golden reader: keep a known-good unit to validate fixtures.
- Write: controlled fixture sequence; power/reset are part of the recipe.
- Readback: CRC/hash check and version match.
- Behavior check: enumerate and confirm expected identity/mode.
- Trace: bind serial number to image version/hash.
- Sampling audit: periodic readout checks detect drift early.
- Rollback/lock: keep a safe fallback path; lock bits if supported.
- program + readback pass rate ≥ X% per lot.
- post-program enumeration success ≥ X% across Y samples.
- field identification can read version/hash reliably within X s.
Board Integration Hooks: Power, Reset, ESD, and Layout Contracts
This section turns “board integration” into executable contracts: power rails and sequencing, reset/recovery behavior, and connector-side ESD strategy. The goal is stable enumeration, deterministic recovery, and predictable post-ESD behavior—without expanding into Type-C, high-speed SI, eye diagrams, or choke selection.
- VBUS dependency must be explicit: define whether attach/enumeration is gated by valid VBUS presence and what “valid” means in the system. Verify: log VBUS presence vs attach events; no “ghost attach” when VBUS is absent.
- Rail set and tolerance must be pinned: list required rails (3V3 / 1Vx) and define acceptable ranges and ripple budget placeholders. Verify: rails within ±X% and ripple ≤ X mV under traffic and hot-plug.
- Sequencing must enforce “strap/NVM stable before release reset”: ensure straps/EEPROM are readable and stable before reset is deasserted. Verify: cold boot enumeration success ≥ X% over Y cycles; no mode drift between boots.
- Inrush and plug-in surge constraints must be declared: large bulk capacitance near the port must align with system inrush policy; do not “fix instability” by uncontrolled bulk. Verify: hot-plug does not brown out rails; no repeated disconnect/reconnect storms.
- Back-power must be actively prevented: avoid powering the bridge through I/O pins when one side is off (USB vs target interface). Verify: with USB off, target-side activity does not raise bridge rails; with target off, USB attach remains stable.
- Ground/reference continuity is a minimum contract: ensure port protection return and bridge ground reference are not forced into long detours. Verify: ESD events do not correlate with persistent enumeration failures or rising endpoint error counters.
- cold boot enumeration success ≥ X% over Y cycles.
- hot-plug attach/detach recovery ≤ X s with no repeated oscillation.
- no back-power observed (I/O pins do not raise rails) across defined power-off states.
- POR outcome must be deterministic: after POR, the bridge must enter a known enumeratable identity and mode. Verify: VID/PID/mode stable across cold boots; no “random mode” after marginal ramps.
- External reset hook must exist for recovery: allow the system to force a return to a known-good state without full power removal. Verify: warm reset returns the same identity within X seconds, stable port mapping.
- Watchdog/recovery policy must be bounded: repeated timeouts should trigger a controlled recovery step (soft reset → hard reset), not endless retries. Verify: no retry storms; recovery triggers after defined thresholds (placeholders).
- Attach behavior must be defined during reset: decide whether USB detach is asserted during reset to avoid host-side ghost devices. Verify: host does not accumulate duplicate device instances after repeated resets.
- Hot-plug recovery must be measurable: insertion/removal should converge to stable operation within a bounded time. Verify: attach/detach recovery ≤ X s; no repeated re-enumeration loops.
- warm reset recovery ≤ X s, identity unchanged (VID/PID/strings).
- no ghost devices after Y reset cycles.
- recovery escalation occurs after X consecutive transaction failures (no infinite retry).
- Protection must be connector-side: place ESD/TVS close to the interface to minimize unprotected trace length. Verify: ESD event does not cause persistent enumeration loss or repeated reconnect loops.
- Return path must be short and continuous: ensure discharge current returns without long detours that inject noise into the bridge reference. Verify: endpoint error counters do not rise after ESD compared to baseline.
- Differential symmetry must be preserved (principle only): keep protection and routing symmetrical to avoid severe imbalance. Verify: post-ESD link behavior stays within the same stability envelope (no new flaps).
- Low-speed sideband pins need a plan: protect ID/strap/GPIO/EEPROM lines to avoid “ESD passes once, fails later” degradation. Verify: identity strings and mode remain stable after ESD; no descriptor corruption symptoms.
- Scope boundary: Type-C details, high-speed line TVS selection, eye/CMC choices belong to the Port Protection / PHY pages. Verify: only placement/return-path rules are enforced here; selection details are routed out.
- post-ESD enumeration success ≥ X% over Y plug cycles.
- endpoint timeouts/stalls do not increase beyond X per Y minutes vs baseline.
- Type-C power negotiation / CC logic / alt-mode routing → Type-C topic page.
- High-speed SI, eye diagrams, retimer/redriver tuning → PHY / SI pages.
- CMC selection and emissions tuning → EMC/ESD page.
Bring-up & Debug: Instrumentation, Logs, and Failure Triage
The fastest field diagnosis comes from a layered triage: enumeration → driver binding → endpoint/transaction → buffer/timeout policy → power/reset correlation. This section defines what to observe and what to log, without turning into a protocol-analyzer tutorial.
- Visibility: confirm the device appears in OS device tree. If not visible → follow “enumeration / power” branch.
- Enumeration integrity: verify VID/PID, strings, configuration/interface count. Mismatch → suspect NVM/straps/version drift.
- Driver binding: confirm class driver is the intended one (CDC/ECM/NCM/Vendor). Wrong driver → fix identity/class exposure, not bus timing.
- Endpoint readiness: confirm endpoints exist and match intended transfer type. No endpoints / stalls → suspect configuration mismatch or reset state.
- Single-transaction minimal test: 1 read/write operation only. Fail here → mapping/permissions/target readiness, not throughput.
- Transaction model validation: queueing/batching/atomicity expectations. Common failure → wrong CS handling, repeated-start handling, or timeouts.
- Timeout & retry policy: ensure retries are bounded and timeouts are not self-defeating. Unstable behavior → retry storm vs overly aggressive timeouts.
- Stress test: sustained traffic with realistic packet sizes and bursts. Correlate errors with FIFO watermarks and CPU load.
- Power/reset correlation: align failures with VBUS/rail events and reset reasons. If correlated → enforce H2-9 board contracts.
- Isolation swap: replace host/port/cable/target to pin the failing layer. Outcome should classify: Host stack vs Bridge vs Target vs Board.
- timestamps: attach/detach, enumeration complete
- VID/PID, strings, serial, interface count
- driver name / class binding outcome
- device path (port topology) and re-enumeration count
- error code summary (timeouts/stalls) per session
- submit/complete counts per endpoint
- timeouts, stalls, NAK-related counters
- payload sizes (small vs large) distribution
- retry counts and abort/reset events
- latency percentiles (P50/P95) placeholders
- FIFO watermark / overrun / underrun
- transaction queue depth and drops
- I²C NACK/timeout, SPI short transfer, UART overrun (as applicable)
- reset reason and recovery triggers
- policy knobs: timeout values and retry thresholds (logged)
- VBUS presence and rail OK signals
- reset asserted/deasserted timestamps
- thermal events (if available) and throttling flags
- ESD test markers (pre/post) and stability envelope comparison
- every log entry must include a timestamp and test profile ID.
- record configuration knobs (packet sizes, queue depth, timeouts, retry thresholds).
- ensure lab and field runs share the same “minimal repro → stress → recovery” ladder.
H2-11. Engineering Checklist: Design → Bring-up → Production (Gate-based)
This chapter turns a USB bridge into a verifiable deliverable: each Gate has inputs, outputs, observable evidence, and pass criteria. The checklist stays strictly at the bridge level (USB role/class, transaction model, NVM identity, power/reset, and bring-up triage), without expanding into PHY/SI/compliance details.
Design Gate (contract locked before wiring)
Goal: freeze USB role/class/driver strategy, transaction model, and identity/NVM plan so bring-up is not blocked by enumeration or OS behavior.
-
USB role & class locked: Device-side bridge vs Host-side controller is explicitly separated.
Verify: OS list + class choice (CDC/HID/MSC/ECM/NCM/RNDIS/Vendor).
Pass criteria: target OS enumerates with in-box driver (or signed driver plan) for X platforms. -
Descriptor & endpoint contract: endpoint types (Bulk/Interrupt) and max packet / interval reflect latency/throughput needs.
Verify: descriptor review + host tool dump.
Pass criteria: no control-transfer retries during steady traffic; EP stalls ≤ X per Y minutes. -
Transaction model defined: queueing, atomic burst size, timeout, and error mapping (NACK/timeout/stall) are written as a contract.
Verify: API spec + negative test cases defined.
Pass criteria: every failure mode maps to a deterministic host-visible error code within X ms. -
Backpressure plan: FIFO depth, watermark, and flow control (UART RTS/CTS / SPI CS policy / I²C stretching policy / Ethernet buffering) are not implicit.
Verify: buffer math + stress scenario list.
Pass criteria: no silent drop; overflow always raises an explicit counter/event within X seconds. -
NVM configuration surface: which fields are strap vs EEPROM, plus CRC/rollback/lock strategy.
Verify: NVM map document + write protection option.
Pass criteria: corrupted NVM cannot brick: device still enumerates in safe mode within X seconds. -
Identity & traceability: serial number, string descriptors, and (if Ethernet) MAC source are decided up front.
Verify: factory record format + on-device readback plan.
Pass criteria: unique ID readable by host within X seconds; duplicate rate ≤ X ppm. -
Power/reset contract: rails, sequencing, brownout behavior, and reset recovery are written as measurable rules.
Verify: power tree + reset timing chart.
Pass criteria: after brownout/replug, re-enumeration success ≥ X/100 cycles. -
USB port protection policy: ESD/TVS placement and grounding policy are defined at the bridge boundary (no PHY deep-dive here).
Verify: placement rule: “connector-adjacent” + symmetry rule for pairs.
Pass criteria: no permanent functionality drift after IEC contact/air test at level X. -
Bring-up observability: which logs/counters exist (EP stalls, underruns, NACKs, link drops, resets) is specified before board spins.
Verify: register/telemetry list + host log schema.
Pass criteria: every triage branch has at least one reliable observable within X seconds. -
Acceptance thresholds drafted: latency/throughput/stability thresholds are written with units and measurement windows (X/Y placeholders allowed).
Verify: test plan includes window size + sample count.
Pass criteria: metrics are reproducible across ≥ X runs with σ ≤ Y%.
Design Gate output checklist: (1) role/class decision, (2) transaction + timeout contract, (3) NVM/ID plan, (4) measurable thresholds, (5) bring-up log schema.
Bring-up Gate (make failures classifiable)
Goal: progress from “enumerates once” to “survives stress + suspend/resume + error injection” with evidence logs.
-
Enumeration stability: repeated plug/unplug and hub topology changes are handled.
Verify: X cycles hot-plug + across hubs.
Pass criteria: success ≥ X/1000; no “ghost COM/NIC” instances. -
Single-transaction sanity: minimal read/write works with deterministic latency distribution.
Verify: known register loop test or echo loopback.
Pass criteria: p99 latency ≤ X ms (window Y seconds). -
Stress & backpressure: saturate traffic while forcing target-side stalls (UART paused, SPI slow peripheral, I²C stretching, ETH congestion).
Verify: stress script + counter correlation.
Pass criteria: no silent drop; overflow reports within X ms; recovery ≤ Y seconds. -
Suspend/resume behavior: S3/S0ix or mobile sleep cycles do not corrupt endpoints or NVM states.
Verify: sleep loop with traffic start/stop edges.
Pass criteria: resume success ≥ X/100; no descriptor drift. -
Reset recovery: POR/external reset/watchdog paths return to a known-good enumerated state.
Verify: forced hang → watchdog; forced brownout → POR.
Pass criteria: recovery time ≤ X seconds; data-path counters reset as specified. -
Error injection: induced CRC/timeout/stall conditions surface as predictable host errors and logs.
Verify: scripted failure cases (disconnect target, hold CS, NACK).
Pass criteria: 100% deterministic classification into triage buckets within X seconds. -
Performance baseline: throughput and CPU usage are measured with defined payload sizes and queue depths.
Verify: fixed test vectors (packet size, batch length).
Pass criteria: sustained throughput ≥ X MB/s with CPU ≤ Y% on target host. -
Field diagnostics pack: the minimum data to collect in the field is proven sufficient (descriptor dump + counters + timestamps).
Verify: reproduce a known issue with only the pack.
Pass criteria: root-cause direction (host vs bridge vs target) within X minutes.
Bring-up Gate output checklist: (1) reproducible scripts, (2) logs/counters schema, (3) baseline report (latency/throughput/CPU), (4) recovery proof.
Production Gate (config consistency + auditability)
Goal: every unit is traceable, its configuration is controlled, and sampling catches drift before field failures.
-
Golden configuration image: NVM fields (VID/PID/strings/mode/GPIO) are frozen and versioned.
Verify: checksum + version tag stored and read back by fixture.
Pass criteria: mismatch rate ≤ X ppm; auto-quarantine on mismatch. -
Write + verify + lock: programming flow enforces read-back and optional write-protect/lock.
Verify: fixture script includes read-back compare.
Pass criteria: 100% units pass read-back; lock status recorded for every serial. -
Identity provisioning: serial number and (for Ethernet) MAC provisioning source is controlled.
Verify: barcode/QR → on-device readback matches database.
Pass criteria: duplicates = 0; lookup success ≥ X/1000 units. -
Sampling & regression: periodic batch tests run stress + suspend + negative cases using the same vectors as bring-up.
Verify: sampling plan by lot/date.
Pass criteria: p99 latency / throughput / error rates remain within X% of baseline. -
Field identification: ability to fingerprint firmware/config version from OS without special tools.
Verify: descriptor string + version endpoint or vendor query.
Pass criteria: version fetch ≤ X seconds on all supported OS. -
RMA-safe behavior: “safe mode” enumeration path is preserved to recover misconfiguration.
Verify: forced bad NVM image test.
Pass criteria: safe mode enumerates within X seconds; fixture can rewrite to golden.
Production Gate output checklist: (1) fixture scripts, (2) trace database schema, (3) sampling report template, (4) safe-mode recovery SOP.
H2-12. Applications & IC Selection Logic (Bundles)
Bundles convert use-cases into selection decisions: choose OS/driver first, then define performance and transaction contract, then pick the bridge IC + supporting parts, and finally lock acceptance tests.
Bundle A · USB ↔ UART (field console / manufacturing / service port)
- Driver target: CDC-ACM (driverless) vs Vendor VCP (signed distribution cost).
- UART features: RTS/CTS, break, 9-bit (if needed), low-latency mode, buffer depth.
- Example bridge IC PNs: FTDI FT232RQ / FT232RL · Silicon Labs CP2102N (e.g., CP2102N-GQFN28) · Microchip MCP2221A
- Baud accuracy: define allowable error (ppm) and validate across temperature.
- Flow control policy: RTS/CTS required for bursts; define overflow reporting behavior.
- Supporting parts (PN examples): Microchip 24LC02B (I²C EEPROM, if external NVM needed) · TI TPS3808G01 or ADI ADM809 (reset supervisor) · TI TPD4EUSB30 (USB-side ESD for high-speed ports)
- Port identity drift: COM port numbering changes across hubs/sleep; plan for stable serial strings.
- Driver mismatch: vendor driver changes across OS updates; keep a controlled signed driver package if needed.
- Back-power: target UART domain powered while USB is off; add isolation policy in the power contract.
- Hot-plug: enumeration success ≥ X/1000 cycles; no zombie ports.
- Sustained stream: data loss = 0 over Y hours at Z baud with RTS/CTS enabled.
- Sleep loop: resume success ≥ X/100 with traffic restart ≤ Y seconds.
Bundle B · USB ↔ I²C / SPI (register access / board debug / fixture control)
- I²C semantics: repeated-start, NACK meaning, clock-stretch policy, bus-clear rules.
- SPI semantics: CPOL/CPHA, CS ownership, max burst length, atomic transaction boundaries.
- Example bridge IC PNs: Silicon Labs CP2112 (HID USB to SMBus/I²C) · Microchip MCP2210 (USB to SPI) · FTDI FT232H / FTDI FT2232H (MPSSE for SPI/I²C/JTAG) · Microchip MCP2221A (USB to I²C/UART)
- Transaction packing: batch multiple register ops into one USB bulk payload to reduce scheduling overhead.
- Timeout tiers: per-byte, per-transaction, and per-batch timeouts must be distinct.
- Supporting parts (PN examples): TI TPS3808G01 or ADI ADM809 (reset supervisor) · Microchip 24LC02B (fixture config EEPROM, if needed)
- Non-determinism: USB scheduling adds jitter; single-op APIs can amplify latency variance.
- Atomicity loss: splitting a CS window or repeated-start across USB packets can corrupt devices.
- Bus lock: I²C stuck-low needs a defined bus-clear and recovery state machine.
- Atomic bursts: max burst length maintained with zero mid-transaction gaps ≥ X runs.
- Negative tests: forced NACK/timeout maps to stable error code within X ms.
- Recovery: I²C bus-clear succeeds ≥ X/100 stuck-low injections.
Bundle C · USB ↔ Ethernet (dongle / service NIC / embedded gateway)
- Class/driver choice: ECM/NCM vs RNDIS vs Vendor depends on OS support policy.
- MAC/PHY attachment: prefer integrated PHY unless an external PHY is explicitly required by the platform.
- Example controller IC PNs: Microchip LAN7800 · ASIX AX88179A · Realtek RTL8153-CG
- Aggregation & CPU: batch packets and avoid tiny frames; confirm host CPU impact under full duplex.
- Interrupt moderation: tune to reduce overhead while keeping latency within target.
- Supporting parts (PN examples): Microchip 24AA02E48 (EUI-48 MAC EEPROM, if external MAC provisioning is used) · Microchip 24LC02B (generic I²C EEPROM, if required) · TI TPS3808G01 or ADI ADM809 (reset supervisor)
- Driver policy drift: OS updates can change CDC-NCM/RNDIS behavior; lock an OS support list.
- MAC identity: duplicate MACs cause invisible network faults; provisioning must be auditable.
- Suspend/resume: NIC disappearing after sleep must be covered by a test loop.
- Throughput: sustained ≥ X Mbps (TX/RX) with CPU ≤ Y% on target host.
- Loss & recovery: link flap recovers within X seconds; no interface rename drift.
- Identity: MAC uniqueness verified; duplicates = 0 for a lot of N units.
Bundle D · Add USB ports to a PCIe system (PCIe-to-USB xHCI host controller route)
- Reality check: the common need is “add USB ports to a PCIe host,” implemented by a PCIe xHCI host controller.
- Lane/port count: PCIe Gen and number of USB ports must match platform bandwidth and routing.
- Example host controller IC PNs: Renesas µPD720202 (2-port) · Renesas µPD720201 (4-port) · ASMedia ASM1042A · Fresco Logic FL1100
- Reset timing: align PERST# and power-good timing to avoid “phantom” xHCI enumeration.
- NVM/firmware: confirm whether external ROM/EEPROM is required for configuration.
- Port protection boundary: define connector-adjacent ESD parts at the USB port level (no PHY deep-dive here).
- Reset races: PERST# timing too short or rails ramp too slow causes intermittent host detection.
- Bandwidth assumptions: multiple ports behind insufficient PCIe bandwidth leads to unpredictable performance.
- Hot-plug expectations: platform policy may block hot-plug; validate platform behavior early.
- PCIe detect: xHCI enumerates reliably across X cold boots and Y warm resets.
- Port stability: all ports enumerate devices without intermittent disconnects over Z hours.
- Stress: simultaneous multi-port load meets throughput targets within X% of baseline.
Recommended topics you might also need
Request a Quote
H2-13. FAQs (Field Troubleshooting Only)
Scope: long-tail field triage only. Each FAQ follows a fixed, measurable 4-line structure: Likely cause / Quick check / Fix / Pass criteria (threshold placeholders X/Y/Z).
Enumerates sometimes, sometimes not — descriptor power or reset timing?
Likely cause: Descriptor power flags (bus/self-powered, bMaxPower) don’t match reality, or reset releases before rails are stable.
Quick check: Compare descriptor dump across attempts; correlate failures with VBUS/3V3 dip events and USB reset timing (first 2–5 s after plug).
Fix: Correct power-related descriptor fields, enforce sequencing (rails → stable → reset release), and add a reset supervisor / longer reset delay.
Pass criteria: Enumeration success ≥ X/1000 hot-plugs across Y host models; no unexpected reset within Z seconds after plug.
Works on one PC but not another — class driver vs vendor driver mismatch?
Likely cause: Different driver binding policies per OS/build, or descriptors trigger a non-inbox path on one host.
Quick check: Compare driver binding (which driver attaches) and descriptor identity (VID/PID, class/subclass/protocol) on both hosts.
Fix: Prefer an inbox class path where possible (CDC/ECM/NCM/HID/MSC), or ship a signed vendor driver with stable VID/PID + installation rules.
Pass criteria: Correct driver binds on X OS versions/builds; install steps ≤ Y; zero “driver blocked/unsigned” incidents in Z trials.
UART looks fine but drops under burst — FIFO/flow control or host scheduling?
Likely cause: FIFO overruns due to missing RTS/CTS backpressure, or host-side scheduling bursts create short-term overload.
Quick check: Correlate drops with FIFO watermark/overrun counters and RTS/CTS activity; repeat with larger USB bulk batches vs small packets.
Fix: Enable hardware flow control, increase buffering/batch size, and set explicit overflow reporting + retry policy (no silent drop).
Pass criteria: 0 drops over Y hours at Z baud with burst pattern; FIFO overrun counter = 0; p99 burst latency ≤ X ms.
I²C reads OK, writes fail — atomic transaction packing or timeout policy?
Likely cause: Write semantics require specific framing (e.g., repeated-start/no-stop) or write-cycle latency exceeds the bridge timeout tier.
Quick check: Compare the write transaction framing against the target requirement; raise timeout temporarily to see if failures flip from “timeout” to “success”.
Fix: Add explicit transaction flags (repeated-start / no-stop), separate per-transaction vs per-batch timeouts, and implement write-verify readback where applicable.
Pass criteria: Write success ≥ X/10,000 ops; p99 write latency ≤ Y ms (window Z minutes); NACK/timeout counters ≤ W per Z minutes.
SPI register writes “succeed” but no effect — CS handling or CPOL/CPHA mismatch?
Likely cause: CS is not held for the full atomic burst, or SPI mode (CPOL/CPHA) / bit order does not match the device.
Quick check: Perform write-then-readback of the same register; validate that the configured SPI mode and CS policy match the device profile.
Fix: Lock SPI mode per target, enforce CS ownership + atomic bursts, and require readback verification for configuration writes.
Pass criteria: Write+readback match ≥ X/10,000 ops; “write-ok/readback-mismatch” events = 0 over Y minutes.
USB-Ethernet shows link but throughput is low — ECM/NCM choice or CPU copy overhead?
Likely cause: Class/driver path adds overhead (wrong mode for the OS), or small-packet workload drives high interrupt + copy cost.
Quick check: Identify which class/driver is bound; measure CPU% at steady traffic; check packet-size distribution (tiny packets vs aggregated).
Fix: Prefer NCM/ECM where supported, enable aggregation/interrupt moderation, increase transfer batch size, and enable checksum offload if available.
Pass criteria: Sustained throughput ≥ X Mbps (TX/RX) with CPU ≤ Y% over Z minutes; packet loss ≤ W%.
After sleep/resume the bridge is “stuck” — remote wake policy or reset recovery missing?
Likely cause: Resume path leaves endpoints in a dead state, or selective suspend/remote wake expectations are mismatched.
Quick check: Compare descriptor/driver state before vs after resume; verify whether the device re-enumerates or remains present but non-responsive.
Fix: Implement a robust resume re-init (or forced re-enumeration), add watchdog-based recovery, and provide a controlled workaround for selective suspend if required.
Pass criteria: Resume success ≥ X/100 cycles; recovery time ≤ Y seconds; no manual replug required in Z trials.
EEPROM-configured units behave inconsistently — NVM image drift or write-verify missing?
Likely cause: NVM image drift across lots, partial programming, or missing read-back verification and version tagging.
Quick check: Read back the NVM fields that affect behavior (IDs/mode/strings) and compare checksum/version tag across multiple units.
Fix: Enforce Golden image + write-verify + optional lock; add a version tag; keep a safe-mode enumeration path for recovery.
Pass criteria: NVM checksum match = 100% for sampled N units; mismatch rate ≤ X ppm; field-behavior-critical fields identical within a lot.
Field cable hot-plug causes reboot — VBUS inrush/back-power path?
Likely cause: Inrush causes a local brownout, or a back-power path injects current through I/O and destabilizes reset/power domains.
Quick check: Correlate reboots with rail droop (VBUS/3V3/1Vx) at plug-in; test with target domain unpowered to expose back-power paths.
Fix: Add inrush control/load switch where appropriate, enforce back-drive blocking, strengthen decoupling, and tune reset supervisor thresholds/delays.
Pass criteria: No system reset across X hot-plug cycles; rail droop ≤ Y mV; brownout/reset counter = 0 over Z cycles.
Error counters stay low but users feel lag — latency jitter from small packets?
Likely cause: Tail latency and jitter dominate user experience (small packets + host scheduling + frequent API calls) even when error counters look clean.
Quick check: Log p50/p95/p99 latency over a fixed window; compare single-op vs batched transfers and note jitter (p99 − p50).
Fix: Batch operations, prefer bulk transfers where possible, reduce syscall frequency, and increase queue depth with explicit timeout tiers.
Pass criteria: p99 latency ≤ X ms and jitter (p99−p50) ≤ Y ms over Z minutes; user-visible lag events = 0 in W runs.
Bridge works in lab, fails in ESD — port protection placement or ground return?
Likely cause: ESD transient causes resets/stalls due to protection placement or return-path discontinuity, creating “soft failures” without immediate permanent damage.
Quick check: After ESD, verify descriptor identity is unchanged; check for reset events, endpoint stalls, and error spikes within the first X seconds.
Fix: Enforce connector-adjacent low-cap TVS placement and robust chassis/return strategy; add reset supervisor so recovery is deterministic after a hit.
Pass criteria: After IEC ESD at level X, re-enumeration + traffic pass within Y seconds; failure rate ≤ Z/100 hits; no descriptor drift.
PCIe add-USB card sometimes disappears — reset/clock gating or power management state?
Likely cause: PERST#/power-good timing race, clock gating, or platform power management (ASPM/L-state) transitions cause intermittent host controller loss.
Quick check: Compare detection across cold boot vs warm reset; retest with platform power saving reduced; verify PERST# release relative to stable rails.
Fix: Adjust reset timing, constrain problematic power states, and align firmware/NVM settings if the controller requires it.
Pass criteria: Detection success ≥ X/100 cold boots and ≥ Y/100 warm resets; no disappearance during Z-hour idle + resume loop.
