Shunt Adjustable Reference (TL431-Class)

Q: How low can I run cathode current before a TL431-class device becomes unstable?

Operate above the datasheet IKA(min) with margin. Below ~0.8–1 mA typical, loop gain collapses and the output cap/ESR pole moves, inviting oscillation. Validate at cold temperature where CTR and gm drop. Sweep IKA, load, and temperature while monitoring phase margin; target ≥45–60° with your actual Cout and wiring parasitics.

Q: What divider current is “safe” to beat leakage and Iref without wasting power?

Use Idiv ≥ max(100× worst-case leakage, 10× Iref). This keeps the Iref·Ru term ≤~20% of your total error budget and reduces sensitivity to PCB contamination. Typical designs run 50–200 µA. Increase for high-value resistors, harsh humidity, or wide temperature; decrease only after verifying drift and noise.

Q: How do I place zeros/poles for an opto-isolated TL431 loop to hit 45–60° PM?

Place the TL431 RC zero slightly below the power-stage dominant pole (≈0.7–0.9×). Add a high-frequency pole to roll off noise above crossover. Model opto CTR spread and LED storage; design for worst-case low CTR at cold. Verify Bode across line/load and temperature; keep crossover well below any right-hand-plane zeros.

Q: Why does a large output capacitor oscillate at light load and how do I fix it?

At light load, the TL431’s gm and IKA fall, pushing the Cout/ESR pole into the crossover region. Very low ESR ceramics remove stabilizing zero damping. Fix by increasing IKA, adding a small series resistor to Cout, inserting a feedforward/comp capacitor, or selecting parts with an “all-capacitor stable” variant and validating phase margin.

Q: TL431 vs TLV431: when should I pick the low-current variant?

Choose TLV431-class when you need low IKA operation, lower VREF (~1.24 V) or tighter budgets at light load. It enables ultra-low power and low-voltage rails but usually trades some bandwidth. For robust compensation with wide load steps and higher crossover, the classic TL431 family remains easier to stabilize.

Q: How do I translate ppm/°C and long-term drift into a millivolt budget at 5 V?

Use ΔV = V × (ppm/°C) × ΔT / 10⁶. For 50 ppm/°C over 100 °C, ΔV ≈ 25 mV at 5 V. Add long-term drift (e.g., 1000 h drift) via RSS with resistor tempco and Iref·Ru error. Keep each contributor <20–30% of total to avoid any single dominant term.

Q: Can I reuse the divider for both ADC sense and TL431 without skew or noise?

Yes, if the ADC input bias and sampling network are modeled. Buffer fast-sampling ADCs or provide a small series resistor and local RC to the ADC pin. Ensure the sampling kick doesn’t modulate the TL431 node; re-check Idiv ≥ 10× Iref plus ADC bias to cap bias-induced errors.

Q: What CTR spread and opto aging should I assume in the compensation design?

Assume a wide CTR window (e.g., 50–600%) and derate for temperature and lifetime. Use worst-case low CTR for gain calculations and verify cold startup. Avoid LED overdrive; check storage time. If PM is marginal, lower crossover, raise IKA, or pick screened optos with tighter CTR bins.

Q: How do I check stability across temperature, input range, and load corners fast?

Use a network analyzer or injection transformer to sweep loop gain at cold/room/hot with min/max IKA and line/load extremes. As a quick screen, apply load steps and ramp VIN with superimposed ripple. Look for peaking, chatter, or slow recovery. Iterate RC compensation and IKA until PM ≥45–60° everywhere.

Q: When should I switch to a buried-Zener or CMOS precision reference instead?

Switch when you need ultra-low noise, very low tempco, or minimal IKA. Buried-Zener excels for metrology-grade drift/noise but costs power. CMOS/XFET parts offer low Iq and better PSRR at low current. If TL431 loop constraints dominate your error budget, a series reference plus op-amp may be cleaner.

What It Solves

TL431-Class addresses three recurring needs: precision thresholding, error-amplifier loops, and opto-isolated feedback. We map Problem → Capability → Metric so designs are verified, not guessed.

Stability at Light Load

Low I_KA + large C_k + low ESR shrinks phase margin → oscillation.

Capability: Wide I_KA window; compensation via C_k/R–C–C nodes.

Metric: PM ≥ 45–60°, ESR/C_k inside vendor window across VIN/Load/Temp.

Threshold Drift

High-value divider amplifies leakage and I_ref·R_u; temp/aging add drift.

Capability: Precision V_ref grades, low tempco options, divider sizing rules.

Metric: |ΔV_th| within budget; ppm/°C → mV across −40~+85/125 °C.

Opto Loop Chatter

CTR spread & saturation/recovery shift gain/phase in flyback/LLC loops.

Capability: TL431 EA + R–C–C compensation (zero vs power pole).

Metric: PM ≥ 50–60° min/max load; recovery without spikes across line/temp.

Divider current I_div ≥ max(100× leakage, 10× I_ref); bound I_ref·R_u ≤ 20% total error.
Target PM ≥ 45–60° with ESR/C_k in vendor window; verify across VIN/Load/Temp.
Automotive: prefer AEC-Q100; validate drift post reflow/thermal cycling.

How TL431-Class Works (Internal Model & Parameters)

TL431-Class is a shunt adjustable reference: a 2.495 V (typ.) reference and an error amplifier force the K node to regulate via an external divider (R_u/R_l). Cathode current I_KA and dynamic impedance Z_KA set small-signal behavior; the bias current I_ref adds an error term into R_u.

Output / Threshold: V_out = V_ref · (1 + R_u/R_l) + I_ref · R_u

Drift: ΔV = V × (ppm/°C) × ΔT / 10⁶

RSS Error: σ_total = √(σ²_device + σ²_divider + σ²_Iref·Ru + σ²_drift)

Accuracy grades: ±0.5% / ±1%; V_ref≈2.495 V (typ.).
I_KA window: choose a working point ≥ stability threshold + temp margin.
Z_KA: small-signal output impedance shaping gain vs load perturbations.
I_ref path: visible in high-value R_u; keep I_ref·R_u within budget.
Noise & BW: add RC post-filter only if phase margin remains ≥ target.

Pick I_KA working point ≥ stability threshold + temp margin.
Set I_div so that I_div ≥ max(100× leakage, 10× I_ref).
Keep I_ref·R_u ≤ 20% of total error; then combine by RSS.
Confirm PM ≥ 45–60° across VIN/Load/Temp; opto CTR spread included.

Design Recipes (Threshold, Divider & Bias Window)

This chapter gives a copy-ready recipe to set V_out/V_th, choose a stable I_KA working point, and size the divider current so the I_ref·R_u term stays inside the error budget. Use the four-step flow, verify with the formula card, and close accuracy/drift with the RSS roll-up.

Four-step TL431 recipe with a compact formula card. Wrapped lines prevent overflow on any device.

Set V_out / V_th (e.g., 5.000 V).
Choose I_KA (start 0.5–1 mA; up to ~10 mA for bandwidth/noise headroom).
Size divider current: Idiv ≥ max(100× Ileak, 10× Iref); choose E96/E24 parts.
Compute & close budgets:
- V_out = V_ref·(1 + R_u/R_l) + I_ref·R_u
- Keep I_ref·R_u ≤ 20% of total error
- ΔV = V × (ppm/°C) × ΔT / 10⁶
- σ_total = √(σ²_device + σ²_divider + σ²_Iref·Ru + σ²_drift + σ²_leak)

Example (copy-ready): V_th=5.000 V; I_KA=1.0 mA; I_div=100 µA; device accuracy=±1%; tempco=50 ppm/°C.

Pick R_u, R_l from E96; compute I_ref·R_u and ensure ≤20% of total error; convert tempco to mV drift over your ΔT.

If budgets don’t close: increase I_div or reduce R_u, select a tighter accuracy/tempco grade, then re-verify stability (see Chapter 4).

Stability & Compensation (ESR/Cap Map + Opto Loop)

Stability is a three-way coupling of I_KA, C_k and ESR. Low I_KA plus large C_k and low ESR pushes poles and erodes phase margin. Compensation uses C_k, C_f and the R–C–C network, especially in opto-isolated flyback/LLC loops. Aim for PM ≥ 45–60° across line, load and temperature.

Stability map and RCC compensation. All long texts are wrapped with <tspan> to avoid overflow.

Stability Checklist

C_k/ESR inside window; I_KA ≥ stability threshold + temp margin.
PM ≥ 45–60° across line/load/temp; GM ≥ 6 dB recommended.
RC post-filter re-checked for phase erosion.

Opto Loop Checklist

Zero#1 near the power pole (0.7–0.9×); HF cap sets roll-off.
CTR spread & aging covered with ≥10–15° PM margin.
No saturation/recovery spikes; startup/shutdown free of chatter.

Common fixes: Raise I_KA, increase ESR or reduce C_k; shift zero slightly lower; add small HF cap; re-grade opto CTR; retune R–C–C bounds.

Re-run Bode and time-domain sweeps after every change.

Application Patterns (Copy-Ready)

Four copy-ready patterns. Each tile includes a minimalist circuit, 3 key parameters, and 2 common pitfalls. Text is pre-wrapped to prevent overflow on mobile.

Verification Matrix

Bode across VIN(min/max) × Load(min/max) × Temp(−40/25/+85/+125).
Ramp tests (slow/fast) + pre-bias; time-domain spikes free.
Drift & hysteresis measured; LED/Clamp add thermal steady-state.

Pass/Adjust Criteria

PM ≥ 45–60°; no chatter; CTR/aging margin ≥ 10–15°.
RSS (accuracy + divider + Iref·Ru + drift) ≤ budget.
Power/thermal within limits; re-run sweeps after any change.

Noise, Drift & Temp Behavior

Separate short-term noise (density & bandwidth) from long-term drift (ppm/°C, stress, aging). RC post-filtering reduces noise but can erode phase margin—always re-check stability. When budgets do not close, consider Buried-Zener or CMOS/XFET families, or TLV431-class for ultra-low-current, then re-verify the stability window.

Noise Workflow

Select target bandwidth; integrate density to Vrms.
RC post-filter only if PM remains ≥ target.
Compare Vrms vs ADC/LDO limits; adjust BW or filter.

Drift Workflow

Convert ppm/°C to mV over your ΔT.
RSS with device accuracy, divider, Iref·Ru, aging.
If budget fails: upgrade tempco/accuracy, ↑Idiv or ↓Ru, or switch family.

Power & Reliability (Start-Up, Transients & SOA)

Objective: boots cleanly, survives surges, stays within stress limits. Use the flow below: start-up & minimum load → transient & EMI hardening → automotive & reliability checkpoints. Sweep VIN/Load/Temp, include pre-bias cases, and re-verify phase margin after any EMI countermeasure.

Test Sweep

VIN(min/max) × Load(min/max) × Temp(−40/25/85/125 °C)
Up/Down ramp: slow/fast + pre-bias cases
EFT/Surge overlay; monitor overshoot, chatter, reset

Pass / Adjust

PM ≥ 45–60°; no chatter with ΔV hysteresis
Thermal/SOA within limits after worst-case pulses
Record drift after reflow & burn-in; keep lot traceability

Cross-Brand Mapping (TL431-Class & Notes)

Equivalence here means adjustable shunt reference (TL431-class). Where a brand lacks a true TL431-class, we give a non-equivalent migration hint (CMOS/XFET or buried-Zener) and mark it clearly.

Brand	Representative PNs (Datasheet)	Equivalence	Why this pick / Notes
Texas Instruments	TL431A · TL431B · TL431-Q1 · TLV431 · TLVH431 (1.24 V)	TL431-class (equivalent)	Clear A/B accuracy grading; Q1 is automotive grade; TLV/TVLH cover low-IKA/low-threshold use cases, with complete documentation and easy second-source alignment.
STMicroelectronics	TL431 · TL432 · TLVH431 (1.24 V)	TL431-class (equivalent)	Bins and packages aligned with TI, making primary/secondary sourcing easy; stable European supply.
onsemi	NCP431 (A/B/C) · NCV431 (AEC-Q100)	TL431-class (equivalent)	Covers automotive NCV; full accuracy grades; suitable as an automotive second source or for North American supply chains.
Microchip	MIC431 · MIC432 · (alt, non-equiv) LM4040 (fixed)	TL431-class (MIC431/432) + non-equivalent alternatives	Micrel lineage; if you need lower noise/TC, switch to CMOS/fixed references (loop must be reworked).
NXP	Supply lineage → Nexperia TL431	Equivalent recommendation: switch to TI/ST/onsemi or Nexperia	NXP’s own TL431 discrete coverage is limited; for projects, set up a second source with TI/ST/onsemi, or use Nexperia directly.
Renesas	ISL21070 (precision, fixed) · ISL21010 (low-noise, fixed)	Not TL431-class (non-equivalent)	Renesas focuses on Buried-Zener/CMOS precision references; switching families requires rebuilding the error-amp/compensation model.
Melexis	N/A for TL431-class	Non-equivalent / Not offered	Focused on sensors/drivers; for TL431-class, build a cross-brand combination with TI/ST/onsemi.

Submit your BOM (48h)

BOM & Procurement Notes (Small-Batch Friendly)

Use this section to turn engineering intent into a purchase-ready BOM. Capture mandatory electrical and reliability items, then note lifecycle and second-source strategy. This format is optimized for small-batch builds and automotive variants.

BOM Essentials (Required Fields)

V_out/Threshold (target & tolerance)
I_KA (work) with temperature margin
Accuracy bin (±0.5% / ±1%)
Tempco target (ppm/°C)
Package & max height
AEC-Q100 (Y/N, grade)
Divider R_u/R_l tolerance & TCR
Second-source (Y/N; brand list)

Optional / Integration

ESR range & C_k value (with test frequency)
Optocoupler PN & CTR band
dV/dt requirements (up/down ramps, pre-bias)
EMC levels (EFT/Surge) & injection entry points
Phase-margin target after filters/EMI fixes

Risks & Mitigations

EOL/LTB: record source & last-checked date
False equivalence: TL431-class vs CMOS/XFET fixed refs
Pin & symbol semantics: K/REF variants, Rh path
Stability domain: ESR/C_k window differs by vendor
MOQ/lead time for small batch; –Q1/NCV suffix alignment
Second-source matrix: TI ↔ ST/onsemi as primary pair; Microchip (MIC431/432) as alternate; Renesas/NXP flagged if non-TL431-class.

Submit Your BOM

Cross-brand recommendation within 48h. We honor your small-batch constraints and automotive suffixes.

Submit BOM (rel="nofollow")

Field	Value	Notes
V_out/Threshold	—	Target & tolerance
I_KA (work)	—	≥ stability threshold + temp margin
Accuracy bin / Tempco target	— / — ppm/°C	±0.5% / ±1% etc.
Divider R_u/R_l / TCR	— / — / — ppm/°C	I_div ≥ max(100×I_leak, 10×I_ref)
C_k / ESR window (opt.)	— / —	Specify frequency/temperature
Optocoupler PN / CTR band (opt.)	— / — %	Include recovery time note
Package / Height (mm) / AEC-Q100	— / — / —	Suffixes (-Q1, NCV)
Second-source (Y/N)	—	Brands / PNs list

Tip: for automotive flows, store lot/date codes and post-reflow drift measurement alongside the BOM. Align suffixes across brands.

Design Checklist (One-Page QA)

Print or copy the following 15 items. They mirror TL431-class design risks across bias, divider, compensation, stability, EMC, and drift budgets.

1) I_KA ≥ stability threshold + temperature margin (record typ/min).

2) I_div ≥ max(100×I_leak, 10×I_ref); record estimation basis.

3) I_ref × R_u ≤ 20% of total error budget.

4) Target V_out / ΔV_hys (via R_h) matches calculation and bench data.

5) C_k nominal & ESR stay in the stability window (specify freq/temp).

6) Phase margin ≥ 45–60° across VIN/Load/Temp after all filters.

7) No chatter under pre-bias, slow ramp, or fast ramp conditions.

8) Low-noise RC post-filter does not break the loop (re-check PM/step).

9) Optocoupler CTR spread & recovery included in compensation plan.

10) Over/undershoot < 5% of threshold (note probe & bandwidth).

11) EFT/Surge levels and entry points documented (TVS/snubber precede ref).

12) Thermal/SOA OK for continuous/pulsed stress; copper spreading noted.

13) Post-reflow & burn-in drift ≤ budget; lot/date traceability stored.

14) AEC-Q100 grade & suffix alignment (-Q1/NCV); second-source validated.

15) Lifecycle check: Active/NRND/EOL with links & last-checked date.

Keep measurement bandwidth and probe compensation consistent across checkpoints to avoid false regressions.

Frequently Asked Questions

How low can I run cathode current before a TL431-class device becomes unstable?

Operate above the datasheet IKA(min) with margin. Below ~0.8–1 mA typical, loop gain collapses and the output cap/ESR pole moves, inviting oscillation. Validate at cold temperature where CTR and gm drop. Sweep IKA, load, and temperature while monitoring phase margin; target ≥45–60° with your actual Cout and wiring parasitics.

What divider current is “safe” to beat leakage and Iref without wasting power?

Use Idiv ≥ max(100× worst-case leakage, 10× Iref). This keeps the Iref·Ru term ≤~20% of your total error budget and reduces sensitivity to PCB contamination. Typical designs run 50–200 µA. Increase for high-value resistors, harsh humidity, or wide temperature; decrease only after verifying drift and noise.

How do I place zeros/poles for an opto-isolated TL431 loop to hit 45–60° PM?

Place the TL431 RC zero slightly below the power-stage dominant pole (≈0.7–0.9×). Add a high-frequency pole to roll off noise above crossover. Model opto CTR spread and LED storage; design for worst-case low CTR at cold. Verify Bode across line/load and temperature; keep crossover well below any right-half-plane zeros.

Why does a large output capacitor oscillate at light load and how do I fix it?

At light load, the TL431’s gm and IKA fall, pushing the Cout/ESR pole into the crossover region. Very low ESR ceramics remove stabilizing zero damping. Fix by increasing IKA, adding a small series resistor to Cout, inserting a feedforward/comp capacitor, or selecting parts with an “all-capacitor stable” variant and validating phase margin.

TL431 vs TLV431: when should I pick the low-current variant?

Choose TLV431-class when you need low IKA operation, lower VREF (~1.24 V) or tighter budgets at light load. It enables ultra-low power and low-voltage rails but usually trades some bandwidth. For robust compensation with wide load steps and higher crossover, the classic TL431 family remains easier to stabilize.

How do I translate ppm/°C and long-term drift into a millivolt budget at 5 V?

Use ΔV = V × (ppm/°C) × ΔT / 10⁶. For 50 ppm/°C over 100 °C, ΔV ≈ 25 mV at 5 V. Add long-term drift (e.g., 1000 h drift) via RSS with resistor tempco and Iref·Ru error. Keep each contributor <20–30% of total to avoid any single dominant term.

Can I reuse the divider for both ADC sense and TL431 without skew or noise?

Yes, if the ADC input bias and sampling network are modeled. Buffer fast-sampling ADCs or provide a small series resistor and local RC to the ADC pin. Ensure the sampling kick doesn’t modulate the TL431 node; re-check Idiv ≥ 10× Iref plus ADC bias to cap bias-induced errors.

What CTR spread and opto aging should I assume in the compensation design?

Assume a wide CTR window (e.g., 50–600%) and derate for temperature and lifetime. Use worst-case low CTR for gain calculations and verify cold startup. Avoid LED overdrive; check storage time. If PM is marginal, lower crossover, raise IKA, or pick screened optos with tighter CTR bins.

How do I check stability across temperature, input range, and load corners fast?

Use a network analyzer or injection transformer to sweep loop gain at cold/room/hot with min/max IKA and line/load extremes. As a quick screen, apply load steps and ramp VIN with superimposed ripple. Look for peaking, chatter, or slow recovery. Iterate RC compensation and IKA until PM ≥45–60° everywhere.

When should I switch to a buried-Zener or CMOS precision reference instead?

Switch when you need ultra-low noise, very low tempco, or minimal IKA. Buried-Zener excels for metrology-grade drift/noise but costs power. CMOS/XFET parts offer low Iq and better PSRR at low current. If TL431 loop constraints dominate your error budget, a series reference plus op-amp may be cleaner.

Why do “same-name” TL431 parts behave differently across brands?

Internal EA gm, reference current, bandwidth, and dynamic impedance differ by vendor and grade (A/B/LI/Q1). Pinouts may swap (TL432-style). Stability windows with ceramic Cout also vary. Always read the specific datasheet, match pinout, and re-tune compensation instead of assuming drop-in equivalence.

What procurement flags (AEC-Q100, suffixes, EOL) matter for small batches?

Watch AEC-Q100 grades (Q1/NCV/SCV), accuracy bins (A/B/C), and “LI/Low-Iq” or “HV” variants. Confirm package pinout (KRA vs RKA), lifecycle (active/EOL/LTB), and second-source behavior. Prefer parts with stable supply and cross-brand equivalents; archive PDFs and lot traceability for future audits.

Resources (Official)

Texas Instruments

TL431 / TL432 Datasheet — Adjustable shunt, V_REF≈2.5 V.
TLV431x Datasheet — Low-voltage variant, V_REF≈1.24 V.

STMicroelectronics

TL431 / TL431A / TL431B Datasheet — Grades and accuracy options.
TL431LI Datasheet — Improved low-Iq version.

Nexperia (NXP heritage)

TL431 / TL432 Datasheet — Shunt regulators, multiple packages.

onsemi

TL431A/B, NCV431 Datasheet — Programmable precision references.
NCP431 Datasheet — TL431-class upgrade.
App Note: TL431 in SMPS Control — Compensation and design tips.

Renesas (non TL431-Class reference)

ISL21090 Datasheet — Precision series reference; use when ultra-low drift is required.

Microchip (non TL431-Class, low-voltage shunt)

MIC4043 Datasheet — Low-voltage secondary-side shunt for 1.8–2.5 V rails.

Melexis

N/A for TL431-class parts. Consider Melexis for sensors/LED drivers; use cross-brand TL431 parts from TI/ST/onsemi/Nexperia where needed.

Shunt Adjustable (TL431-Class) Reference