System Role & Hazard Domains

In a 16-bit SAR ADC with a 2.5 V reference, one LSB is roughly 40 µV. A thermal hysteresis of 100 ppm on that rail translates into about 0.25 mV, or 6–7 LSBs of one-time offset shift when the board returns to room temperature after a temperature cycle. This is no longer a rounding error – it is visible at the system level.

The attractive 0.05 % accuracy number on the datasheet is usually guaranteed under steady-state conditions: supply and temperature are stable, the reference has fully powered up and internal nodes have settled. Cold-start, pre-biased outputs and short temperature excursions are often outside that comfort zone, even though they are exactly where many field issues appear.

These behaviours matter most where a reference rail defines thresholds or full-scale ranges:

• Precision ADC/DAC reference rails, where start-up overshoot or hysteresis becomes offset and gain error across the entire conversion range.
• Comparator threshold rails, where unstable start-up behaviour can trigger false trips or mask genuine faults.
• Safety and monitoring channels in BMS and motor control, exposed to cold-crank, hot soak and repeated temperature cycling that amplify these effects.

Start-Up Behaviour Basics

Start-up behaviour is more than a single number on the datasheet. It covers how the reference output moves from 0 V or a pre-biased level to its final value, how long it takes to settle and when the system can safely trust that rail. Three concepts are especially useful in real designs: start-up time, settling time and enable-to-ready time.

Start-up time is usually defined from VIN or EN rising to the moment Vref first enters a coarse window around its final value. Settling time takes it further and asks when Vref enters and stays within the final accuracy band after any overshoot or undershoot. Enable-to-ready is a system-level view: the time from enabling the reference to the point where downstream ADCs, comparators or safety logic can rely on it without being exposed to transient errors.

The shape of the start-up waveform depends strongly on conditions. A true cold-start, where internal nodes have fully discharged, often gives the longest and most revealing behaviour. Warm-starts can look much cleaner but are rarely the worst case. At the same time, output load current and output capacitance can stretch the start-up, introduce a second slow rise or even create a misleading plateau that looks stable but is still moving.

In practice you will see a handful of recurring patterns on the bench. A clean monotonic rise is ideal. A rise with overshoot and a late back-step may still be acceptable if conversions are held off until after settling. More dangerous is the pre-biased case where the reference latches at an intermediate level or needs a full power cycle before it will start correctly. Figure F2 sketches these typical waveforms.

Thermal Hysteresis & Repeatability

Thermal hysteresis describes how much a reference fails to return to the same output voltage after a full temperature excursion. The classic experiment is simple: measure Vref at a starting temperature T1, move the device to another temperature T2, then return to T1 and measure again. The difference between the two Vref readings at T1 is the hysteresis for that cycle, usually expressed in ppm of the nominal output voltage.

This behaviour is different from both temperature coefficient and long-term drift. Tempco describes the continuous slope of Vref versus temperature and is often modelled as a first- or second-order curve; at a given temperature, going up and coming back ideally lands on the same point. Long-term drift is tied to elapsed time and ageing even at a fixed temperature. Thermal hysteresis, by contrast, is event-driven: each strong temperature cycle can leave a small residual offset at the starting temperature, influenced by mechanical stress and package construction.

Datasheets usually report hysteresis as “±X ppm typ” over a specified range such as −40~+85 °C or −55~+125 °C. Sometimes this is for a single cycle; sometimes it is combined into broader “stability over temperature” or “stability over reflow” figures. The key is to recognise that these numbers represent one-time or accumulated offsets at the same temperature, not continuous slope and not multi-year ageing.

When you translate ppm into millivolts and then into ADC LSBs, thermal hysteresis can easily consume several counts of error in a high-resolution system. Figure F3 sketches the basic measurement loop and highlights how the two Vref samples at T1 differ before and after the cycle.

Mapping Datasheet Specs to Real Behaviour

Start-up and hysteresis numbers only make sense when you understand the conditions under which they were measured. The same “1 ms start-up time” can mean very different things depending on load current, output capacitance and VIN ramp, and a single hysteresis line in ppm hides assumptions about temperature range and soak time. This section links those entries back to real waveforms and error budgets.

For start-up and enable time, check the test conditions carefully. Is the reference measured with no load or with a representative output current? Is the specified CL a small, local ceramic capacitor or a large bulk network? Is VIN stepped quickly or ramped slowly? If your application uses higher load, larger Cout or much slower ramps than the datasheet, the true start-up and settling times on the bench will be longer and the waveform may change shape.

Many precision references now state whether start-up into a pre-biased output is guaranteed. A line such as “start-up from 0 to 0.9 × Vref pre-bias, guaranteed” tells you that the vendor has characterised this behaviour under defined conditions. Wording like “not tested” or “not characterised” does not prove failure, but it does mean you must verify your own pre-bias scenarios, especially when references share rails with clamp diodes, protection networks or other supplies.

Hysteresis entries also deserve a close read. The quoted ppm figure always refers to a particular temperature span, such as −40~+85 °C or −55~+125 °C, and to a particular cycling and soak profile. Some numbers are typical only and are not production tested. When you translate those ppm values into millivolts on your chosen Vref and then into ADC LSBs, you can see how much of your offset or gain budget they consume.

A simple way to keep everything consistent is to walk through a short chain: take the datasheet entry in ppm, convert it to a voltage shift on your reference rail, convert that into LSBs for the ADC resolution in use, and then compare it with the allowed system error. Figure F4 shows this flow for one example hysteresis number.

Design Rules for Start-Up & Pre-Bias

Avoiding start-up surprises comes down to a few concrete rules: sequence the reference and its loads in a safe order, size load and Cout within the stable region, and handle pre-bias and clamp paths explicitly. Once these conditions are under control, the start-up waveforms you see on the bench will be close to what the datasheet suggests, instead of depending on chance interactions between rails.

For precision ADCs, the reference should reach its final value before conversions begin and stay within a tight error band during the first samples. A practical rule is to delay ADC start-up until Vref has reached at least 99 % of its final value and remained within a small window for tens of microseconds. Overshoot and late settling are harmless as long as conversions are held off until after the ready point, ideally using a dedicated ready or power-good signal rather than a fixed delay.

Comparator thresholds derived from Vref should also be shielded from start-up. If the comparator is allowed to evaluate while Vref is still rising or ringing, it can generate false UV/OV or fault decisions. Gate comparator outputs with a power-good signal, or choose devices with built-in blanking or delay so that fault logic only becomes active once Vref is genuinely in range. Safety-related comparators in BMS and motor drives benefit especially from this extra margin, because they see the harshest cold-crank and slow-ramp conditions.

Pre-bias adds another layer. Clamp and protection paths from other rails can hold the Vref node at a mid-level before the reference even starts, particularly when internal ESD structures connect Vref to AVDD or other supply pins. To avoid latch-off, identify all paths that can pre-bias the node, then insert series resistance, start-up clamps or active discharge devices so that the reference sees a well-defined starting point at each power-on.

Load current and output capacitance shape the start-up envelope. Staying inside the recommended Cout range keeps the control loop stable, but large capacitors and heavy initial load will still stretch start-up and can create apparent plateaus. Design with the worst-case load current in mind and observe the waveform with that load enabled. In higher resolution systems, the acceptable amount of residual movement before the first conversion shrinks rapidly, and automotive or safety applications typically demand more guard band than general industrial or consumer designs.

Budgeting Thermal Hysteresis

Once thermal hysteresis is understood as an offset introduced by temperature cycling, it can be treated as a normal part of the error budget. The practical steps are to convert the datasheet ppm value into a worst-case offset for one representative cycle, decide where that offset sits within your total offset and gain allowance, and then use packaging, temperature grade and calibration strategy to keep it under control over product lifetime.

Start with the hysteresis entry in ppm and multiply by the nominal reference voltage. For example, 100 ppm on a 2.5 V reference is 0.25 mV. On a 16-bit ADC using that rail as full-scale, each LSB is roughly 40 µV, so the hysteresis from one cycle alone can amount to roughly 6–7 LSBs of offset. If the allowed offset limit is only a few LSBs, hysteresis cannot be treated as a minor term: it must be a first-class item in the budget alongside initial accuracy and tempco.

Factory calibration interacts strongly with hysteresis. If calibration is performed at room temperature and the unit later experiences wide temperature excursions in the field, the offset seen when it returns to room temperature will reflect both calibration accuracy and hysteresis. If calibration is performed at an extreme temperature, such as +85 °C, the offset at room temperature immediately afterwards may be shifted by the specified hysteresis figure. In both cases it is worth reserving a specific part of the calibration budget for hysteresis and validating it with a small number of devices in a temperature chamber.

Package and temperature grade provide additional levers. Plastic SMD references are cost-effective but tend to exhibit more stress-induced offset with cycling than ceramic or metal packages. Higher temperature grades such as AEC-Q100 Grade 0 and Grade 1 are qualified for wider ranges and more aggressive cycling, but the published hysteresis figures may also be larger. For designs that live within a narrower range, using a device specified only over −40~+85 °C can be a good compromise so long as hysteresis is still comfortably inside the budget for the actual mission profile.

Finally, consider how many severe temperature cycles your product will see over its lifetime. Many datasheets provide only single-cycle data. As a first approximation you can treat each cycle as adding a random offset of that order of magnitude, with the overall effect growing roughly with the square root of the number of cycles. Critical designs should replace this estimate with real measurements over several cycles. Figure F6 contrasts thermal hysteresis with tempco and long-term drift along the lifetime axis and emphasises that it is a discrete, event-driven effect.

Lab Validation for Start-Up & Pre-Bias

Bench validation of start-up behaviour fills the gaps left by datasheets. A practical setup combines a programmable VIN source with controlled ramps, a configurable load and output capacitor board, a way to inject pre-bias into the Vref node and a scope or high-resolution ADC to capture the waveform. The goal is to explore conditions that are harder to characterise in production, such as very slow VIN ramps, heavy load at power-up and realistic pre-bias paths.

A simple test matrix covers three main axes: VIN ramp slope, pre-bias level and the combination of Cout and Iout. For ramp slope, it is useful to test an almost step-like fast ramp, a nominal ramp similar to the end application and a very slow ramp that mimics cold-crank or brown-out. For pre-bias, sweeping from zero to fractions such as 0.2, 0.5 and 0.8 times Vref reveals whether internal start-up circuitry can overcome realistic clamp and leakage paths. For Cout and Iout, exercise the datasheet range plus the actual worst-case configuration planned on the board.

For each point in the matrix, the waveform is judged against three criteria. First, whether the start-up is monotonic or exhibits secondary steps and plateaus. Second, whether any overshoot stays within an acceptable band and settles within a defined time before downstream ADCs or comparators become active. Third, whether there are any latch-off or meta-stable states that require extra reset actions. Classifying conditions as PASS, MARGINAL or FAIL makes it easier to translate bench observations into clear design rules.

The final step is to turn lab results into acceptance criteria for specifications and PRDs. That includes capturing the safe range of VIN ramp slopes, the maximum start-up and settling times under worst-case load, the range of pre-bias levels where correct start-up is guaranteed and the minimum delay or ready signal required before enabling conversions and fault decisions. With this information written into design documents, future changes of reference type, package or operating range can be checked against a known baseline.

Thermal Hysteresis Measurement & Screening

Thermal hysteresis tests translate high-level ppm figures into real offsets on your own boards. A straightforward setup combines a temperature chamber, a stable supply for the reference, a controlled load and a meter or high-resolution ADC with enough resolution to resolve a few tens of microvolts. Devices are cycled through a defined temperature profile while Vref is recorded at well-defined points, especially at the starting temperature before and after the cycle.

A common profile is room temperature to low temperature, then to high temperature and back to room temperature. At each plateau, the system is allowed to soak so that the reference, PCB and package reach thermal equilibrium before measurement. Vref at the initial room temperature is captured as a baseline; after the full cycle, the room-temperature Vref is measured again. The difference between these two readings, normalised to the nominal reference value, is the hysteresis for that cycle expressed in ppm.

To separate hysteresis from tempco, noise and measurement drift, averaging and careful timing are essential. Several readings at each temperature point reduce noise. The tempco itself is characterised by the Vref changes between the low, high and intermediate temperatures, while hysteresis is the offset between room-temperature readings before and after the cycle. Instrument drift can be monitored using a secondary reference channel or a built-in calibration routine so that it does not masquerade as device hysteresis.

For critical applications such as aerospace and automotive safety domains, conditions are often tightened. That may mean more cycles, wider temperature spans, tighter acceptance limits or screening out devices with unusually large hysteresis. In general industrial and consumer equipment, a small sample across one or two representative cycles is usually enough to confirm that hysteresis stays comfortably inside the budget derived from the datasheet and system-level error analysis.

BOM & Procurement Notes (Start-Up & Thermal Hysteresis)

Small-batch buyers and design engineers rarely write start-up behaviour and thermal hysteresis explicitly into their BOM or PRD, even though these hidden behaviours can dominate system accuracy. This section gives a set of fields you can copy into your requirements so that vendors and distributors shortlist references that genuinely meet your start-up and hysteresis needs.

Core Electrical Fields

• Vref and accuracy tier: e.g. “Vref = 2.5 V, initial accuracy ≤ ±0.05 % at 25 °C.”
• Effective system accuracy: clarify whether the accuracy limit applies after start-up and one temperature cycle over the full operating range.
• Noise and PSRR budget: if relevant, state the allowable noise and PSRR impact on your ADC or comparator thresholds.

Start-Up Guarantees

Start-up behaviour should be captured in a few clear, testable sentences rather than left as an implied datasheet detail.

• Start-up time at defined load and Cout: “Max start-up time ≤ 1.5 ms at Vref = 2.5 V, Iout = 5 mA, Cout = 1 μF, VIN ramp ≥ 1 V/ms.”
• Pre-biased start-up compatibility: “Start-up must be guaranteed for output pre-bias between 0 and 0.8 × Vref with pre-bias current ≤ 1 mA.”
• Soft-start expectations: “Soft-start is acceptable if Vref reaches 99 % of final value within 2 ms; no extended plateau beyond 10 ms is allowed.”

Thermal Hysteresis Requirements

• Quantitative limit: “Thermal hysteresis ≤ 100 ppm per cycle over −40 to +85 °C, one cycle, as defined by the vendor.”
• Data requirement (when no hard limit): “If no guaranteed limit is available, provide typical hysteresis versus temperature range and test conditions.”
• Thermal cycling report for safety-critical rails: “For automotive or safety rails, provide a temperature cycling and hysteresis report including sample size, conditions and acceptance criteria.”

Temperature Grade, Package and Reflow

• Temperature grade: specify at least “Industrial −40 to +85 °C” or automotive “AEC-Q100 Grade 1” or better where required.
• Package type and height: e.g. “DFN, MSOP or SOIC only, maximum package height X mm, isolation or creepage requirements if relevant.”
• Reflow budget: “Device must tolerate at least three lead-free reflow cycles according to the vendor’s recommended profile.”

Example Reference Families Across Brands

The following reference families illustrate the class of devices that typically offer well-documented start-up behaviour, good long-term stability and usable thermal hysteresis information. They are examples to guide your sourcing and second-source planning, not a fixed shortlist.

Compatibility Risks to Flag

• Different brands can use very different internal start-up circuits even for pin-compatible, same-voltage references; pre-bias behaviour and overshoot may not match.
• Many hysteresis figures are typical-only. The real production spread must be clarified with vendor FAEs or validated in your own temperature chamber.
• When reusing a legacy design, replacing the reference without re-checking start-up and hysteresis can break power-up sequencing, comparators and calibration flows.

FAQs: Start-Up Behaviour and Thermal Hysteresis

These questions focus on the practical problems you hit when reference rails leave the ideal datasheet world and enter real boards. Each answer is kept short enough to reuse in support docs, internal wikis or search snippets, while still pointing to the checks that matter for precision systems.