Link integrity is about turning “link-up but unstable” symptoms into measurable physical causes (loss, reflection, crosstalk, clock/SYSREF timing)
and fixing them with repeatable bring-up steps and proof-by-BER.
This page provides practical rules, measurement workflows, and selection questions for LVDS/JESD links so margin is designed, verified, and maintained
across real-world events and corner conditions.
What this page solves
This page turns common high-speed link symptoms into physical root causes and concrete actions that can be measured and repeated.
It focuses on LVDS and JESD204 link integrity: eye margin, reflections, loss/ISI, crosstalk, return-path continuity, and how these impact CDR lock and Subclass-1 alignment.
Typical failure symptoms
Link comes up, then drops frames or packets
Intermittent bit errors (BER spikes) under load, temperature, or EMI events
Eye diagram fails margin targets or collapses with certain patterns
CDR occasionally loses lock or relocks unpredictably
A repeatable workflow: measure first, change one variable, verify with eye and BER tools
Link Integrity fundamentals: what an eye diagram really tells
Eye diagrams are a fast visual summary of sampling margin. They show how timing and amplitude headroom changes with channel loss,
reflections, crosstalk, and jitter. A healthy-looking eye can still fail at low BER, so eye checks should be paired with BER/PRBS validation.
Eye basics (minimum set)
UI (unit interval) is the time width of one bit; eye width is the usable timing window.
Eye height is amplitude headroom; it shrinks with loss, noise, and crosstalk.
Crossing behavior hints at imbalance, termination issues, and reflection-driven ringing.
RJ vs DJ: random jitter blurs the eye; deterministic jitter warps it (often from ISI/reflections/crosstalk).
Channel “big three” that shape the eye
Insertion Loss (IL) increases ISI and reduces eye height/width (frequency-dependent attenuation).
Return Loss (RL) indicates reflections; poor RL often shows up as edge ghosts and ringing.
Crosstalk (NEXT/FEXT) injects pattern-dependent noise bursts, shrinking the eye unpredictably.
LVDS link integrity: source-synchronous rules that actually hold
LVDS failures are rarely “mystery protocol issues.” Most problems are physical: impedance discontinuities, broken return paths,
data-to-clock skew, and reflections from vias or connectors. The goal is to keep the differential channel stable and repeatable so
the receiver sees a consistent sampling window across temperature, load, and board-to-board variation.
The four LVDS variables that dominate SI outcomes
Differential impedance: target 100Ω, but continuity matters more than a perfect nominal value.
Return path: a continuous reference plane prevents hidden inductance and reflection-like behavior.
Data-to-clock skew: in source-synchronous links, relative timing is the first priority.
Termination: the right strategy turns reflections into a non-issue instead of deterministic jitter.
Skew priorities (source-synchronous LVDS)
DATA ↔ CLK skew is more critical than absolute trace length; sampling margin is set by the clock edge at the receiver.
DATA ↔ DATA skew matters for bus alignment, but it is usually secondary to DATA ↔ CLK alignment.
Prefer structural consistency (same layers, same via count, same reference plane) before using serpentine compensation.
Termination decision logic (keep it measurable)
Receiver termination is the default for point-to-point links when reflections must be minimized at the sampling end.
Source termination can be effective when the driver edge and near-end reflection dominate the eye shape.
Split termination helps control common-mode and bias requirements when the receiver expects a defined midpoint.
AC termination is used when DC loading or biasing constraints require blocking the termination’s DC path.
JESD204B/C physical channel: loss, ISI, and when EQ or a retimer is unavoidable
JESD lanes run at multi-Gbps, so channel behavior is dominated by frequency-dependent insertion loss and the ISI it creates.
The practical workflow is to estimate channel loss by segment, apply the least-aggressive equalization that restores margin,
and only add a retimer when the channel exceeds what receiver EQ and layout discipline can realistically recover.
Why JESD needs channel thinking (not guesswork)
Higher lane rate shrinks UI, so ISI eats timing margin quickly.
Insertion loss reduces edge energy; the receiver sees blurred transitions and a closed eye without EQ.
Reflections and connector discontinuities create deterministic patterns that EQ cannot always “average away.”
Equalization building blocks (concept-level, action-focused)
CTLE: boosts high-frequency content to counter loss, but can amplify high-frequency noise.
DFE: cancels post-cursor ISI, but aggressive settings can cause mis-decisions and error bursts.
Strategy: tune for BER improvement, not for the “prettiest” eye under a single pattern.
Redriver vs retimer (decision framing)
Redriver reshapes the analog signal; it helps moderate loss but does not fully break accumulated jitter/ISI.
Retimer recovers clock and retransmits; it can reset margin across multiple connectors or long cables.
Use a retimer when the channel is long, connector-heavy, or beyond what receiver EQ can reliably compensate across corners.
CDR behavior and lock stability: what the link must deliver
A CDR does not “care” about a pretty static eye capture. It reacts to the input jitter spectrum, residual ISI after EQ,
and low-frequency wander that pushes its tracking loop. A link can pass a quick eye check yet still suffer lock drops when
supply noise, return-path discontinuities, or slow disturbances modulate the effective edge timing.
What drives CDR stability (link-side view)
ISI: loss and discontinuities blur transitions and create deterministic edge shifts across patterns.
RJ: broadband noise widens the timing distribution and reduces sampling margin.
LF wander: slow disturbances (supply/return-path coupling, EMI events) push the tracking loop and can trigger lock drops.
Symptom → likely cause mapping (fast triage)
Eye width shrinks → ISI / deterministic jitter (discontinuities, via stubs, connectors) or increased jitter.
Eye height drops → insertion loss, noise, or crosstalk bursts (often pattern or activity dependent).
Occasional lock drop → low-frequency disturbance, supply/ground coupling, or return-path issues that modulate edge timing.
Minimum stability check (repeatable)
Track lock status and error counters over time, not just a single capture.
Correlate lock drops with events (load steps, switching, temperature changes) using timestamps.
Validate improvements with BER/PRBS under worst-case conditions, not only at room temperature.
SYSREF provides a repeatable phase reference used to establish deterministic alignment (LMFC-related state). When SYSREF quality
degrades, arrives outside the allowed skew window, or picks up edge jitter from coupling, Subclass-1 repeatability can fail even
if lanes appear to run normally.
Three link-integrity failure modes for SYSREF
Waveform quality issues: reflection, overshoot, or unstable threshold crossings create time uncertainty.
Skew out of window: routing, fanout, or buffer-path mismatch makes devices see SYSREF at different times.
Edge jitter from coupling: noise or crosstalk adds edge timing variation that collides with sampling windows.
Practical rules that improve repeatability
Use a clear fanout topology and keep branch paths structurally consistent (layers, vias, buffers).
Manage equivalent delay rather than only “trace length,” especially when buffers or connectors are involved.
Treat SYSREF like a timing signal: control termination, avoid discontinuities, and keep it away from aggressors.
Measurement & bring-up workflow: measure, isolate, and converge
Reliable bring-up depends on a measurement plan that isolates layers. Eye diagrams help compare margin quickly, but they can be
distorted by probes, fixtures, and reference-plane choices. PRBS/BER tools remove protocol variables and quantify stability over
time. The most efficient workflow validates the physical layer first, then SYSREF/LMFC alignment, and only then protocol configuration.
PRBS isolates the physical layer by removing packet framing and higher-layer variability.
Use PRBS/BER when the link is up but unstable, when errors are intermittent, or when EQ/retimer decisions must be validated.
Built-in PRBS, loopback, and error counters enable fast responsibility splits: TX/RX/channel.
Three-step localization (do not reorder)
Physical layer: eye/BER, lock status, and error counters under time and corner conditions.
Alignment: SYSREF/LMFC repeatability across resets, temperature, and supply events.
Protocol configuration: only after physical and alignment evidence is stable and repeatable.
Engineering checklist (tick-box ready)
This checklist is designed for design reviews and bring-up. Each item is a hard requirement with minimal evidence keywords.
Use it to keep link integrity decisions consistent across PCB spins, connector choices, and lane-rate upgrades.
1) Channel & impedance
☐ Differential routing class defined (100Ω class) — evidence: stackup / solver / TDR
☐ Reference plane is continuous along the full path — evidence: layout review
☐ Connector/backplane/cable has a model or loss spec — evidence: vendor curve / S-params
☐ Layer transitions are minimized and structurally consistent — evidence: via count parity
☐ Measurement reference plane is defined for validation — evidence: test points / fixture plan
☐ RX/SerDes supplies are decoupled and return paths are short — evidence: PDN review
☐ Low-frequency disturbance sources are identified — evidence: event list / log tags
☐ Lock drops and retrain events are measurable — evidence: counters / status reads
☐ Stability is tested across corners (temp, load, EMI events) — evidence: run logs
☐ Changes are validated with BER + lock stability, not only with eye — evidence: before/after
6) SYSREF (Subclass-1)
☐ Fanout topology is defined and repeatable — evidence: tree diagram
☐ Equivalent delay is matched across branches — evidence: path parity / buffer parity
☐ Termination and threshold crossings are stable — evidence: waveform check
☐ Skew window is budgeted and verified — evidence: window plot / markers
☐ SYSREF is isolated from aggressors — evidence: keepout / placement
Application patterns that stress link integrity (topology-driven)
The patterns below focus on channel topology and stability risks (loss, reflection, coupling, lock drops). They intentionally do
not discuss ADC architecture or protocol register tuning. The goal is to identify where margin is typically consumed and what
decisions must be made early to avoid bring-up dead ends.
Pattern A — Multi-channel JESD over connector/backplane/cable segments
System margin is set by the worst lane. Lane-to-lane variation (connector launches, via fields, routing escapes) dominates multi-lane success.
Model availability becomes a hard requirement. If S-parameters/AMI guidance cannot be obtained, bring-up becomes trial-and-error.
EQ decisions must cover corners. A setting that “looks good” on one lane or one card does not guarantee multi-lane stability over temperature and events.
Pattern B — Multi-card expansion (multiple channel segments) and retimer placement
Multiple discontinuities matter more than “total length.” Every connector/launch adds reflection and ISI that stacks across segments.
Retimer placement is a topology decision. Insert a retimer where it breaks the worst segment and restores margin before the receiver runs out of EQ capability.
Redriver vs retimer is not interchangeable. A redriver is linear shaping; a retimer re-times and can reset accumulated impairment.
Pattern C — Industrial long runs (EMI/ESD) with LVDS (link-side view)
Errors are often event-driven bursts (switching, motor events, ESD) rather than a smooth BER increase.
Common-mode control matters. Return paths, shielding reference, and connector grounding affect both robustness and emissions.
Protection must preserve the differential channel. Any protection or filtering must be checked for bandwidth and impedance impact (details handled elsewhere).
This page does not recommend a single part. Instead, it provides the fields to request, the risks those fields control, and a
copy-ready inquiry template. Example material part numbers (MPNs) are included only as reference points to align conversations
with suppliers and to request comparable alternatives with complete modeling support.
Must-ask fields (grouped by component type)
Component type
Fields to request
Evidence to ask for
Redriver / Retimer
Lane rate range • EQ type (CTLE/DFE) • compensation range • additive jitter • reference clock requirement • latency/consistency • diagnostics/counters
Improve waveform quality • match equivalent delays • keep SYSREF away from aggressors • verify skew window
Rule of thumb: If a fix cannot be proven with long-run counters/BER across corners, it should be treated as an experiment, not a solution.
Copy-ready supplier inquiry template
Project: High-speed differential link integrity (JESD/LVDS), topology: [single-board / multi-card / cabled]
Lane count & rate: [# lanes] @ [Gbps per lane], channel segments: PCB + [connector/backplane] + [cable length if any]
Targets:
- Long-run stability: no lock drops / no retrain events within [time window]
- BER / error counters: PRBS-based verification under [temperature/load/EMI events]
Questions to confirm:
1) Does the device support our lane rate range and topology?
2) What EQ options are available (CTLE/DFE), and what channel loss range is supported at our target rate?
3) Additive jitter contribution (typ/max) and any reference clock requirements (if retimer).
4) Latency behavior and consistency across resets/temperature (relevant to alignment budgets).
5) What diagnostics are available (lock status, error counters, recommended test modes)?
Required deliverables:
- Datasheet with measurement conditions
- IBIS-AMI model (or equivalent) and a reference simulation flow
- Recommended layout/termination guidance and reference designs
- For connectors/cables: S-parameters + insertion/return loss plots over frequency
FAQ — Link integrity (answers + structured checks)
Each answer includes a compact “data-style” checklist: symptom → likely cause → measurements → knobs → pass criteria.
Use the tables to keep bring-up decisions evidence-driven and repeatable.
Eye looks open but still BER errors — why?
A single eye capture is not a BER guarantee. BER is a long-run statistical outcome affected by jitter spectrum, burst noise,
pattern-dependent ISI, and measurement setup differences.
Prove stability with PRBS/BER over time and corners (temperature, load switching, EMI events).
Keep the reference plane and fixture consistent; otherwise eye comparisons are not valid.
Correlate errors with events (power transients, motor/inverter switching) using timestamps.
BER target met across corners with no lock drops / retrains in the test window
Common trap: Comparing eyes measured at different fixtures or planes and treating the “bigger eye” as the true channel improvement.
When is a retimer mandatory for JESD204C?
A retimer becomes mandatory when receiver EQ cannot recover the eye margin across the intended topology and corner conditions,
or when accumulated impairments across multiple segments cause training instability or lock drops.
Use retimer if long-run PRBS BER cannot be met with reasonable EQ and topology is multi-segment (connectors/backplane/cable).
Use retimer if stability depends on a fragile “sweet spot” EQ setting that fails across temperature/load events.
Require models (S-params / IBIS-AMI) to predict feasibility before spin.
Trigger
EQ cannot meet BER/stability across corners
Topology signs
Multiple connectors, backplane, long cable, repeated discontinuities
Measurements
PRBS BER over time, lock drops, training repeatability
Placement logic
Insert where it breaks the worst segment before margin collapses at RX
Pass criteria
Stable training + BER target met with margin across lanes and corners
Common trap: Using a retimer as a substitute for fixing obvious reflections (launch/via/termination) that will still break stability.
What measurements separate reflection vs loss vs crosstalk?
Reflection, loss/ISI, and crosstalk leave different signatures. The fastest separation comes from combining time-domain evidence
(where the disturbance occurs) with frequency-domain evidence (how the channel attenuates and distorts).
Reflection: time-localized echoes/ringing linked to launches, vias, connectors.
Loss/ISI: slower edges, closed eye mainly from insertion loss and bandwidth limits.
Crosstalk: errors correlated with neighbor activity (aggressor toggling).
Impairment
Best evidence
Fast action
Reflection
TDR/step response echoes; eye ringing at fixed delays
Increase spacing; preserve return path; keepout from aggressors
Common trap: Treating every closed eye as “loss,” then over-driving EQ while leaving the real reflection source untouched.
How to set CTLE/DFE without amplifying noise too much?
EQ should be selected by measurable stability, not by the “largest eye.” Start with the least aggressive settings that
meet BER and lock stability; higher EQ can amplify noise and create false margin.
Use a stepwise sweep: CTLE first, then add DFE only if needed for BER.
Choose the minimum-pass setting: lowest EQ that meets BER across corners.
Validate with long-run counters; eye snapshots are secondary.
Goal
Meet BER and lock stability with minimum EQ
Order
CTLE sweep → DFE add-on → re-check BER
Watch-outs
Noise amplification, mis-detection on bursts, fragile “sweet spots”
Evidence
BER vs EQ sweep table; lock drops vs EQ
Pass criteria
Stable BER margin across temperature/load events
Common trap: Picking EQ by “best-looking eye” while ignoring long-run counters and event-driven lock drops.
Why does CDR lose lock only during motor/inverter switching events?
Event-driven lock loss usually indicates low-frequency wander or burst coupling into the receiver timing path. Switching events
can disturb return paths, inject noise, or modulate thresholds, creating timing excursions large enough to break tracking.
Timestamp errors and correlate with switching states and load steps.
Check return-path continuity and keep sensitive lanes away from high dV/dt aggressors.
Validate improvements by repeating event tests, not by idle-only measurements.
Lock status logs, error bursts vs event timestamps, repeatability across events
Knobs
Improve return path, reroute away from aggressors, shielding/ground reference consistency
Pass criteria
No lock drops under repeated worst-case switching sequences
Common trap: Declaring “fixed” after idle bench testing without reproducing the real switching event stress.
What SYSREF skew budget is “safe” and how to verify it?
“Safe” depends on the device’s alignment window and the system’s deterministic timing requirements. The reliable approach is
to budget skew against the allowed window, then verify repeatability across resets and corners with waveform-quality checks.
Overshoot/ringing, stable threshold crossing, clean edges at the device pins
Verification
Alignment repeatability across resets; log alignment failures and jitter-sensitive events
Knobs
Topology consistency, termination, keepout from aggressors, path parity
Pass criteria
Alignment succeeds repeatedly with stable SYSREF edges under corners
Common trap: Treating skew as “trace length only” while ignoring buffer paths and topology differences.
Can SYSREF be routed like any other LVDS signal?
SYSREF should not be treated as “just another LVDS pair.” Its edge timing directly impacts deterministic alignment; waveform
integrity and arrival consistency matter more than average amplitude.
Control termination and discontinuities to avoid ringing that shifts threshold crossing time.
Use a consistent fanout topology and match equivalent delays across branches.
Keep SYSREF away from aggressors (fast switching, high-speed lanes) to reduce edge jitter injection.
Priority
Edge timing repeatability over “pretty amplitude”
Main risks
Ringing → time uncertainty; skew mismatch; coupling → edge jitter
Measurements
Waveform quality at device pins; skew window verification; reset repeatability
Clean edges + alignment repeatability across corners
Common trap: Routing SYSREF through “convenient” paths that cross splits or pass aggressors because it is “only a pulse.”
LVDS length matching: data-data vs data-clock — what matters most?
For source-synchronous LVDS, the key variable is the relative skew between data and clock at the receiver. Absolute length
is less important than consistent reference planes, controlled impedance, and stable termination.
Match data-to-clock within the interface tolerance; then keep data-data skew consistent inside the group.
Avoid “over-serpentine” that creates impedance ripple and extra discontinuities.
Prioritize reference-plane continuity and termination placement.
Plane splits, via asymmetry, serpentine impedance ripple
Measurements
Timing margin/eye at RX, error counters under activity, TDR for discontinuities
Pass criteria
Stable operation across activity patterns without intermittent errors
Common trap: “Perfect length match” that adds excessive serpentine and worsens impedance and crosstalk.
Do connectors dominate SI more than PCB traces at multi-Gbps?
Not always, but connectors are strong discontinuity points and can dominate quickly when there are multiple launches,
stack-height variations, or poor return loss. The only reliable way to decide is to use models and segment budgets.
Request S-parameters for the connector launch and measure return loss sensitivity.
Count discontinuities: multiple connectors/backplane transitions often dominate over a single controlled PCB segment.
Validate by swapping connector variants or removing one discontinuity in a controlled experiment.
Decision input
S-params, IL/RL curves, launch structure, count of transitions
Connector-dominant signs
Ringing/echo at fixed delays; strong RL issues; sensitivity to stack/mating
Trace-dominant signs
Smooth IL slope with length; predictable rate/length degradation
Measurements
TDR for discontinuities; BER vs topology changes; eye/BER per segment
Pass criteria
Margin sustained after worst discontinuities are validated or mitigated
Common trap: Assuming “short PCB traces” guarantee success while ignoring multiple connector launches and their return loss.
How to use PRBS/BERT to isolate physical layer issues?
PRBS/BERT removes protocol variables and gives a clean physical-layer verdict. It is most effective when paired with
controlled topology changes and a strict order: physical layer → alignment → protocol.
Run PRBS long enough to expose intermittent issues; log error counters and lock status over time.
Change only one variable at a time (EQ, termination, topology segment) and re-run PRBS.
After physical stability is proven, move to SYSREF/LMFC alignment verification.
Common trap: Tuning protocol settings to “mask” an unstable physical layer that PRBS would reveal immediately.
Why do equalizers sometimes worsen spurs/noise in captured data?
Strong EQ can increase sensitivity to noise and interference by boosting high-frequency content and by making decisions on a
noisier waveform. This can convert small impairments into burst errors or visible artifacts downstream.
Prefer “minimum-pass” EQ verified by BER, not maximum shaping.
Re-check aggressor coupling and event-driven errors after enabling stronger EQ.
Consider retimer when EQ must be overly aggressive to meet BER.
BER target met with less aggressive EQ and stable lock under events
Common trap: Increasing EQ until an eye “looks good,” then accepting new event-driven errors as “random.”
How to decide between redriver and retimer?
Choose a redriver when linear equalization can restore margin with stable BER across corners. Choose a retimer when the channel
requires re-timing to reset accumulated impairment or when stability and training are not repeatable with linear shaping.
Redriver: single-segment or mild multi-segment channels where EQ solves loss/ISI without fragile settings.
Retimer: multi-segment channels (connectors/backplane/cable) where lock drops or training failures persist.
Make the decision using BER + stability logs, not only eye snapshots.
Decision factor
Redriver
Retimer
Channel type
Mostly linear loss
Multi-segment + accumulated impairment
Stability
Repeatable BER with mild EQ
Lock drops / training fragile without re-timing
Evidence
BER vs EQ stable across corners
BER improves + stability returns across corners
Pass criteria
Meets BER without brittle settings
Meets BER with repeatable training and lock stability
Common trap: Choosing by lane rate alone instead of by topology and long-run stability evidence.
