A DAC with Sample-and-Hold (S/H) separates the update event (writing a new code) from the valid output window (when the output must stay flat and predictable). This is the practical fix when “writing” and “using” the analog output cannot happen at the same time without causing errors.

The three failure modes that S/H eliminates

• Update glitch disturbs the load: the DAC’s code transition injects a short, code-dependent transient that can trigger comparators, disturb bias nodes, or kick a control loop.
• Sampling overlaps settling: the receiving system (ADC, comparator, demodulator, timing gate) observes the output while it is still settling, so “valid” measurements become dependent on update timing rather than true output value.
• Multi-channel timing drift: channels update at slightly different times (skew), creating phase errors that appear as mismatched control vectors, inter-channel ripple, or unwanted modulation.

When S/H is the correct tool

• Synchronous control outputs: phase-aligned updates across multiple channels with a defined “effective” time.
• Gated / scanned outputs: the output must remain quiet during a measurement window, while updates happen elsewhere.
• External sampling systems: an ADC or comparator samples the DAC output; the sampling point must always land in a stable window.
• Disturbance-sensitive loads: bias rails, precision references, or high-gain analog nodes where short transients matter.

Key takeaway: the goal is not “a smoother DAC,” but a defined valid window that remains stable even while the system is updating.

A practical timing dictionary (only what matters for hold)

• tUPDATE: the moment a new DAC code is latched (or an update strobe is asserted).
• tSETTLE: time for the output to enter (and remain within) the target error band after an update (e.g., to 0.5 LSB, 1 LSB, or a specified %).
• tHOLD: duration where the output is held constant by the S/H action.
• tAPERTURE / tDELAY: the delay from the trigger to the effective hold boundary (where track ends and hold begins).
• ΔtSKEW: channel-to-channel timing mismatch of the effective hold boundary (or update event), which consumes timing margin.

Define “valid output window” as an engineering contract

The output is valid only in the portion of the hold window that starts after settling completes and includes a guard margin to cover uncertainty (temperature drift, load variation, probe loading, and channel skew). In other words: the hold window is necessary, but not sufficient; validity starts only when the error band requirement is met.

Back-solve timing from the system sampling point

Many systems start from a fixed sampling time (an ADC sample instant, a comparator latch, a modulation boundary, or a gated measurement window). The safe approach is to anchor that sampling point inside the valid region, then allocate budget backward: update must occur early enough to finish settling, while skew and uncertainty must fit inside the remaining margin.

• If the sampling instant is fixed, tUPDATE is constrained by tSETTLE plus margin.
• If the hold window is fixed, ΔtSKEW reduces the usable valid region across channels.
• If the load varies, the margin must cover worst-case settling and droop behavior (validated by measurement, not guesswork).

Multi-channel timing: what “synchronous” must guarantee

“Synchronous updates” should be interpreted as a measurable alignment of the effective output moment (the hold boundary and subsequent valid region), not merely a shared digital write. The contract for multi-channel control is: all channels must present stable outputs during the same valid region, and the remaining skew must be smaller than the system’s allowed phase error.

Sample-and-hold is not just a feature label. It is a physical hold node: the exact point where a capacitor (or an equivalent internal element) must store charge so the output stays quiet during the valid window. That location determines the dominant error path: glitch injection at the hold boundary, droop during hold, and load sensitivity that can shrink the valid region.

Three implementation styles and what they really trade

A minimal decision rule: pick the hold node first, then validate the window

• If inter-channel alignment is the top priority, prefer a solution with a vendor-defined hold boundary and a clear skew specification.
• If the hold node must be placed near a disturbance-sensitive circuit, external S/H can work, but only with measured injection and droop.
• If the load is capacitive / remote / protected, use buffering and isolation so load behavior cannot collapse the valid region.
• Regardless of implementation, the output window is valid only when settling + margin fits inside the hold window (as defined in the timing model).

During a hold event, the output is “quiet” only if the hold node stores charge without being disturbed. The dominant disturbance mechanism is not a slow error; it is a fast, edge-driven charge transfer that produces a short transient at the hold node. In practice, the low-glitch goal means: minimize the net charge injected into C_HOLD and prevent clock edges and simultaneous switching from coupling into the hold node.

The three glitch sources (think in “charge paths”)

• Charge injection (Q_inj): when a switch turns off, channel charge is pushed into the hold node. This creates a step at the capacitor: a hold-step that directly corrupts the valid region.
• Clock feedthrough: fast edges couple through parasitic gate capacitances and package/trace capacitance into the hold node. Even if average charge is small, the peak transient can violate disturbance limits.
• Code-dependent switching (major carry): certain code transitions flip many internal switches at once. The resulting transient energy couples into the output path, then into the hold node—often creating the largest code-dependent disturbance.

A useful engineering model: the hold-step is set by charge over capacitance

At the hold boundary, a disturbance becomes a voltage step on the hold capacitor. A first-order estimate is: ΔV ≈ Q_inj / C_HOLD. This captures the correct knob (capacitance) and the correct enemy (net injected charge), but it also exposes the real trade: larger C_HOLD reduces ΔV yet can slow settling and stress buffer stability.

Suppression tactics that preserve the valid window

• Windowing / gating: schedule code updates outside the measurement window so any transient cannot be observed inside the valid region.
• Symmetric switching: complementary or balanced switch structures reduce net Q_inj so the hold-step is smaller and less code-dependent.
• Segmented updates: avoid worst-case “all-at-once” switching during sensitive intervals; reduce major-carry disturbance when system timing allows.
• RTZ / NRZ only in hold context: choose output behavior that makes the hold boundary easier to keep quiet; any RTZ tradeoffs belong to the system window contract.

The objective is consistent: protect the valid region by controlling charge injection and edge coupling at the hold node.

“Flat” is not a visual straight line. It is an engineering contract: during the valid region, the held output must remain inside the target error band. This requires two conditions at the same time: (1) the output has settled after the update, and (2) the output does not drift or get disturbed by leakage and loading while held.

Droop mechanisms (think in charge loss and equivalent currents)

• Leakage paths: switch leakage, ESD/clamp leakage, PCB surface leakage (humidity/contamination), and package parasitics slowly remove charge from the hold node.
• Buffer/input bias: input bias currents of the buffer or the receiving stage can source/sink charge from C_HOLD, producing a predictable but temperature-dependent droop slope.
• Static buffer error under load: output stage headroom, finite output resistance, and PSRR create slow shifts with supply and load changes.
• Load steps & sampling kickback: a load transient (or downstream sampling capacitor) can pull charge from the hold node, appearing as a step or burst that can violate the valid region even if average droop is small.

Map the problem to measurable specifications

A common trap: bigger C_HOLD is not automatically better

• A larger C_HOLD usually reduces hold-step amplitude, but it demands more charge during updates and can extend settling time.
• The buffer may become less stable with large capacitive loading, creating ringing or slow recovery inside the hold window.
• Startup and gating transients can become more visible when the hold capacitor dominates the node dynamics.

The correct approach is to size C_HOLD to meet both the step disturbance limit and the settling + stability limits, then validate with worst-case code transitions and worst-case load.

“Synchronous” must be defined at the effective output moment: the hold boundary and the subsequent valid region. A shared digital write is not sufficient if channel-to-channel delay shifts the valid region. The alignment contract is: all channels present stable outputs during the same valid region, and remaining skew stays below the allowed phase error.

Skew sources (layered by what can be controlled)

• Trigger distribution: fanout delay, asymmetry in a trigger tree, and edge-rate degradation across connectors.
• PCB interconnect: unequal trace length, different reference planes, and return-path discontinuities that change edge timing.
• Channel dispersion: device internal delay mismatch and aperture dispersion of the S/H boundary that shifts when the node is effectively held.
• Environmental drift: temperature and supply variation that move delays and buffer behavior, shrinking shared valid region margin.

Alignment strategies (system actions, not interface internals)

• Single-source trigger tree: distribute one edge through a symmetric fanout so each channel sees the same timing reference.
• Trace and reference matching: route critical timing lines with matched length on the same layer over a consistent return plane.
• Adjustable delay: add controllable timing trim so the effective hold boundary can be aligned in bring-up and recalibrated if needed.
• Define the sample point: pick a sampling instant inside the shared valid region, then ensure all channels’ skew fits inside the margin.

Acceptance approach: budget Δt to phase error and to control error

Start from the system tolerance: the maximum allowable timing mismatch between channels. Treat it as a budget and allocate it to trigger distribution, routing, and channel dispersion. The system passes when the worst-case total skew remains below the shared valid-region margin across temperature and load.

External sample-and-hold succeeds or fails at the hold node. The network around that node must simultaneously satisfy four competing requirements: droop (charge retention), noise/disturbance rejection, settling (window timing), and stability (no ringing inside the valid region). Treat the hold capacitor and its driver as a system, not as isolated parts.

C_HOLD selection: droop, noise, bandwidth, and stability are one trade

• Droop target: a larger C_HOLD reduces droop for the same leakage and bias currents, extending how long the output stays within the error band.
• Disturbance sensitivity: a larger C_HOLD is harder to disturb by short impulses, but it also stores more charge and can amplify startup and gating transients.
• Settling budget: a larger C_HOLD demands more charge during updates, often increasing t_SETTLE and shrinking the usable valid region.
• Stability margin: C_HOLD is a capacitive load. If the buffer is not stable for that load, ringing can violate the valid region even if droop is slow.

Practical rule: size C_HOLD against the allowed hold-step + droop first, then confirm the design still meets settling-to-band and no-ringing limits.

Isolation R and small RC: damping and protection that costs settling time

• Why R_iso helps: it isolates the buffer from the full capacitive load, improves phase margin, and reduces ringing and charge “snap” into C_HOLD.
• What it breaks: R_iso adds a time constant with C_HOLD and downstream capacitance. More damping usually means longer settling.
• How to tune safely: every R_iso change must be validated by measuring settling-to-band and overshoot peak for worst-case code transitions.

Buffer stability: required verification actions (not just a datasheet sentence)

• Step response at two amplitudes: test a small step (typical update) and a major step (worst-case transition) and record overshoot, ringing, and settling-to-band.
• Worst capacitive corner: include C_HOLD, cable capacitance, ESD diode capacitance, and ADC sampling capacitance in the load model.
• Temperature and supply corners: verify that bias currents (droop) and phase margin (ringing) remain acceptable across the full operating range.
• Measurement integrity: use a probing method that does not add large ground inductance or probe capacitance that changes ringing and settling.

Cable / ADC / clamps: how the downstream system disturbs the hold node

• ADC sampling kickback: a sampling switch and capacitor can steal charge from the hold node, creating a code- and timing-dependent disturbance.
• Cable capacitance and reflections: long lines add capacitance and edge distortion; the buffer sees a harder capacitive load and can ring.
• ESD/clamp leakage and capacitance: leakage increases droop; junction capacitance increases load and reduces stability and settling margin.

Always validate the hold node with the real downstream environment, not a simplified bench load.

For DACs used with sample-and-hold, “good performance” must be expressed as a window contract. Datasheet numbers are only useful when they are tied to the same step size, load, and timing window used by the system. The goal is to map system KPIs back to specific parameters, identify side effects, and close the loop with verification tests.

Must-check datasheet fields (only what impacts the hold window)

Read the conditions. A “great” settling number measured with a small step, light load, or relaxed error band may not satisfy the real window.

Map system KPIs back to parameters (requirements → numbers to check)

• Allowed disturbance in the window (mV or LSB): demand limits for glitch impulse, overshoot peak, and hold-step disturbance.
• Window length: require settling-to-band < (hold window start margin) and droop small enough to stay inside the band until the window ends.
• Multi-channel phase error: translate phase tolerance into Δt, then require channel skew + trigger + routing to fit inside the shared valid-region margin.
• Flatness target: convert long-hold accuracy into droop rate and leakage requirements at worst-case temperature and load.

Error budget structure (three buckets that must all fit inside the band)

The budget becomes actionable only when it is filled with measurements under worst-case conditions.

Close the loop: requirements → parameters → side effects → verification

Do not stop at selecting a part number. Every parameter constraint introduces side effects (for example, C_HOLD and R_iso choices can trade settling for stability). The only reliable finish line is verification: worst-case code transitions, worst-case loads, and worst-case corners.

All measurements must reference the same update event and the same valid-region definition. The trigger that causes the DAC update must also trigger the measurement capture. Otherwise, averaging and time uncertainty can hide the exact behaviors that break sample-and-hold windows.

• Trigger: use the update strobe (LDAC/SYNC/FPGA strobe) as the timing origin.
• Load realism: measure with the real downstream network (C_HOLD, R_iso, cable, clamps, ADC sampling).
• Worst-case coverage: run worst code transitions, worst load, and temperature/supply corners.

Glitch measurement: bandwidth, triggering, and impulse vs peak

• Bandwidth requirement: glitch is a fast transient; insufficient bandwidth can under-report peak and distort the shape.
• Triggering: trigger on the update strobe, then capture a tight window around the transition with consistent pre-trigger.
• Impulse concept: peak amplitude alone can be misleading; glitch impulse (equivalent area/energy) often correlates better to disturbance.
• Worst transition: test major carries and large code steps; compare repeatability across many captures.

Droop measurement: hold-window sampling and isolating slow drift

• Measure inside hold only: exclude update and settling; sample only within the defined hold window.
• Use slope, not endpoints: sample multiple time points in hold and fit a slope to estimate droop rate.
• Separate droop from thermal drift: run a short droop test (window-scale) separately from long-term drift tests (minutes/hours).
• Corner validation: repeat at worst-case temperature and with real clamp/cable/ADC loading that changes leakage and bias.

Settling measurement: small vs large steps and “enter-and-stay” criteria

• Two step sizes: measure a representative small step and a worst-case large step (major carry / full-scale fraction).
• Band definition: define 0.5 LSB or 1 LSB relative to the final value; use the same rule across all tests.
• Enter and stay: settling time is when the output enters the band and remains inside it (no re-exit due to ringing).
• Real load: repeat with the full output network (C_HOLD, R_iso, buffer, cable, clamps, ADC sampling).

Phase alignment measurement: step timing and lightweight correlation

• Method 1 (synchronous step): update all channels at once and extract Δt from a consistent feature (hold boundary or band-entry time).
• Method 2 (correlation): drive the same known waveform on multiple channels, compute time offset Δt, then convert to phase error at the relevant frequency.
• Define the alignment point: when ringing differs across channels, align on hold boundary or band entry rather than on a single threshold crossing.

Minimum reproducible test set (baseline bring-up)

• Glitch: worst code transition, consistent trigger, high-bandwidth capture, peak + impulse-style comparison.
• Settling: small + large step, 0.5/1 LSB band, enter-and-stay rule, real load.
• Droop: hold-window sampling, slope extraction, temperature corner.
• Alignment: multi-channel synchronous step to extract Δt, repeat across temperature and layout corners.

This checklist turns the sample-and-hold discussion into a build sequence. Each group is a set of actions that must be completed before moving to the next stage.

Timing (window contract)

• Define update event, hold boundary, and valid region start/end.
• Record required settling-to-band margin before the sample point.
• Set a minimum time between updates that preserves the valid region under worst-case steps.

Circuit (C_HOLD, R_iso, buffer stability)

• Choose C_HOLD to meet allowed hold-step + droop, then re-check settling-to-band.
• Introduce R_iso (or small RC) to isolate capacitive load; re-validate overshoot and settling for worst steps.
• Confirm buffer stability with the full downstream model: cable, clamps, and ADC sampling kickback.

Synchronization & layout (skew and return-path control)

• Build a symmetric trigger distribution and measure channel-to-channel Δt on hardware.
• Keep hold-node routing short with continuous return paths; avoid crossing splits and noisy reference changes.
• Separate digital switching currents from the hold node; verify with near-field probing or quiet/active mode comparisons.

Bring-up & verify (minimum test matrix)

• Measure glitch for worst transitions with consistent trigger and sufficient bandwidth.
• Measure settling (small + large step) using enter-and-stay band criteria (0.5/1 LSB).
• Measure droop using hold-window sampling and slope extraction; isolate thermal drift.
• Measure alignment via multi-channel synchronous step (Δt), then repeat under corner conditions.

These application patterns are included only when the system depends on hold-window behavior. Each pattern is defined by a window contract: update transients must stay outside the sample window, and the held output must remain inside the error band.

Phase-aligned multi-channel control (synchronous injection / bias / multi-phase control)

• Why S/H is required: if effective hold boundaries differ between channels, the control vector “tears” within a cycle.
• Window contract: per-channel settling-to-band must finish before the shared sample point; channel-to-channel Δt must fit inside the shared margin.
• Verification: multi-channel synchronous step, extract Δt at a consistent feature (hold boundary or band-entry time).

Gated output / sample-window synchronization (hold only when the system observes)

• Why S/H is required: updates must not occur during observation; output must be stable only inside a defined window.
• Window contract: update transient (glitch/overshoot) must be fully outside the sample window; hold flatness must stay inside the band for the full window.
• Verification: strobe-aligned captures that mark “update window” vs “sample window,” then check band compliance only inside the sample window.

Scan / point-by-point update systems (stable output during measurement dwell)

• Why S/H is required: the measurement dwell must see a constant output; update and settling must not consume the dwell time.
• Window contract: (update + settling) must fit inside the “dead time” between points; droop across dwell must stay inside the band.
• Verification: point cadence test: update → settle → hold → sample, repeated across worst load and temperature.

Disturbance-free updates for sensitive nodes (precision bias / fragile analog thresholds)

• Why S/H is required: even brief transients can trip thresholds, inject charge, or corrupt a sensitive analog operating point.
• Window contract: specify allowable transient peak/area in the sample window; enforce enter-and-stay settling before observation.
• Verification: worst code steps + real clamps/cable + band compliance inside the defined observation window.

Example part-number shortlist (verify window and load conditions in the latest datasheets)

These are example part numbers only. Selection must be driven by the hold window (glitch/settling/droop/Δt) and the real load model.

Selection must be driven by the hold window. Datasheet numbers are only comparable when test conditions match the same update event, the same load model, and the same “valid region” definition.

A) Selection fields (grouped cards; no side-by-side layout)

B) Risk mapping (field → failure mode → acceptance)

C) Inquiry template (questions for vendor/FAE)

Position rule respected: IC selection logic appears before this FAQ, and this FAQ contains no images.