ECG Lead Chain: Ultra-Low-Noise AFE, RLD & Lead-Off Detection
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An ECG lead chain is successful when it delivers a diagnostic waveform even with large common-mode mains pickup, big DC electrode offsets, motion artifacts, and transient overloads. The practical path is controlling the interference paths (CM→DM), stabilizing the RLD loop, making lead-off reliable, and budgeting noise/drift so the system stays usable across real cables, patients, and temperature corners.
H2-1 · What this page answers (center answer + reader goals)
Core answer:
The ECG lead chain is the ultra-high-impedance, ultra-low-noise differential path from electrodes to the ADC,
designed to keep diagnostic ECG stable under large common-mode pickup, DC electrode offsets, strong 50/60 Hz interference,
and transient overloads.
What this page delivers:
architecture decisions, RLD + lead-off coexistence rules, a “where mains enters” path breakdown,
plus measurable criteria for noise, drift and overdrive recovery.
Reader goals (practical outcomes)
- Identify whether 50/60 Hz problems come from common-mode pickup or CM→DM conversion (impedance imbalance / asymmetry).
- Choose AFE/INA/PGA/ADC partitioning that prioritizes no overload and fast recovery before chasing marginal noise wins.
- Design a stable RLD loop and reliable lead-off detection without injecting visible artifacts into the ECG band.
- Verify performance with clear, repeatable tests: noise floor, drift with temperature, residual mains, and recovery time after transients.
Engineering criteria (what “good” looks like)
- Mains robustness: residual 50/60 Hz remains low even with electrode impedance imbalance and realistic cable coupling.
- Stability: RLD does not oscillate across patient/cable models; output is limited and fails safe.
- Waveform integrity: filtering removes interference without flattening clinically relevant morphology.
- Recovery: after overload, the front end returns to usable baseline quickly and flags “invalid window” when needed.
Scope note: only lead-chain essentials are covered (electrodes → protection → AFE/ADC interface). Isolation, logging, comms and system EMC are not expanded here.
Figure F0 — Coverage map of the ECG lead chain. Main path is highlighted; side mechanisms show where RLD, lead-off and mains coupling interact.
H2-2 · Where the ECG lead chain sits (system boundary + interface constraints)
The ECG lead chain occupies the patient-side measurement boundary: it starts at electrodes and ends at the minimum ADC interface needed
for waveform processing. Downstream isolation, logging, networking and platform subsystems are intentionally not expanded here.
Constraint 1 — Patient connection safety (lead-chain level)
- Why it exists: electrodes connect directly to the patient, so any drive/injection (RLD, lead-off) must be limited and fault-tolerant.
- What it controls: protection placement, leakage paths, bias current impact, and how quickly the chain returns to a usable baseline after stress.
- How to prove it: test with worst-case electrode impedance and cable coupling; confirm stable RLD behavior and low false lead-off alarms.
Constraint 2 — ADC interface requirements (ECG-specific)
- Why it exists: ECG diagnostic morphology must remain intact while interference is removed; sampling and filtering must be explainable and testable.
- What it controls: anti-aliasing strategy, notch enable/disable behavior, and lead-off injection frequency planning to avoid visible artifacts.
- How to prove it: apply known waveform + mains coupling + impedance imbalance; verify residual mains and distortion remain within acceptance.
Constraint 3 — Transient overload coupling (fast recovery matters)
- Why it exists: real systems see bursts and overloads; long saturation is more harmful than the event itself because it creates unusable gaps.
- What it controls: clamp/RC time constants, AFE overload behavior, and the need for a clear “invalid window” flag during recovery.
- How to prove it: apply controlled overload; measure recovery time to baseline and confirm lead-off and mains rejection do not misbehave during recovery.
Only the required interfaces are pulled across the boundary
ADC data
Lead-off flag
RLD enable / status
Overload / recovery flag
Self-test / diagnostic bits
Anything beyond these signals (isolation architecture, logging pipelines, networking stacks) is intentionally left to other focused pages.
Figure F1 — System boundary for the ECG lead chain. The highlighted block defines in-scope content; grey blocks indicate out-of-scope platform areas.
H2-3 · Signal reality: electrode-skin interface & DC offsets
ECG waveforms are small, but the input environment is not. The electrode-skin interface introduces large DC offsets,
a high and time-varying source impedance, and motion artifacts. The front end must tolerate big common-mode swing and
differential offsets while keeping a stable diagnostic waveform.
Reality A — Large DC offset (electrode half-cell potential)
- What it causes: the input can be driven toward saturation long before the ECG waveform is amplified.
- What it demands: sufficient input range (CM and DM), controlled baseline management, and predictable overload recovery.
- Design warning: aggressive high-pass filtering can distort clinically relevant low-frequency morphology.
Reality B — High, drifting electrode impedance
- What it causes: input bias and leakage currents turn into baseline error and slow drift.
- What it demands: ultra-high input impedance, low bias/leakage paths, and symmetry to reduce CM→DM conversion.
- Failure symptom: mains rejection degrades sharply when electrode impedances are imbalanced.
Reality C — Motion artifact (time-varying interface)
- What it causes: low-frequency baseline wander and sudden steps that can look like electrical faults.
- What it demands: a recovery strategy that preserves waveform integrity and makes “invalid window” observable when needed.
- Practical check: performance must be verified across posture, cable routing, and contact quality.
Engineering magnitude guide (order-of-magnitude)
Useful ECG (DM): mV-level
Electrode DC offset: much larger than ECG
50/60 Hz pickup (CM): can reach V-level
Electrode impedance: kΩ → 100 kΩ (variable)
Design implication: protect headroom and recovery first, then optimize noise and filtering.
Figure F2 — Equivalent electrode-skin model showing DC offsets, interface impedance (R||C), mains coupling, and CM→DM conversion.
H2-4 · Front-end architecture (Diff AFE / INA / PGA / ADC)
Architecture choices should be driven by the input realities: large DC offset, V-level common-mode pickup, variable electrode impedance,
and overload events. A robust chain protects headroom and recovery first, then optimizes noise and filtering.
Typical chain 1 — INA / Instrumentation amp + PGA + ADC
- Strength: clear partitioning and tunable gain/bandwidth for predictable noise budgeting.
- Risk: DC offset and CM swing can drive stages into overload if range and protection are not planned.
- Use when: recovery behavior and performance corners must be engineered and verified explicitly.
Typical chain 2 — Charge/current-input front end (concept only)
- Why it matters: some implementations shift design focus to interface bias paths and input impedance shaping.
- Scope note: only the concept is referenced here to frame bias/leakage priorities for high-impedance electrodes.
Typical chain 3 — Integrated ECG AFE (PGA + ADC + RLD + lead-off)
- Strength: mature internal coordination for RLD and lead-off functions, often with recommended configurations.
- Risk: overload recovery and protection interaction must be validated for worst-case electrode/cable models.
- Use when: repeatability and reduced analog variability are prioritized for production.
Key decisions (write it as “if…then…”)
- If DC offset + mains CM swing approaches the input range, then increase headroom and plan recovery before adding gain.
- If early-stage PGA risks saturation, then distribute gain later while controlling noise contributions via budgeting.
- If lead-off injection can fold into the ECG band (alias/interaction), then reserve a clean injection frequency window and validate with worst-case sampling.
- If electrode impedance is high/variable, then bias current and leakage become dominant error sources—optimize them before chasing extra ADC bits.
- If overload events are expected, then treat “overload recovery time” as a primary KPI, not a footnote.
Minimum spec checklist (what to look at first)
Input range (CM + DM)
CMRR vs frequency
Input bias / leakage
Input-referred noise
Overload recovery time
Protection leakage impact
Lead-off interaction
A chain that looks excellent on noise but fails headroom, recovery, or leakage control will produce unstable ECG in real electrode conditions.
Figure F3 — Internal architecture map: protection → INA/PGA → ADC → digital filters, plus RLD and lead-off paths with key interaction points.
H2-5 · RLD (Right-Leg Drive) loop design
What RLD does: it senses input common-mode (CM) and drives an inverted feedback signal back to the patient,
reducing CM swing. This helps avoid front-end saturation and improves practical mains robustness.
What RLD does not do: it does not “erase” differential mains created by impedance imbalance (CM→DM conversion).
If electrode impedances are mismatched, residual 50/60 Hz can remain even with a strong RLD loop.
Engineering knobs (make the loop predictable)
- CM sense point: sense the true input CM near the AFE inputs; wrong sensing points can slow or misdirect the loop.
- Loop stability: the patient/electrode interface is a drifting R||C load, so phase margin must survive worst-case models.
- Compensation network: use a defined compensation block so the loop does not “hunt” under cable and impedance changes.
- Output limiting: add amplitude limiting and output resistance so overload does not escalate into oscillation or long recovery.
- Fault behavior: current limiting and “RLD degraded” status signaling prevent silent failures and reduce false conclusions during debug.
Interaction notes (where surprises come from)
- Input filtering: RC networks can shift phase and affect the RLD loop; validate stability with the final component values.
- Shielding & imbalance: imbalance converts CM pickup into DM error; RLD reduces CM swing but cannot fully cancel that conversion.
- Lead-off coexistence: lead-off injection and RLD share the same physical electrodes; isolate frequency bands and detection logic.
Debug table: symptom → likely cause → action
| Symptom | Likely cause | Action |
|---|---|---|
| 50/60 Hz suddenly gets worse | RLD loop unstable / saturated / open path | Check RLD output for oscillation or clipping; compare RLD ON vs OFF; confirm electrode return path |
| Slow “breathing-like” baseline drift | Insufficient phase margin with real electrode R||C | Adjust compensation; validate across high-impedance and cable-coupled models |
| One lead is consistently worse | Imbalance causing CM→DM conversion | Inspect electrode contact and symmetry; reduce mismatch; confirm with impedance sweep |
| RLD ON looks worse than OFF | Wrong loop polarity / excessive loop gain | Verify polarity; reduce loop gain; enforce output limiting and output resistance |
| Long recovery after transient overload | RLD clipping + slow return; protection RC too heavy | Tune limiter recovery; reconsider RC time constants; add a clear “invalid window” flag |
| Lead-off alarms increase when RLD enabled | Shared path interaction; impedance imbalance skews detection | Separate injection band; gate detection by RLD state; verify with worst-case imbalance models |
Figure F4 — RLD as a closed-loop system: CM sense, compensated amplifier, output limiting, patient load, and a return path back to the CM node.
H2-6 · Lead-off detection (DC/AC/impedance methods + conflict points)
Core requirement: lead-off must be reliable without polluting ECG. That means the detection signal stays out of the ECG passband,
avoids aliasing, and remains robust against RLD interaction, electrode imbalance, and protection leakage.
Method A — DC injection / DC offset observation
- What it is: inject a small DC current or check DC behavior to infer open/short conditions.
- Main risk: bias currents and leakage paths can mimic “partial disconnect” under high electrode impedance.
- Best use: basic self-check or as a secondary cross-check, not as the only decision path.
Method B — AC micro-injection (impedance measurement)
- What it is: inject a small AC tone and measure response magnitude/phase to estimate electrode impedance.
- Main risk: wrong frequency selection can land in passband or alias into it, creating visible ripple or noise.
- Best use: primary method when paired with a clear frequency window and narrowband detection.
Method C — Indirect inference from bias/protection behavior (use carefully)
- What it is: infer connection quality using changes caused by bias networks and protection components.
- Main risk: temperature, humidity, and clamp leakage can increase false “half-off” indications.
- Best use: supportive signal combined with AC impedance results and robust debounce logic.
Engineering pitfalls (what breaks lead-off in practice)
- Passband intrusion / aliasing: injection frequency must avoid the ECG band and sampling fold-back regions.
- RLD interaction: RLD changes the CM environment; imbalance can skew detection unless paths and logic are isolated.
- Leakage masquerading as “partial off”: clamp leakage and bias currents create apparent impedance changes under high-Z electrodes.
- Debounce trade-off: short debounce increases false alarms; long debounce delays real disconnect detection.
Decision criteria (threshold + debounce + latency)
- Threshold: set thresholds with margin for electrode variability and leakage drift; avoid a single brittle number.
- Debounce: filter transient contact bounce; prefer multi-stage decisions (quick hint + delayed confirm) to reduce false alarms.
- Alarm latency: balance nuisance alarms vs safety; validate with worst-case motion and impedance imbalance.
Figure F5 — Lead-off injection (green) and sensing/detection (purple), highlighting the frequency window, RLD interaction, and leakage-related false indications.
H2-7 · Mains rejection (50/60 Hz): path breakdown + acceptance criteria
Key idea: “50/60 Hz” is not one problem. It appears through (1) common-mode pickup,
(2) common-mode to differential conversion caused by imbalance, and (3) digital-domain artifacts that only look like mains.
A notch filter can reduce visible ripple, but it does not fix the root cause if the path is CM pickup or CM→DM conversion.
Path A — Common-mode pickup (body/cable capacitance)
- How it enters: the patient body and lead wires form capacitive coupling to the environment, lifting both inputs together.
- Why it hurts: large CM swing consumes front-end headroom and increases the chance of saturation under real electrode offsets.
- Most effective knobs: reduce CM swing with RLD (when stable), maintain strong CMRR around 50/60 Hz, and reduce coupling sensitivity with practical cable/shield handling.
Path B — CM→DM conversion (imbalance creates differential mains)
- How it is created: electrode impedance mismatch, input impedance mismatch, or asymmetric protection/filtering converts CM pickup into a differential error.
- Why a notch is not enough: the notch treats the symptom after conversion; the conversion mechanism can still drive overload and degrade recovery.
- Most effective knobs: enforce input symmetry (matching series R/RC/clamp paths), minimize mismatch sources, and verify behavior under intentional impedance imbalance.
Path C — Digital artifacts (sampling, filtering, aliasing)
- How it appears: out-of-band interference folds into the ECG band (aliasing), or filter interactions generate a mains-like pattern.
- Why it is confusing: the waveform can show “mains-looking” ripple even when true environmental pickup is not the dominant path.
- Most effective knobs: control analog bandwidth (anti-alias), validate sampling choices, and apply digital notch/adaptive filtering only with a constraint: do not distort diagnostic morphology.
Mitigation by layers (what each layer actually fixes)
- Hardware: CMRR vs frequency, stable RLD, input symmetry, and cable coupling control — mainly addresses Path A and Path B.
- Analog filtering: anti-alias and bandwidth control — prevents Path C from being created.
- Digital filtering: notch or adaptive methods — reduces residual symptoms after the analog/hardware path is already well-behaved.
Acceptance criteria (repeatable, worst-case oriented)
- Impedance imbalance: validate mains behavior with balanced electrodes and with intentional mismatch (to expose Path B).
- Cable posture sensitivity: repeat measurements across representative cable placements (to expose Path A).
- RLD state comparison: compare RLD OFF vs ON, watching both ripple and headroom/saturation events.
- Digital artifact check: confirm the apparent mains does not come from aliasing by testing with altered sampling/filter settings and checking consistency.
Symptom → most likely path → first action
| Symptom | Likely path | First action |
|---|---|---|
| Ripple changes a lot with cable placement | Path A (CM pickup) | Reduce coupling sensitivity; check RLD stability; review CMRR around mains |
| One lead is always worse than others | Path B (CM→DM conversion) | Check electrode impedance mismatch; enforce input symmetry across protection/RC paths |
| Notch reduces ripple but overload still happens | Path A/B dominant | Fix headroom (CM swing) and conversion sources before relying on digital filtering |
| “Mains-like” pattern changes with sampling/filter settings | Path C (artifact/alias) | Re-check anti-alias and frequency planning; validate folding behavior |
| Lead-off setting changes the “mains” look | Path C or interaction | Verify injection tone stays out of band; confirm detection chain does not leak into ECG |
Figure F6 — Three mains paths: CM pickup (orange), CM→DM conversion under imbalance (red), and digital artifacts (purple).
H2-8 · Input protection & overload recovery (usable signal matters)
Protection is not free: clamps, TVS devices, and RC networks can add leakage, noise, and mismatch.
The practical KPI is not only surviving a transient, but how quickly the front end returns to a usable ECG window
(overload recovery time) without leaving a residual baseline bias.
What harsh events do to the lead chain (impact-focused)
- Node displacement: input nodes are pulled hard; clamps conduct and the AFE may saturate.
- Nonlinear tails: clamp recovery and RC settling can leave a transient “tail” that hides ECG content.
- Usability gap: during recovery, alarms and recordings can be affected unless the chain returns quickly and predictably.
Protection topology knobs (and their hidden costs)
- Series resistors: limit surge current, but add thermal noise and can interact with bandwidth choices.
- Clamps/TVS: protect nodes during overload, but off-state leakage can create baseline error under high electrode impedance.
- RC shaping: softens edges and controls bandwidth; asymmetry between channels can worsen CM→DM conversion.
Overload recovery time (the real usability KPI)
- Definition: time from “event ends” to “ECG returns to a usable window” (no clipping, stable baseline, expected noise floor).
- Why it matters: long recovery creates blind time where the chain is technically alive but clinically unhelpful.
- Design implication: include a defined recovery path and avoid limiter/clamp behavior that sticks or re-triggers.
Engineering criteria (measureable outcomes)
- Recovery time: compare protection options by time-to-usable waveform after overload.
- Residual bias: check whether the baseline returns cleanly or stays offset due to leakage paths.
- Noise increment: quantify the added noise floor from series resistance and protection networks.
- Symmetry check: confirm both channels see matched protection/RC behavior to avoid extra mains conversion.
Debug table: symptom → likely cause → action
| Symptom | Likely cause | Action |
|---|---|---|
| Waveform clips for a long time after an event | Clamp/limiter recovery is slow; AFE saturates and sticks | Improve recovery path; avoid sticky limiting; validate with repeated overload pulses |
| Baseline stays shifted after overload | Off-state leakage or bias path changed by protection components | Review clamp/TVS leakage; ensure symmetry; verify bias currents under high-Z electrode models |
| Mains rejection worsens after adding protection | Protection network asymmetry creates CM→DM conversion | Match series R/RC/clamp paths; confirm layout symmetry and component tolerance effects |
| Noise floor rises noticeably | Series resistance and bandwidth choices increased noise contribution | Rebalance R values and filter placement; verify noise increment vs baseline requirement |
| Lead-off false alarms increase after protection changes | Leakage and RC settling distort injection/sense behavior | Re-check injection frequency window and detection chain; adjust debounce thresholds for leakage drift |
Figure F7 — Symmetrical protection (series R + clamps + RC) and a defined recovery path, highlighting leakage-to-baseline error and recovery time KPI.
H2-9 · Noise & drift budgeting (input-referred, measurable, review-ready)
Key idea: “Ultra-low noise” becomes practical only when the total input-referred noise (IRN)
and baseline drift are turned into a budget that can be allocated to resistors, the INA/AFe, and ADC + reference.
A good budget explains why the waveform looks noisy and which block must improve.
A practical budgeting workflow (no formula dump, fully actionable)
- Define bandwidth and the IRN target: specify the ECG bandwidth used for evaluation (the number must always carry its bandwidth).
- Choose a worst-case source impedance corner: high electrode impedance makes current noise and leakage dominate; budget must be valid there.
- Allocate IRN to buckets: (A) input resistors/filters, (B) INA/AFe noise (en/in), (C) ADC quantization + reference noise, (D) “residual” from injection paths.
- Check gain placement impact: ensure the selected gain does not push any stage into overload or make the ADC/REF bucket dominate.
- Verify injection paths do not modulate noise: compare IRN with lead-off/RLD-related functions enabled/disabled to catch ripple-like modulation.
- Close the loop with measurement: confirm the measured IRN matches the budget within reasonable tolerance under worst-case impedance and temperature.
Noise contributors (what dominates in real high-impedance ECG inputs)
- Electrode/source thermal behavior: rising source impedance increases sensitivity to current noise and leakage-driven errors.
- Input resistor thermal noise: series resistors and filter resistors add noise; “more protection R” is often paid in IRN.
- Amplifier voltage noise (en): sets the floor when source impedance is modest and the input network is quiet.
- Amplifier current noise (in): becomes critical when source impedance is high; it converts directly into input noise.
- Bias/leakage noise and drift: tiny currents through high impedance create baseline errors; temperature usually makes this worse.
- ADC quantization + reference noise: effective resolution is limited by reference quality and front-end scaling, not by bits alone.
Drift chain (temperature → leakage/bias → baseline movement)
- Temperature dependence: leakage paths and bias behavior typically increase with temperature, especially around high-impedance nodes.
- Asymmetry creates visible issues: if A/B paths drift differently, drift becomes differential error and may also worsen mains conversion.
- Control knobs inside the lead chain: periodic self-check using known input states, conservative bias/leakage selection, and baseline-only digital compensation that avoids morphology distortion.
Budget table template (review-ready fields)
| Contributor | Input-referred noise (placeholder) | Bandwidth condition | Worst-case corner / note |
|---|---|---|---|
| Electrode/source | IRN_SRC | BW_Hz | High-Z corner |
| Input R / filter network | IRN_R | BW_Hz | Protection trade-off |
| INA/AFe (en/in) | IRN_AFE | BW_Hz | Source impedance dependent |
| ADC quantization | IRN_Q | BW_Hz | Scaling / gain placement |
| Reference noise | IRN_REF | BW_Hz | Often overlooked limiter |
| Injection residual (if applicable) | IRN_INJ | BW_Hz | Enable/disable comparison |
Figure F8 — Budget funnel: contributors → total input-referred noise (IRN_TOTAL) over a stated bandwidth (BW_Hz), plus drift emphasis.
H2-10 · Layout, cabling & motion artifacts (engineer the “mystery” away)
Key idea: ECG inputs are high-impedance, so tiny leakage and tiny coupling capacitance
become visible waveform issues. The reliable approach is to control leakage and symmetry in the PCB input zone, and to treat the cable as a coupling element.
Motion artifacts are handled by a careful HPF time constant choice plus baseline restoration that preserves waveform fidelity.
High-impedance input layout (checklist + failure modes)
- Guard ring / driven guard: prevent surface leakage from turning into baseline drift under humidity and contamination.
- Input symmetry: keep A/B routing and component paths matched (protection, RC, leakage paths) to avoid CM→DM conversion.
- Minimize high-Z area: shorten high-impedance traces and reduce exposed surface area to lower coupling and leakage sensitivity.
- Leakage control zone: keep-out, cleaning, and moisture-aware spacing around the input to stop “drift that depends on the day.”
Cabling and coupling (treat the cable as a circuit element)
- CM pickup source: the cable and body capacitively couple to the environment; posture changes can change the CM swing.
- Shield boundary: shielding can reduce pickup, but asymmetry or poor reference behavior can still convert CM into DM.
- Acceptance must include posture: validate noise and mains behavior across realistic cable placements and “touch” conditions.
Motion artifacts and baseline wander (stability vs fidelity)
- Analog HPF time constant: too aggressive removes low-frequency content; too slow leaves long baseline tails that hide details.
- Digital baseline restoration: remove baseline components only; avoid “over-cleaning” that reshapes clinically important morphology.
- Practical guidance: tune with controlled motion/impedance changes and verify the filter does not introduce oscillatory settling.
Field symptoms → likely mechanism → first checks
| Symptom | Likely mechanism | First checks |
|---|---|---|
| Baseline drifts strongly while walking | Electrode impedance changes + motion artifact | Review HPF time constant and baseline restoration; validate under controlled motion |
| One lead is much more sensitive than others | Asymmetry or localized leakage path | Check guard/symmetry; inspect contamination/humidity sensitivity around high-Z nodes |
| Touching chassis increases mains ripple | CM coupling and reference movement | Re-check cable coupling path; verify symmetry and CM control behavior under touch/posture changes |
| Humidity makes drift noticeably worse | Surface leakage increases with moisture | Strengthen leakage control zone (cleaning/spacing/guard); re-test baseline drift vs temperature |
| Lead-off enable changes noise appearance | Injection tone coupling or folding | Validate injection frequency window; compare IRN and spectrum with injection OFF/ON |
| Swapping the cable changes performance a lot | Different coupling capacitance and shielding effectiveness | Treat cable as part of acceptance; verify posture sensitivity and leakage/symmetry stability |
Figure F9 — PCB high-impedance zone (guard + symmetry + leakage control) and cable CM pickup (Ccouple + touch/posture sensitivity).
H2-11 · Validation & production test checklist (prove it with data)
Key idea: A lead chain is “good” only if it stays stable and diagnostic under worst-case impedance, mains coupling,
and overload events. This section provides a bench + production checklist with repeatable stimuli, measurable metrics,
and clear pass/fail gates.
Validation matrix (overview)
| Test | Stimulus / corner | Metric | Gate (PASS/FAIL) |
|---|---|---|---|
| CMRR vs frequency | In-phase injection sweep; include mains region | CMRR(f) in dB | Meets target across defined band |
| Mains residual under imbalance | 50/60 Hz with A/B impedance imbalance + cable posture | Residual mains amplitude / spectrum | Residual within limit; no overload |
| Lead-off accuracy | Open / high-Z / normal states via fixture matrix | TP/FP/FN, latency, debounce | Error rates within spec window |
| RLD loop stability | Body/cable RC corners; posture/touch equivalent | Oscillation, settling time | No oscillation; bounded response |
| Overload recovery | Controlled input overload pulse / step | Recovery time + residual offset | Recovers within time; offset within limit |
| IRN + drift vs temperature | Low/room/high temperature points; high-Z corner | IRN (band-limited), drift rate | Matches budget; stable across temp |
Bench validation checklist (repeatable setup → stimulus → metrics → gate)
1) CMRR(f) and mains residual under impedance imbalance
- Setup: in-phase injection to both inputs through large, matched resistors; add switchable A/B impedance imbalance network (R or R||C).
- Stimulus: frequency sweep (include the mains region) and posture-equivalent coupling changes (switchable Ccouple).
- Metrics: CMRR(f) in dB; residual mains component amplitude/spectrum under balanced and unbalanced conditions.
- Gate: meets CMRR target across band; residual mains stays within limit without pushing the front end into overload.
2) Lead-off detection accuracy (open / high-Z / normal)
- Setup: fixture matrix selects three truth states: open, high impedance, normal; include realistic RC edges for “half-off” behavior.
- Stimulus: scripted state transitions; verify the injection tone/frequency window does not fold into the visible ECG band.
- Metrics: TP/FP/FN rates, detection latency, debounce window effects (false alarms vs missed detection).
- Gate: mis-detect rates and latency are within defined limits across worst-case impedance corners.
3) RLD loop stability across cable/body corners
- Setup: body + electrode model with switchable R/C corners; add posture/touch equivalent coupling capacitance changes.
- Stimulus: step changes in coupling (Ccouple) and impedance; enable/disable RLD to compare behavior.
- Metrics: oscillation presence, oscillation frequency/amplitude, step response settling time, bounded output drive.
- Gate: no sustained oscillation under worst-case corners; response remains well-damped and repeatable.
4) Overload recovery and residual offset (controlled overload)
- Setup: controlled overload pulse/step injection at the input; log front-end output and baseline recovery behavior.
- Stimulus: repeatable overload shapes; include multiple protection configurations if selectable.
- Metrics: recovery time to “usable waveform window”; residual offset after a defined settling time.
- Gate: recovery time and residual offset remain within the defined limits; no repeated clamp-trigger tail.
5) IRN and drift vs temperature (budget reality check)
- Setup: low/room/high temperature points; test both shorted-input and high-impedance corners.
- Stimulus: steady-state capture per temperature point; include repeat runs to check stability.
- Metrics: band-limited input-referred noise (IRN) and baseline drift rate; note lead-to-lead asymmetry if present.
- Gate: IRN tracks the budget; drift stays bounded across temperature; asymmetry flags leakage/contamination risks.
Example part numbers for a practical test fixture (non-exhaustive)
- Switch / matrix (state selection, impedance corners): TI TMUX1308, TI TS5A3159, ADI ADG704, ADI ADG884
- Precision resistors (imbalance + injection networks): Vishay TNPW0603 series, Susumu RG series (thin-film, low drift)
- C0G/NP0 capacitors (RC body/cable models): Murata GRM1885C1H series (C0G/NP0 family)
- RLD driver / buffer op-amps (examples): TI OPA333, TI OPA320, TI OPA376, ADI ADA4528
- Integrated ECG AFEs often used for reference designs: TI ADS1292R / ADS1294 / ADS1298, ADI ADAS1000, ADI AD8233, Maxim MAX30001
- Low-leakage / protection examples (evaluate leakage vs temperature): Nexperia BAV199, TI TPD1E10B06
Note: These are example building blocks for fixtures and comparisons. Final selection should be validated against leakage, noise, and temperature behavior in the target lead chain.
Production test strategy (fast “proxy metrics” to screen outliers)
- Noise floor proxy: short input (or switch to a known quiet state) and measure RMS + key spectral bins. This quickly flags reference noise, contamination, and assembly issues.
- Offset/leakage proxy: measure baseline under a known impedance state; repeat after a short warm-up. Drift beyond a limit indicates leakage or asymmetry.
- Lead-off response proxy: toggle open/normal states through the matrix; verify detection latency and debounce behavior without excessive false alarms.
- Stability sanity check: apply a small coupling step (switchable Ccouple) and verify no oscillation signature appears on the output.
Print-ready checklist (project review / factory use)
☐ Fixture verified: switch matrix + impedance corners + Ccouple steps + logging
☐ CMRR(f) sweep executed (includes mains region); data logged with bandwidth condition
☐ Mains residual tested under balanced + unbalanced impedance; multiple cable postures
☐ Lead-off truth table validated (open / high-Z / normal): TP/FP/FN + latency + debounce
☐ RLD stability checked across body/cable RC corners; no oscillation; bounded settling
☐ Controlled overload test executed: recovery time + residual offset recorded
☐ IRN measured (band-limited) at low/room/high temperature points; matches budget
☐ Drift rate measured vs temperature; lead-to-lead asymmetry reviewed
☐ Production proxy metrics validated: noise floor + offset/leakage + lead-off response
☐ Pass/Fail gates applied; results stored with Log ID / serial traceability
Figure F10 — Validation workflow: controlled setup, stimulus set (mains / lead-off / overload), metrics extraction, pass/fail gating, and traceable logs.
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H2-12 · FAQs × 12 (ECG Lead Chain)
These FAQs target practical lead-chain decisions: mains paths, RLD stability, lead-off accuracy, overload recovery, noise/drift budgeting, and layout/cable coupling.
