High-Impedance FET-Input Op Amp for pA-Level High-Z Sensors
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High-impedance buffering succeeds when system leakage and charge injection are controlled—not just when the op-amp datasheet shows “pA bias”. This page explains how to turn high-Z sources into stable measurements with guarding, a defined return path, humidity-aware layout/cleanliness, and verification tests that quantify drift and recovery.
What this page solves: when “high-Z” becomes the dominant error source
In 100 MΩ–GΩ sensor chains, accuracy is usually limited by pA-level currents and leakage paths (PCB surface, connectors, protection structures, humidity), not by “op-amp gain” or generic bandwidth. The most reliable workflow is to start from a current/leakage budget, then build guarding, cleanliness, and verification hooks around the input node.
- pH / ISE glass electrodes and other ultra-high-impedance probes
- Electrochemical sensing nodes where the measurement input is high-Z (measurement side only)
- GΩ divider / insulation monitoring / charge-sensitive or electrostatic front ends
- Photodiode voltage-mode buffering (not full transimpedance design)
- How pA × RSOURCE becomes mV-level offset and why humidity often dominates the budget
- How to separate device bias current from system leakage (PCB/connector/cable/protection)
- Practical guarding patterns (driven guard, keepouts, slots) and cleanliness workflows that scale to production
- High-Z stability pitfalls: input capacitance, cable capacitance, slow recovery, “touch” effects
- Verification hooks: leakage baseline, humidity sweep, overload recovery and cable sensitivity tests
- Full transimpedance amplifier (TIA) compensation and photodiode/PMT front-end deep dives
- Complete three-electrode electrochem control loops and system-level AFE architectures
- Chopper/zero-drift internal mechanism details (only high-Z impact is referenced here)
- EMI/ESD certification-style immunity design rules beyond leakage-aware protection basics
- ADC driver / FDA common-mode matching and anti-alias filter design details
The real error terms in high-Z chains
High-impedance accuracy should be treated as a current problem. The input node is sensitive to tiny currents and stored charge: even “invisible” leakage through contamination films or protection structures can exceed the op-amp’s datasheet bias current.
- Input bias current (IB) vs temperature and common-mode: drives DC offset via IB·RSOURCE
- Input capacitance (CIN) and input charge behavior: affects settling, “touch” response, and stability
- Offset / drift / 1/f noise: matters at low frequencies, but may be secondary to leakage
- Overload recovery: determines how quickly readings return after input over-range or ESD events
- PCB surface leakage (flux residue, ionic contamination, moisture film)
- Connector and cable insulation leakage (humidity-dependent and handling-dependent)
- Protection structure leakage (ESD diodes/TVS/OVP clamps may leak at the same scale as IB)
- Adsorbed charge & dielectric absorption (slow recovery after touch, motion, or over-range)
IB (max over temp), input leakage of protection structures, CIN and charge behavior, offset/drift & 1/f noise, overload recovery, humidity sensitivity, and package/cleanliness manufacturability.
Definition & taxonomy: FET-input vs CMOS-input vs JFET vs electrometer-grade
“FET-input” is a useful label, but it does not guarantee pA-level system performance by itself. The measured bias/leakage is a combination of the input device, protection structures, packaging, and the surrounding PCB/connector environment. This section defines the common categories and explains what they tend to change in practice: IB, CIN, overload recovery, and sensitivity to leakage.
Where the pA comes from (a practical source map)
The current seen by a high-Z sensor node can be dominated by non-obvious paths. A correct taxonomy is less about the marketing label and more about identifying which leakage contributors are likely to be significant and how they behave over temperature and humidity.
- Input device leakage (gate/junction leakage): sets a baseline for intrinsic IB
- Protection network leakage (ESD/OVP/inversion): can be comparable to intrinsic IB and may vary strongly with temperature
- Input bias/support circuitry (startup/trim paths): may show transient charge effects and long recovery tails
- Package surface leakage (mold compound, leadframe spacing): rises with moisture and contamination
- Board/connector/cable leakage: often the dominant term in real environments
Chopper/zero-drift amplifiers may introduce input charge artifacts that are more visible in high-Z nodes. This page only explains the high-Z impact and how to recognize it; internal chopper theory and mitigation techniques belong to the dedicated zero-drift page.
What tends to differ across categories (engineering consequences)
- Often a strong choice for high-Z buffering when low bias current is needed without aggressive charge behavior.
- Real-world limit can still be protection leakage or surface leakage rather than the JFET itself.
- Practical focus: confirm IB distribution over temperature and validate recovery after input over-range.
- Can achieve very low bias current, but high-Z nodes may become more sensitive to CIN, charge injection, and long cables.
- Handling symptoms can include touch-induced steps, long settling tails, or stability changes with cable length.
- Practical focus: characterize cable capacitance sensitivity and verify stability/settling under worst-case input conditions.
- Emphasizes total leakage control (package behavior, input protection strategy, and testability) rather than a single “IB typical” number.
- Targets making real-world performance closer to datasheet values across humidity and temperature.
- Practical focus: validate leakage under environmental stress (RH/temperature) and ensure production cleaning/inspection workflows are compatible.
Error model: convert pA into volts—IB × RSOURCE, leakage × humidity, and CIN dynamics
High-impedance accuracy is best treated as a current-to-voltage conversion problem at the input node. The dominant term is often not “op-amp gain” but the total input-node current (intrinsic bias + leakage + injected charge) flowing through an effective source resistance.
- DC error: VERROR ≈ (IB + ILEAK,total) · RSOURCE,eq
- Dynamic step: ΔV ≈ QINJECTED / CTOTAL
- Slow settling: τ ≈ RSOURCE,eq · CTOTAL (long cables and high input capacitance increase τ)
- 1 pA × 10 MΩ = 10 µV
- 1 pA × 100 MΩ = 100 µV (0.1 mV)
- 1 pA × 1 GΩ = 1 mV
- 10 pA × 1 GΩ = 10 mV (a small leakage increase becomes a large offset)
- Humidity / handling sensitive drift: surface / connector / cable leakage is likely dominating.
- Mostly temperature driven drift: intrinsic IB or protection-structure leakage may dominate.
- Step + long tail recovery: Q/C effects, dielectric absorption, or slow discharge paths are likely.
- Gets worse with longer cables: CSTRAY rises, increasing charge sensitivity and settling time.
Input leakage in the real world: PCB surface, connectors, cables, and packaging
Datasheets often describe intrinsic input bias current under controlled conditions. In high-impedance systems, the measured offset and drift are frequently dominated by external leakage paths: PCB surface films, connector and cable insulation, fixture leakage, and protection structures whose leakage rises with temperature and humidity.
- PCB surface: flux residue, ionic contamination, solder mask edges, fiberglass exposure, via-in-pad and crowded pin fields
- Connectors & fixtures: contamination films, condensation, handling residues, insulation tracking
- Cables: insulation leakage and triboelectric/handling effects that change with humidity
- Protection structures: ESD/TVS/OVP clamps may leak at the same order as intrinsic IB
- Moisture films can form a continuous conductive path once a humidity threshold is crossed.
- Ionic residue increases surface conductivity dramatically when moisture is present.
- Temperature often increases leakage in protection structures and accelerates moisture-driven conduction.
- Packages with tighter spacing and harder-to-clean regions can trap residue near sensitive nodes.
- Exposed pads and under-body areas can increase cleaning difficulty and leakage repeatability risk.
- For high-Z designs, consistent cleaning and inspection often matter as much as the intrinsic IB spec.
This section focuses on leakage mechanisms and layout/manufacturing implications. Detailed bias-return and protection circuit strategies belong to the dedicated biasing & protection section; full photodiode/TIA compensation belongs to the TIA/photodiode front-end pages.
Guarding & layout for pA: driven guard rings, slots, standoffs, and cleanliness workflow
In pA-level designs, the most effective improvement rarely comes from changing the op amp. The repeatable win is to reduce the voltage difference across leakage paths and to prevent surface conduction from forming near the input node. Guarding is a layout-and-process method: guard topology, keepouts, slots, and cleanliness must be designed together.
A leakage path behaves like a large resistance on the PCB surface. The leakage current is driven by the voltage difference across that path. A driven guard brings the surrounding surface close to the sensitive node potential, so the voltage difference is minimized and leakage drops.
- Follow the input node (default): best when the measurement node is the highest-impedance point to protect.
- Follow the output: acceptable when the circuit is a true buffer and output closely tracks input under all conditions.
- Follow a reference: useful when the input node stays near a fixed common-mode point; avoid if the node swings widely.
- Guard ring + keepout: isolate the sensitive node from contaminated surfaces and handling.
- Slots: break surface leakage paths; evaluate mechanical and return-path side effects.
- Standoffs / elevation: reduce moisture film continuity near the node; evaluate assembly repeatability.
- Conformal coating: can help or hurt; treat as a process window that must be validated under humidity.
Cleanliness workflow (principles that scale to production)
- Clean: remove ionic residue and flux films near the input node and connectors.
- Dry: eliminate moisture films; short-term “good” readings can fade if drying is incomplete.
- Check: verify residue/cleanliness with a consistent inspection method and record results.
- Protect: store and handle boards to prevent re-contamination at the high-Z node.
- Guard driven to the wrong net: increases voltage difference and worsens leakage.
- Guard ring breaks: one discontinuity can defeat the entire guard strategy.
- Via “sneak paths”: contaminated vias can provide hidden conduction routes.
- Solder mask openings / silkscreen near the node: absorbs moisture and traps residue.
- Test points near high-Z: handling and probing inject charge and create long settling tails.
- Guard ring is continuous and surrounds the entire high-Z node and trace.
- No vias, test points, or silkscreen inside the keepout region.
- Slots/clearance interrupt surface paths from connectors toward the input node.
- ESD/protection components are placed to avoid creating a leakage bridge into the high-Z region.
- Cleaning and drying steps are defined and repeatable for production builds.
Biasing high-Z sensors safely: DC return paths, common-mode range, and protection without leakage
High-impedance sources still require a DC return path. Without a controlled return path, the input node behaves like a floating capacitor and can drift into saturation. The challenge is that bias networks and protection parts can introduce leakage currents comparable to the target pA-level budget. This section focuses on establishing bias closure while keeping leakage under control.
- Open input drift: readings can wander and eventually rail as charge accumulates on CIN and stray capacitance.
- Handling steps: touch or cable motion injects charge; without a return path, recovery can take a long time.
- Hidden saturation: the input may quietly move outside common-mode range, causing non-obvious measurement errors.
- Ultra-high-value bias resistor: provides DC closure with minimal loading; verify leakage and humidity sensitivity.
- Symmetric biasing: sets a stable common-mode point; ensure the bias network does not create a leakage bridge.
- Guard-aware bias routing: keep bias components and surfaces inside guarded/clean regions when possible.
- Overvoltage, reverse input, and ESD protection are necessary, but protection leakage can match the pA-level target.
- Protection placement and reference choice can create a new leakage path into the high-Z node.
- Overload events can cause long recovery tails; recovery time must be tested as part of verification.
This section focuses on leakage-aware bias closure and practical protection principles. Certification-grade EMI/ESD routing and surge/EFT immunity details belong to the dedicated EMI-hardened page.
Noise in high-Z systems: en vs in, 1/f, source-Z shaping, and chopper tradeoffs
In very high source impedance measurements, “pA-level input bias” is necessary but not sufficient. Noise is often dominated by input current noise converted into voltage noise by the source impedance: in · RSOURCE. Low-frequency applications (pH, electrochemistry) are also strongly affected by 1/f noise.
- Voltage noise (en) matters, but it does not scale with RSOURCE.
- Current noise (in) becomes voltage noise through the source impedance: VN ≈ in · RSOURCE.
- As RSOURCE increases, in · RSOURCEn looks excellent.
- Lower RSOURCE / wider bandwidth: en and wideband integration often dominate.
- Higher RSOURCE / low-frequency readout: in and 1/f terms often dominate stability.
- Long cables / large C: effective source impedance becomes frequency-shaped; validate noise over the real measurement bandwidth.
- Benefit: significantly lower 1/f and drift can improve low-frequency stability.
- Risk: input charge injection and ripple artifacts can be more visible at very high impedance.
- Practical rule: if low-frequency drift dominates, chopper can help; if the node is highly capacitive and sensitive to injection, verify for ripple and step-like artifacts.
Stability with high impedance & capacitive sources: CIN, cable C, and how to avoid oscillation
High-impedance sources frequently come with large capacitance from electrodes, probes, and cables. That capacitance can reduce phase margin and raise noise gain, producing ringing, slow recovery, or oscillation even in “DC” measurement chains. The goal is to control the input-node impedance and validate stability with simple bench tests.
- Cable capacitance: longer cables raise C and make the node more injection-sensitive.
- Electrode / probe capacitance: sensors and fixtures often look like R plus large C.
- Input and protection capacitance: CIN and protection junction capacitance add directly at the node.
- PCB stray capacitance: large copper areas near the node increase C and coupling.
- Riso at the input node: isolates cable/electrode C; place it close to the op-amp input.
- Input RC shaping: limits high-frequency gain and reduces ringing; validate settling time impact.
- Bandwidth limiting: reduces noise gain peaking; check for measurement latency and recovery.
- Leakage awareness: any added components must be placed and cleaned to avoid creating leakage bridges.
- Apply a small step or square-wave stimulus and observe overshoot and ringing on the output.
- A/B test: change cable length, add/remove Riso, and add/remove protection parts to see sensitivity trends.
- Record recovery time after overload or handling events; long tails indicate charge and weak discharge paths.
This section targets stability problems caused by input/cable capacitance in high-impedance measurement chains. Full loop-gain derivations and general compensation theory belong to the stability/compensation overview and high-speed op-amp pages.
Typical circuits & application patterns: pH, electrochem probes, and photodiode voltage-mode buffering
High-impedance applications share a common requirement: a stable buffer stage with controlled leakage, a defined return path, and predictable recovery after handling or overload. The patterns below focus on minimum viable high-Z chains. Photodiode coverage is limited to voltage-mode (photovoltaic) buffering; full transimpedance (TIA) design and compensation belong to the dedicated photodiode front-end page.
- Minimum chain: Glass electrode → High-Z buffer → Low-pass → ADC.
- Dominant errors: leakage and handling charge often exceed headline bias specs in the real build.
- Layout musts: driven guard + keepout + clean zone around the connector and input node.
- Verification: humidity A/B, cable-move step response, and overload recovery time.
- Minimum chain: Probe node → Buffer + defined bias point → ADC/measurement.
- Dominant errors: weak return path leads to drift; added bias/protection can add leakage.
- Layout musts: keep bias network inside guarded/clean regions where possible.
- Verification: bias-point sensitivity checks and recovery tail measurement after injection events.
- Minimum chain: Photodiode (voltage mode) → High-Z buffer → Filter/ADC.
- Dominant errors: input leakage, CIN and cable C shape settling and injection sensitivity.
- Boundary: transimpedance gain and stability compensation are covered in the photodiode front-end page.
- Verification: slow illumination steps, cable-length sensitivity, and long-tail recovery after overload.
IC selection logic: map specs to risks and tests (no part numbers)
High-impedance designs fail when “typical” datasheet numbers are treated as guarantees. Selection should be run as a closed loop: spec fields → failure risks → verification tests. This section lists what to request from vendors and how to translate each spec into a measurable risk.
- Input bias current vs temperature: max over temperature, and distribution/guardband if available.
- Input protection leakage: leakage vs temperature and input voltage (if protection exists).
- Input capacitance and CM dependence: CIN vs common-mode and input voltage.
- Overload recovery: time to recover after saturation and ESD-like events.
- Noise: 0.1–10 Hz noise, wideband noise, and input current noise in.
- Offset/drift: treat as secondary when leakage dominates in the real build.
- Package and process compatibility: cleaning, moisture sensitivity, and handling constraints.
| Spec field | Failure mode | Minimum test |
|---|---|---|
| IB max vs temp | DC error and drift that scales with RSOURCE | temperature sweep with a known high-R source |
| Protection leakage | humidity-sensitive offsets and “mystery bias” | humidity A/B, add/remove protection parts |
| CIN vs CM | ringing, step sensitivity, slow settling | step response vs cable length and C add-on |
| Overload recovery | long recovery tails after saturation/handling | rail-to-linear recovery timing under repeatable events |
| in, 0.1–10 Hz | low-frequency instability and poor averaging | low-frequency window measurement and long-run logging |
| Package/process notes | lot variation and moisture-driven field drift | process audit: cleaning, storage, and handling verification |
- Humidity sensitivity: dry vs high humidity, record offset drift and recovery.
- Handling injection: cable movement or probe touch, record step size and tail time.
- Overload recovery: controlled saturation event, time-to-linear and repeatability.
- Capacitance sensitivity: vary cable length / add small C, check ringing and settling.
- Low-frequency noise window: log long runs to capture 1/f-like behavior and drift.
- Provide maximum input bias current over temperature, and distribution/guardband information if available.
- Provide input protection leakage vs temperature and input voltage (if any protection structures are present).
- Provide input capacitance vs common-mode and input voltage, including typical and worst-case conditions.
- Provide overload recovery time after saturation and ESD-like events, with test conditions.
- Provide 0.1–10 Hz noise, wideband noise, and input current noise in with measurement conditions.
- Provide package and process notes related to cleaning, moisture sensitivity, and handling limitations.
Engineering checklist: bring-up, validation tests, and production controls for pA-level designs
pA-level performance is a system outcome: PCB surface leakage, cabling injection, guard integrity, recovery behavior, and process cleanliness can dominate over datasheet “typical” numbers. This checklist turns those risks into repeatable bring-up steps, validation tests, and production controls.
- Cleanliness visual check: no flux residue, fingerprints, white deposits, or contamination near the input node, connector pins, and guard ring.
- Guard continuity check: guard ring/trace is continuous (no breaks, no accidental vias to other nets, no unintended solder mask windows that create water films).
- Guard net correctness: guard is connected to the intended driven node (not tied to a fixed rail or to the high-Z input by mistake).
- Input node geometry: keepout/clean zone exists around the input node and connector; no copper pours or silkscreen close to the node.
- Open input expectation: confirm behavior matches the design’s intended return path (floating nodes should not be treated as “bad” without this context).
- Short-to-reference expectation: when shorted to the reference node, output should settle quickly and drift should reduce sharply.
- Handling injection sanity: gentle cable motion should not create uncontrolled steps with extremely long tails.
- Overload/recovery smoke test: a controlled, repeatable perturbation should recover within the allowed time window for the application.
- Goal: establish a leakage baseline that separates PCB/process effects from the IC’s intrinsic bias/leakage.
- Method: measure under a fixed fixture/cable; compare “as-built”, “after cleaning/drying”, and “after humidity exposure”.
- Pass criteria: baseline should be stable and repeatable; large shifts after humidity indicate surface/connector leakage dominance.
- Record: baseline level, drift slope over time, and any step events with timestamps.
- Goal: quantify humidity-driven drift that can overwhelm pA-level bias.
- Method: step RH across multiple plateaus (low → high → back), keeping cable/fixture unchanged and allowing stabilization at each plateau.
- Pass criteria: drift vs RH should be consistent across repeats; non-repeatable jumps usually point to contamination or charge absorption/release.
- Record: RH, temperature, soak time, drift slope, and recovery behavior when RH returns low.
- Goal: ensure the chain returns to valid accuracy within application limits after a defined disturbance.
- Method: apply a controlled, repeatable event (defined amplitude and duration) and time recovery to a defined error threshold.
- Pass criteria: recovery time and tail behavior are bounded and repeatable across multiple runs.
- Record: event definition, peak excursion, time-to-threshold (Trecover), and run-to-run spread.
- Goal: quantify step magnitude and settling tails caused by cable capacitance changes and charge injection.
- Method: repeat a defined motion/insertion pattern with fixed cable types and lengths (short vs long).
- Pass criteria: step size and tail time remain within bounds and do not worsen dramatically with cable length.
- Record: cable type/length, step peak, settling time to threshold, and any ringing/oscillation signatures.
- Define a consistent cleaning workflow (wash → rinse → dry) and lock the parameters to prevent hidden leakage shifts.
- Control storage after cleaning (sealed dry storage) to prevent moisture uptake before final test.
- Keep high-Z assembly steps (connectors, guarding areas) under stricter handling rules than standard analog boards.
- Audit ionic residue on a sampling plan (per lot, after process changes, after chemistry changes).
- Use audit results to gate release and to trigger re-clean / process adjustment when trends drift.
The items below are practical examples used in pA-level labs and builds. Final selection must follow compatibility and safety requirements of the local process.
- Vishay · CRHP1206AF1G00FKE1 (1 GΩ, 1206)
- Ohmite · HVC1206Z1008KET (10 GΩ, 1206)
- Nexperia · BAV199 (low-leakage dual diode, commonly used as a leakage-conscious clamp option)
- Keithley · 7078-TRX-BNC (Triax to BNC adapter for guarded setups)
- Amphenol RF · 031-30231-37 (Triax connector example; select by mechanical needs)
- Alpha Wire · 2841/1 RD005 (PTFE insulated wire example)
- Essentra · HTSN-M3-10-6-2 (nylon standoff example)
- Techspray · 1631-16S (flux remover example; verify compatibility and follow safety procedures)
- GEN3 · CM series (ionic contamination / cleanliness test system example)
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FAQs: high-impedance FET-input op amps (buffering, leakage, guarding)
These FAQs focus on high-Z buffering with FET-input op amps: leakage paths, guarding, return paths, cable capacitance effects, recovery behavior, and production-ready checks. Topics such as full photodiode TIA compensation, full electrochemical potentiostat loops, and dedicated ADC driver design are intentionally out of scope here.
My input bias current is “pA” on the datasheet—why do I still see mV-level drift?
- Fast checks: compare “before/after cleaning”, run a low-RH vs high-RH A/B test, and short the input to the reference node to see if drift collapses.
- Fixes: enforce a driven guard + clean zone, define a DC return path, and A/B test protection parts for leakage impact.
How can PCB contamination create leakage larger than the op-amp’s bias current?
- Fast checks: microscope/UV inspection, cleaning + drying A/B, and RH step tests to see whether offsets change with moisture.
- Fixes: widen spacing/keepout at the input node, use driven guarding, and lock a cleaning + ionic-residue audit workflow for production.
When should a driven guard follow the input vs follow the output?
- Fast checks: verify guard continuity, confirm the guard is actually driven (not floating), and confirm the guard net is not accidentally tied to a rail or a different reference.
- Fixes: drive the guard from the correct tracking node, avoid breaks/vias that create unguarded bridges, and keep the guard inside a clean, moisture-controlled region.
Why does humidity cause step changes instead of smooth drift?
- Fast checks: RH step tests (low → high → low), look for hysteresis, and repeat runs to separate stable trends from random jumps.
- Fixes: improve cleaning/handling controls, expand input keepout/guard coverage, and validate any coating process with repeatable RH tests.
Do input protection diodes/TVS always ruin high-Z accuracy?
- Fast checks: A/B build with and without the protection parts, sweep temperature and RH, and measure both baseline drift and recovery time after a perturbation.
- Fixes: select lower-leakage protection, place protection where leakage is tolerable, and keep the protected node inside the guarded/clean region.
How do I create a DC return path without loading a GΩ source?
- Fast checks: compare open-input behavior with and without the return path, and confirm that short-to-reference settles quickly and repeatably.
- Fixes: use very high-value bias/return resistors, keep them within the guarded/clean region, and validate drift and recovery under humidity.
Why does touching the cable change the reading for seconds?
- Fast checks: repeat a fixed “cable move” action, compare short vs long cables, and observe step magnitude and settling time.
- Fixes: improve shielding/guarding near the connector, limit bandwidth where acceptable, and add carefully chosen isolation/RC damping that does not introduce new leakage paths.
What’s the quickest way to measure leakage without special instruments?
- Fast checks: measure baseline before/after cleaning, then repeat at higher RH; large deltas strongly indicate surface/connector leakage.
- Fixes: standardize the test script and store baseline metrics for each lot to detect process shifts early.
How does input capacitance affect settling time with a high-Z sensor?
- Fast checks: step response tests with short vs long cables, and incremental added capacitance to find stability/settling boundaries.
- Fixes: reduce effective capacitance where possible, add controlled isolation/RC damping, and verify that any fix does not introduce leakage-sensitive components near the input node.
Why does the circuit oscillate only with a long cable attached?
- Fast checks: vary cable length, add small capacitance steps to reproduce the boundary, and observe ringing/overshoot in step response.
- Fixes: add isolation resistance or RC damping at the input (kept clean/guarded), and limit bandwidth when the application allows it.
How should production test record leakage/drift so failures can be traced later?
- Fast checks: ensure the test uses a fixed fixture/cable and a consistent timing script so trends reflect leakage rather than setup noise.
- Fixes: store: baseline leakage, drift slope, RH sensitivity (slope vs RH), Trecover, cable-step peak/settle, cleaning batch ID, fixture ID, and ambient T/RH.
Is conformal coating always helpful for high-Z nodes?
- Fast checks: A/B compare coated vs uncoated boards across RH steps, and measure both drift slopes and recovery tails.
- Fixes: use coating only when it measurably improves RH sensitivity, and lock the coating process to maintain repeatability across lots.
Tip: For high-Z debugging, keep the fixture and cable constant, change one variable at a time, and always compare results before/after cleaning and across humidity.
