A low-drift TIA turns tiny sensor currents into stable, trustworthy voltage readings by treating stability (Cin + Cf), leakage/drift control, noise budgeting, and overload recovery as one engineered system.
This page provides a practical, reusable path to pick Rf/Cf, prevent cable/protection-induced oscillation, and verify drift/noise/recovery on the bench—so picoamp measurements remain stable in real boards and real environments.
What this page solves
A low-drift TIA is only “low drift” when stability, leakage, and noise are budgeted together. This page provides a reusable Rf/Cf workflow, practical stability and bandwidth targets, and a board-level checklist to control picoamp errors.
✅ Solves
Readings that drift over time or change with humidity/handling.
Wideband noise and low-frequency “wander” that hides slow signals.
Oscillation/ringing when a cable, sensor capacitance, or protection is added.
Slow recovery after overload events (clamps, saturation, sudden large current).
Unexpected zero errors dominated by PCB leakage and contamination.
🚫 Not covered
Photodiode/PMT system topics (dark-current trim, auto-range, optical performance metrics).
Electrochemical 3-electrode biasing and depolarization strategies.
Charge amplifiers and IEPE/piezo-specific front ends.
Deep anti-alias / reconstruction filter design (only TIA-side constraints are noted).
Full production analytics pipelines (only verification hooks and checklist items are included).
Cover the four failure modes first—stability with input capacitance, leakage/drift at the summing node, noise budgeting, and overload recovery—then lock Rf/Cf and verify on the bench.
Define Low-Drift TIA and where it fits
A low-drift transimpedance amplifier (TIA) converts tiny sensor currents into a measurable voltage while keeping the summing node predictable over time, temperature, and humidity. “Low drift” in a TIA is dominated by input bias/leakage, low-frequency noise, and slow recovery tails—not just DC offset on paper.
What “low drift” means in TIA work
Bias current & leakage: sets the true DC error through Rf and often dominates in humid/contaminated boards.
Temperature drift: offset and bias tempco determine slow baseline movement across operating range.
0.1–10 Hz noise: defines how stable slow signals look after averaging.
Dielectric absorption tails: creates “memory” and long recovery after overload or step events.
pA–nA: dark currents, high-impedance probes, micro-current sensing.
nA–µA: common photodiode and chemical sensor operating currents.
µA+ (overload): transients from hot-plug, strong light, clamps, or faults.
Term
Main impact
Quick verification
Ib
DC error through Rf, baseline drift
Short input, log Vout vs time/humidity
Vos
Output baseline shift, temp drift contribution
Temperature sweep, compare zero at each point
Cin
Stability/ringing, compensation sensitivity
Step response with/without cable/protection
Rf
Gain, thermal noise, DC error scaling
Apply known current, verify linearity/headroom
Cf
Phase margin, bandwidth, settling
Ringing/overshoot vs Cf sweep
Noise-gain
How en appears at the output
Compare noise with/without added Cin
Recovery
Overload tail, “memory” after clamps
Standard overload event, log return-to-zero
Model the input as a current source plus parallel capacitance and leakage to ground. That summing node behavior determines stability, drift, and recovery far more than “typical” datasheet numbers.
Core transfer: transimpedance gain, headroom, and error terms
The first-order relationship is simple: Vout ≈ −Iin · Rf. It holds only while the summing node stays near virtual ground and the amplifier remains in its linear output range. Start by proving headroom, then attribute error sources by category before doing any noise budgeting.
Error tree (engineering view)
DC terms
Bias/leakage → offset through Rf: Ib · Rf and board leakage create true baseline error.
Vos and temp drift: shifts the baseline across temperature and time.
Dielectric “memory”: slow tails after steps or overload can look like drift.
Dynamic terms
Finite AOL/GBW: the summing node is no longer ideal virtual ground, causing gain error near bandwidth limits.
Phase margin loss: ringing/overshoot corrupts “measured gain” before the output settles.
Saturation / overload terms
Output swing and drive: headroom limits define the true linear range.
Input range behavior: near-rail input stages can become nonlinear even before obvious clipping.
Clamp injection: protection paths can add bias and create long recovery tails after overload.
Calculation order (Step 1–5)
Define current range: Imin / Imax and any expected overload events.
Choose Rf for headroom: keep Vout inside the linear swing with margin.
Estimate baseline error: convert bias + leakage + Vos drift into output offset.
Set dynamic targets: bandwidth and settling time required by the measurement.
Only then budget noise: map output noise to an equivalent input current floor.
The usable measurement window is bounded above by linear headroom and below by the integrated noise floor. Baseline errors (bias/leakage/drift) shift the window and can consume usable range long before noise becomes the limit.
The real challenge: stability with input capacitance (Cin/Cs/cable)
Input capacitance (sensor + cable + protection + layout) is often the first-order stability driver in low-drift TIAs. As Cin increases, the noise gain rises earlier and faster, reducing phase margin and causing ringing or oscillation unless compensation is designed intentionally.
Symptom → mechanism → quick checks
Symptoms
Ringing/overshoot after steps, or small oscillations that appear only with a cable.
Noise level changes when a probe is attached or when the cable is touched.
Settling time is much longer than expected even when the gain looks correct.
Mechanism
Cin with Rf creates an earlier noise-gain rise, pushing the loop toward lower phase margin.
With insufficient compensation, the loop crosses unity gain where op-amp phase is already degraded.
Quick checks
Compare step response with and without the cable/protection parts installed.
Sweep Cf in small steps and confirm ringing reduces monotonically toward a controlled response.
Use a lower-capacitance probe (or an active probe) and check whether the waveform/noise changes.
Knobs you can control
Rf: sets transimpedance gain and the Cin-driven corner; larger Rf makes Cin effects appear earlier.
Cf: limits noise-gain rise to restore phase margin; too much Cf trades bandwidth and settling time.
Op-amp GBW / phase: determines where the loop crosses unity and how much phase is available.
Cin budget: include sensor, cable, ESD/protection, package, and layout parasitics.
Layout parasitics: summing-node routing and nearby switching edges can add effective Cin and injection.
Treat Cin as a budget item (sensor + cable + protection + layout). Compensation with Cf should be designed to restore phase margin while meeting bandwidth and settling targets.
Choosing Cf: compensation targets, bandwidth, and settling time
Cf is not a “make it stable” knob—it is a compensation target that must satisfy three closed-loop requirements: enough phase margin, only as much bandwidth as the measurement needs, and a controlled step response that settles inside the error band. Bigger Cf is not automatically better; it trades bandwidth and can extend recovery tails.
Pick Rf by range:
choose transimpedance gain and keep Vout in linear headroom with margin.
Solve Cf by stability target:
increase Cf in small steps until ringing is controlled, then verify bandwidth and settling time still meet requirements.
Compensation targets
Target 1 — Phase margin: no persistent ringing or probe-sensitive oscillation.
Target 2 — Bandwidth: enough for the signal dynamics, not “maximum possible.”
Target 3 — Step response: overshoot and settling time remain inside the error band.
Common pitfalls
Probe capacitance is treated as “system Cin”, so stability only exists during measurement.
ESD/TVS input capacitance is ignored, shifting the corner and killing phase margin on the real board.
Cable/fixture capacitance is missing from the Cin budget; the tuned Cf is too small in-system.
Cf is made very large to stop oscillation, then bandwidth and settling time quietly fail.
Ringing is blamed on “sensor noise” while the root cause is loop stability at the summing node.
Use a repeatable step test to tune Cf. Stop when ringing is controlled, then re-check bandwidth and settling time. If the response becomes slow, re-audit the Cin budget and protection choices instead of blindly increasing Cf.
Noise: en/in vs Rf/Cin, and how to budget it (without lying)
A credible noise budget separates contributions and states the bandwidth it is integrated over. In low-drift TIAs, Rf thermal noise sets a baseline, op-amp voltage noise is shaped by noise gain (often worsened by Cin), op-amp current noise matters at tiny currents, and 0.1–10 Hz noise/drift controls slow-read stability.
Noise term
Dominant when
How to reduce
Trade-off
Rf thermal
Large Rf, wide BW
Limit BW, avoid excess gain
Slower response
en term
High Cin, rising noise gain
Control noise gain (Cf/Cin), pick lower en
BW, power, stability margin
in term
Tiny currents, very high-Z inputs
Pick low in, manage temperature, limit BW
Device choice constraints
0.1–10 Hz
Slow signals, long averaging
Pick low LF noise, control drift/leakage
May expose recovery tails
A budget is only meaningful when it states the bandwidth and the measurement method. Control Cin and noise gain to prevent en from dominating, and treat low-frequency noise/drift as the limiter for slow, high-resolution readings.
In ultra-low-current TIAs, “drift” is often dominated by leakage around the summing node rather than by the typical datasheet numbers. Treat leakage as an unintended input current source: humidity, residues, protection devices, and capacitor memory can easily overwhelm pA-level signals.
3-layer drift map (root-cause view)
Layer A — IC / package
Ib temp drift: bias current changes with temperature and becomes output drift through Rf.
Vos temp drift: baseline moves with temperature and time, especially near rails.
Package moisture / stress: slow baseline movement under humidity and mechanical stress.
Layer B — PCB surface leakage
Flux/ionic residues: form a conductive film that grows dramatically with humidity.
Moisture / condensation: water films create leakage paths and “touch-sensitive” offsets.
Fingerprints / dust: uncontrolled leakage paths appear and change with handling.
Layer C — components near the node
Capacitor leakage & dielectric absorption: memory effects that look like slow drift.
ESD clamp leakage: reverse leakage and junction capacitance both hurt pA stability.
Parasitics: test pads, long traces, and solder mask edges can add leakage paths.
Board-level actions (reusable checklist)
Keep the summing node tiny: shortest route, no stubs, no nearby fast edges.
Use a guard ring: surround the summing node with a continuous ring and keep the area clean.
Driven guard (when needed): drive the guard to a suitable low-impedance potential near the node.
Define a keepout: no solder mask openings, no test pads, no silk, no vias in the clean zone.
Clean and verify: clean residues, then re-test under humidity/airflow to confirm improvement.
Optional coating: only after cleaning and validation; coatings can trap contaminants if applied too early.
Leakage debug order (fast isolation)
Disconnect the sensor: isolate external leakage and cable effects first.
Short or cap the input: force a known condition and observe baseline movement.
Humidity / airflow stimulus: add moisture or blow air and watch offset drift response.
Touch/move sensitivity: touch cable/nearby area; strong correlation points to surface leakage or injection.
Clean and re-test: a before/after comparison is the strongest evidence chain.
Keep the summing node inside a defined clean zone. Guarding reduces leakage-driven current into the node only if the surrounding surfaces stay clean and the guard is tied to a suitable low-impedance potential.
Input protection & overload recovery (why it takes minutes to come back)
Minute-scale recovery is usually a charge-storage problem near a high-impedance summing node. During overload, clamps conduct and inject charge; Cin/Cf and parasitics get charged, then discharge through extremely weak leakage paths. Protection strength often trades directly against input capacitance, leakage, and charge injection.
Cin/Cf charged; dielectric absorption and leakage dominate
Reduce charge storage; choose low-memory parts near node
Protection improves survival but worsens stability/noise
Input Cin and leakage rise; noise gain and drift increase
Use staged limiting; keep high-C devices away from node
Engineering strategies (trade-off aware)
Stage the protection: limit current first, then clamp; avoid placing large-junction parts at the summing node.
Prefer soft limiting: reduce charge injection compared to hard clamps when possible.
Add a controlled discharge path: ensure stored charge has a defined way to bleed off without corrupting normal measurement.
Keep Cin and leakage low: protection strength must be balanced against stability, drift, and recovery time.
If recovery is slow, measure time-to-error-band after a defined overload event. Then reduce charge injection and provide a controlled discharge path while keeping added input capacitance and leakage under control.
Component choices that actually matter: Rf/Cf technology, dielectrics, parasitics
In picoamp TIAs, “same schematic, different parts” is a real system change. Rf sets noise and drift sensitivity through temperature and voltage coefficients plus packaging leakage; Cf can add memory (dielectric absorption) and leakage; protection devices add input capacitance and leakage that directly raise stability and drift risk at the summing node.
Map each “mysterious” symptom to a parasitic: Cp shifts stability, leakage shifts baseline, DA creates memory tails, and ESD Cin raises noise gain and compensation burden.
Layout & wiring for picoamp nodes: routing, shielding, cables, probing
Picoamp nodes are not “just another net.” The summing node must be tiny, clean, and far from high dv/dt and digital edges. Cable capacitance must be treated as Cin in the stability budget, and measurement methods must be chosen so probing does not change the circuit.
Do
Tiny summing node: shortest route, no stubs, no test pad on the node.
Guard ring + keepout: define a clean zone around the node.
Keep high dv/dt away: switching nodes and clocks stay far from the node region.
Budget cable Cin: cable length and type are part of the compensation plan.
Use short probe return: minimize ground loop area during measurements.
Validate with stimulus: move the cable and vary humidity to expose leakage sensitivity.
Don’t
Do not route a long high-impedance node trace across the board.
Do not place a switching node or fast digital edge next to the summing node.
Do not assume probing is “free”: probe Cin and leakage can dominate behavior.
Do not tune Cf only after wiring changes; treat the cable as Cin from day one.
Do not use long ground clips that create large measurement loop areas.
Do not leave flux residues and exposed surfaces near the node.
Treat wiring and probing as part of the circuit. Cable Cin and probe Cin change noise gain and stability; keep the summing node tiny, guarded, and far from switching and digital edges.
Verification plan: stability, noise, drift, and recovery tests (bench recipes)
A low-drift TIA must be validated with repeatable bench recipes under the same Cin conditions used in the real system (sensor + cable + protection + probing). The test plan below turns stability, noise, drift, and overload recovery into measurable pass/fail criteria and comparable logs.
Bench recipes (reusable)
Stability recipe
Stimulus: step/pulse via small coupling capacitor (square wave) or a repeatable current-step fixture.
Record: Cin condition, overshoot, ringing cycles, settling time, sensitivity to probe/cable movement.
Pass: no sustained oscillation; ringing decays; settling fits the project time window at worst-case Cin.
Noise recipe
Wideband RMS: define measurement bandwidth, anti-aliasing, sampling rate, and record length.
0.1–10 Hz: define warm-up, time window, sample spacing, and detrend rule; document conditions.
Pass: meets the allocated noise budget under the same Cin and shielding/probing method.
Drift recipe
Run in three conditions: sensor disconnected → input shorted → sensor + cable connected.
Stress: temperature points (at least 2–3) and humidity/airflow sensitivity checks.
Pass: baseline drift stays inside the error window; humidity sensitivity is controlled after cleaning/guarding.
Recovery recipe
Define a standard overload event (amplitude + duration) that forces clamp/saturation.
Record: saturation depth, time-to-error-band, and recovery tail shape.
Pass: time-to-error-band meets the required “back-to-usable” window; tail does not create long-lived offset.
Test item
Stimulus
Instrument
Pass criteria
Notes
Stability (step response)
Cap-coupled square wave or current-step fixture
Scope + function generator
No sustained oscillation; settling ≤ time window at worst Cin
Document Cin: sensor + cable + ESD + probe
Noise (wideband RMS)
Fixed BW + fixed record length
ADC or DMM + logging
RMS ≤ allocated noise budget (same BW & setup)
State input condition: short / sensor / cable
Noise (0.1–10 Hz)
Long time window + defined detrend
DMM/ADC + stable thermal setup
Within low-frequency budget after warm-up
Always log warm-up time and ambient
Drift (temp/humidity)
Temp points + humidity/airflow sensitivity
Thermal chamber or controlled stimulus + logging
Baseline stays inside error window across conditions
Cf (ceramic): C0G/NP0 dielectric (class recommendation for low memory)
The same Cin and probing conditions used on the bench must match the real wiring and protection stack, otherwise stability and drift results will not transfer.
Use this checklist to keep the design process disciplined: requirements must define the budget, schematic choices must be verifiable, layout must protect the summing node, and bring-up must add complexity step-by-step to avoid chasing false failures.
Design checklist (requirements + schematic)
Define current range (min/typ/max) and required headroom at Vout.
FAQs (low-drift TIA): quick fixes without widening the scope
These FAQs collect the most common bench and field issues for picoamp TIAs—cable/Cin stability, leakage/drift, probing artifacts, and overload recovery—so the main page stays focused.
Why does the output change when the cable is touched or moved?
Symptom
Baseline, noise, or stability changes when the cable is moved, touched, or re-routed.
Likely causes (Top 3)
Cable capacitance changes the effective Cin, shifting noise gain and phase margin.
Leakage paths (humidity/contamination) are modulated by handling and triboelectric effects.
Shield/ground return changes inject common-mode or EMI into the summing node region.
Quick checks (2–3 steps)
Repeat with input shorted at the connector; if the effect persists, it is board/cable/probing, not the sensor.
Swap to a shorter cable and re-run step response; stability sensitivity indicates Cin-driven behavior.
Blow dry air / gently warm the board; humidity sensitivity points to leakage/contamination.
Fixes (priority order)
Budget cable Cin explicitly and choose Cf for the worst-case cable + protection + probe stack.
Improve node hygiene: keepout + guard, documented cleaning, and controlled handling around the node.
Stabilize shielding/return: consistent shield termination and reduced loop area near the front-end.
Don’t do
Do not “tune Cf” using a short bench cable and assume it will work with the final cable harness.
How do I estimate the “real” input capacitance seen by the TIA?
Symptom
Cf selection and stability predictions do not match bench behavior because Cin is underestimated.
Likely causes (Top 3)
Cable capacitance dominates and was not counted (pF/cm or pF/ft class effects).
Protection parts add Cin (ESD diode, clamp network) closer to the node than expected.
Probe and test fixtures add capacitance and change ground return coupling.
Quick checks (2–3 steps)
Measure cable capacitance with an LCR meter (disconnect both ends); log pF vs length.
Repeat step response with and without the protection network populated to observe Cin impact.
Compare scope results using a low-C active probe vs a standard passive probe.
Fixes (priority order)
Define Cin as a stack: sensor + cable + ESD + routing parasitics + probe; design for worst-case.
Move high-C protection away from the summing node (staged protection) where feasible.
Provide a stable measurement point at low-impedance nodes to avoid probing the summing node.
Don’t do
Do not treat probe capacitance as negligible when the design is sensitive to tens of pF.
Why does adding a protection diode make the TIA oscillate?
Symptom
A stable TIA becomes noisy, rings, or oscillates after adding clamps/ESD diodes.
Likely causes (Top 3)
The protection device adds Cin at the summing node, increasing noise gain at high frequency.
Nonlinear junction capacitance and layout parasitics add extra poles/zeros.
Clamp placement changes return currents and injects fast transients into the node region.
Quick checks (2–3 steps)
Compare step response (same stimulus) with protection depopulated vs populated.
Temporarily add a known capacitor to emulate the diode Cin; if behavior matches, Cin is the driver.
Probe Vout with the least-invasive probe available; verify oscillation is not a probing artifact.
Fixes (priority order)
Re-select Cf for the new worst-case Cin (including protection); confirm settling window is still met.
Use staged protection: small-signal leakage-friendly elements near the node, larger ESD parts at the connector.
Improve routing: shorter node, controlled return, and physical separation from dv/dt aggressors.
Don’t do
Do not place a high-capacitance clamp directly on the summing node and expect stability to remain unchanged.
What’s the fastest way to tell if the issue is leakage or bias current?
Symptom
The baseline drifts or offsets unexpectedly, and the source of the error is unclear.
Likely causes (Top 3)
Surface leakage across PCB contamination or humidity paths near the summing node.
Op-amp input bias current and its temperature dependence.
Leakage from components connected to the node (Cf, protection, connector insulation).
Quick checks (2–3 steps)
Disconnect the sensor and leave the input open; then short the input and compare baseline behavior.
Apply humidity/airflow stimulus (gentle breath at a distance or controlled humid air); leakage responds strongly.
Warm the board slightly and observe slope change; bias-driven offsets usually show stronger temperature correlation.
Fixes (priority order)
Leakage control first: keepout + guard, documented cleaning, and reduced exposed surfaces near the node.
Reduce bias impact: verify input bias specification at the actual temperature and common-mode; confirm headroom.
Audit node-connected parts: replace leakage-prone components and re-test under humidity stimulus.
Don’t do
Do not chase bias-current explanations before ruling out board-level leakage with humidity/cleanliness checks.
Why does the TIA take seconds/minutes to recover after overload?
Symptom
After a strong input event (light spike, electrode hit, hot-plug), the output baseline returns very slowly.
Likely causes (Top 3)
Clamp conduction injects charge; Cf and node capacitances store it and leak out slowly.
Dielectric absorption (“memory”) in Cf creates a long recovery tail after large steps.
Input stage overdrive recovery is slow, especially when output saturates deeply.
Quick checks (2–3 steps)
Reproduce with a standardized overload amplitude and duration; log time-to-error-band.
Disable/replace clamps temporarily; if the tail improves, charge injection is dominant.
Swap Cf technology/value and compare tail shape; strong “memory” points to Cf DA/leakage.
Fixes (priority order)
Prevent deep saturation: add staged limiting so clamps do not slam the summing node.
Select Cf for low memory and acceptable leakage; verify recovery time meets the application window.
Review headroom and recovery: ensure output swing margins and avoid operating near rails when possible.
Don’t do
Do not accept minute-scale recovery as “normal” without isolating clamp injection vs capacitor memory.
Is a larger Cf always safer for stability? What does it cost?
Symptom
Increasing Cf reduces ringing but the system becomes slow, noisy in-band, or recovers poorly after events.
Likely causes (Top 3)
Large Cf lowers bandwidth and extends settling time beyond the application window.
Large Cf increases stored charge, worsening overload recovery tails.
Cf leakage and dielectric memory can dominate drift and recovery in picoamp systems.
Quick checks (2–3 steps)
Measure step response and log settling time vs Cf (same Cin condition).
Run a standardized overload event and compare time-to-error-band vs Cf.
Check 0.1–10 Hz noise and baseline drift after warm-up for each Cf option.
Fixes (priority order)
Choose Cf to meet a stability target at worst Cin while respecting bandwidth/settling requirements.
If stability margin is tight, reduce Cin (cable/protection/probing) before inflating Cf.
Use low-memory, low-leakage Cf technology when recovery and drift are critical.
Don’t do
Do not select Cf by “no ringing on the scope” alone; always check settling and recovery tails.
How do I measure 0.1–10 Hz noise correctly for a TIA?
Symptom
Reported low-frequency noise changes drastically between setups, instruments, or teams.
Likely causes (Top 3)
Measurement window, warm-up time, and detrend rules are not controlled.
Environmental drift (temperature/humidity/airflow) leaks into the “noise” number.
Instrument settings (filters, sample rate, aperture) change the effective band.
Quick checks (2–3 steps)
Lock the procedure: warm-up time, record length, sample spacing, and a fixed detrend method.
Run with input shorted and then with the real Cin stack; log both for comparability.
Record ambient changes (temp/humidity) during the capture; correlate any slow slope.
Fixes (priority order)
Standardize test conditions: stable thermal environment, fixed sampling plan, and logged metadata.
Separate drift from noise using repeatable short/open/sensor conditions and environment notes.
Use the same instrument filter chain and report it with every 0.1–10 Hz result.
Don’t do
Do not compare 0.1–10 Hz numbers without matching window length, warm-up, and detrend rules.
Why does the noise get worse when probing with an oscilloscope?
Symptom
Connecting a scope probe increases noise, adds ringing, or changes the baseline.
Likely causes (Top 3)
Probe capacitance adds to Cin, raising noise gain and reducing phase margin.
Probe leakage and surface contamination create a parallel leakage path near the node.
Long ground leads create a loop antenna that couples EMI into the measurement.
Quick checks (2–3 steps)
Use a short ground spring or coax ground return and compare to a long ground clip.
Try a low-C active probe and compare ringing/noise to a standard passive probe.
Measure at a low-impedance point (Vout) rather than the summing node whenever possible.
Fixes (priority order)
Probe correctly: shortest return, minimal capacitance, and stable shielding near the front-end.
Budget probe Cin as part of worst-case Cin when validating stability on the bench.
Add dedicated test points at low-impedance nodes so the summing node is not touched.
Don’t do
Do not interpret “scope makes it worse” as proof of EMI only; first assume Cin/loop effects.
Which matters more here: voltage noise (en) or current noise (in)?
Symptom
Op-amp selection is confusing because some parts win on en while others win on in/bias.
Likely causes (Top 3)
High source impedance and large Cin make en convert into current via jωCin·en.
Large Rf and tiny currents make in and bias/leakage dominate baseline and low-frequency performance.
Stability tuning (Cf) changes noise gain, moving the balance between terms.
Quick checks (2–3 steps)
Increase Cin (add known capacitor) and see if noise rises; strong sensitivity indicates en·Cin dominance.
Increase Rf and see if baseline/noise rises; strong sensitivity indicates in/bias/leakage dominance.
Compare short-input noise vs sensor+cable noise; divergence indicates Cin/source-driven terms.
Fixes (priority order)
For large Cin/high-Z sensors: prioritize low en and stable compensation at worst Cin.
For picoamp DC accuracy: prioritize low bias/leakage and low in; enforce board cleanliness and guarding.
Validate by measurement: report RMS noise over defined BW and 0.1–10 Hz under the real Cin stack.
Don’t do
Do not pick an op-amp using en alone when cable/protection capacitance is a dominant system parameter.
How to choose Rf technology to minimize drift and leakage?
Symptom
Identical TIA schematics behave differently after changing Rf part number or footprint.
Likely causes (Top 3)
Temperature coefficient (TCR) and voltage coefficient (VCR) change gain and linearity under swing.
