Common pain points this page fixes

• Cable movement changes the reading (capacitance/leakage and shielding effects).
• Baseline drift at low frequency (leakage paths, bias currents, absorption “memory”).
• Humidity and contamination shift the zero point (board/connector surface leakage).
• ESD/handling degrades performance over time (leakage and protection trade-offs).
• Large shocks saturate the amplifier and recovery is slow (overload recovery and time constants).

Outcomes to expect (engineering deliverables)

• Stable Vout from a charge source, with a clear parameter flow-down.
• Charge-to-voltage sizing for Cf and Rf (dynamic range + low-frequency pole).
• Stability fixes that work across real cable capacitance variation.
• Leakage/drift control methods that survive humidity, connectors, and handling.
• Layout + verification checklist to make the design repeatable in production.

Out of scope (kept on sibling pages)

• IEPE/ICP constant-current sensor powering standards and receivers (only interface hooks are mentioned here).
• General sensor theory or mechanical mounting guidance.
• Photodiode/PMT transimpedance specifics (different source physics and noise terms).

Minimal equivalent model (what matters in real hardware)

• Q: generated charge from mechanical stimulus (the primary signal variable).
• Cs: sensor capacitance; sets the source capacitance seen by the amplifier.
• Rp / Leak: insulation and surface leakage; dominates low-frequency drift and baseline recovery.
• Ccable: cable capacitance added at the input; impacts stability and noise gain.

Turning a sensor datasheet into circuit numbers (workflow)

1. Convert sensor sensitivity (often in pC per unit) into a Qmax for the worst-case event.
2. Get Cs from the sensor datasheet or measure it with an LCR meter at an appropriate frequency.
3. Estimate Ccable from the cable spec (pF/m) times length, or measure it with the cable installed.
4. Treat Leak as an environment-dependent parameter: connector, humidity, PCB cleanliness, and guarding change it by orders of magnitude.

What the ideal relationship means in real hardware

• Cf sets sensitivity: smaller Cf increases Vout per unit charge but saturates sooner.
• Cs + Ccable do not set gain (ideally): they mainly influence stability and noise gain, not the Q→V conversion factor.
• Rf provides a DC path: it prevents output “sticking” and sets the low-frequency behavior and baseline recovery time.

How to size Cf and Rf (parameter flow-down)

1. Define Qmax from the worst-case event (shock/impact peaks, not just typical levels).
2. Choose Vout range to avoid saturation (output swing headroom + ADC full-scale + overload margin).
3. Compute Cf so Qmax maps into the allowed Vout range (leave margin for transients and tolerances).
4. Set Rf from the required low-frequency cutoff or baseline recovery time: larger Rf recovers more slowly; smaller Rf rolls off more low-frequency content.

Single-ended charge amplifier (most common)

• Use when: cable lengths are moderate and the ground reference is well-controlled.
• Main risk: sensitive to ground noise and shield/return routing.
• Key hooks: shield strategy, input protection, and output isolation to the next stage.

Pseudo-differential / differential sampling (for noisy grounds and DAQ inputs)

• Use when: long cables, ground potential differences, or a differential ADC/DAQ input is available.
• Main risk: common-mode range and matching; the receiving stage must tolerate expected CM shifts.
• Key hooks: define a stable reference and keep the measurement as a pair (signal + return).

Guarded input (for ultra-high impedance and leakage control)

• Use when: pA-level leakage matters (humidity, contamination, high-Z connectors).
• Main risk: guard is not a substitute for cleanliness; incorrect guarding can add coupling.
• Key hooks: guard the high-impedance node and control where leakage currents are allowed to flow.

Symptom patterns that strongly suggest a cable-capacitance stability issue

• Only certain cable lengths oscillate: the added C shifts breakpoints and loop crossover frequency.
• Touching or moving the cable triggers ringing: capacitance and shield coupling change in real time.
• Temperature changes turn a stable build unstable: open-loop gain/phase and input parameters drift, consuming margin.

High-leverage fixes (keep the list short and effective)

• Input series damping (Rin): adds loss in the input C network to reduce peaking and sensitivity to cable variation.
• Shape the loop with a Cf-related zero: a small parallel element can move the noise-gain breakpoint away from crossover.
• Output isolation (Riso) + RC snubber: prevents capacitive loads and ADC input networks from pulling phase down.
• Choose a more suitable op amp: enough GBW and phase margin in the expected total input capacitance range.

Three mechanisms that dominate baseline drift and slow recovery

• Leakage (PCB + connector + cable): creates an unintended current path at the high-impedance node, shifting baseline.
• Input bias current (Ib): forces a DC current that must flow through the feedback network, producing an output offset/drift term.
• Dielectric absorption (DA) in Cf: stores and releases charge slowly, causing “memory” after large events.

Why lab-stable designs can drift on-site

• Humidity and residue can change surface leakage by orders of magnitude.
• Connectors and cable ends often dominate leakage under condensation or contamination.
• Handling and ESD events can create new leakage paths unless protection is designed for high-impedance nodes.

Noise sources that typically dominate in piezo charge amplifiers

• Op-amp voltage noise (en): transferred through the loop and multiplied by noise gain at higher frequencies.
• Op-amp current noise (in): converts to voltage noise when the feedback path is high impedance (large Rf).
• Rf thermal noise: always present and often prominent when Rf is large or the target bandwidth includes low frequencies.
• Noise gain from total input capacitance: Cin shifts breakpoints and can raise the effective contribution of en.

Bandwidth integration (why RMS noise grows with BW)

• RMS noise comes from integration: noise spectral density accumulates over the measurement bandwidth.
• Wide bandwidth pushes toward en limits: especially when noise gain rises due to large Cin.
• Low frequency adds 1/f tradeoffs: zero-drift parts reduce 1/f and offset drift, but switching artifacts must stay outside the band of interest.

Practical rules of thumb (use trigger conditions, not slogans)

• Prioritize low in: high-impedance designs with large Rf and low-frequency bandwidth goals.
• Prioritize low en: wideband designs and cases where noise gain rises at higher frequencies.
• Watch Rf thermal noise: large Rf can become the floor even when the op amp looks “quiet” on paper.

Input protection goals (in order)

• Absorb ESD energy near the connector: keep the return path short and out of the high-Z region.
• Limit current into the sensitive node: series resistance prevents clamps and inputs from being overstressed.
• Clamp voltage without leakage: avoid protection parts that add large leakage at temperature or humidity.
• Recover quickly after overload: prevent saturated states and stored charge from creating long baseline tails.

Field events that commonly break charge amplifiers

• Cable plug/unplug: stored charge and shield contact sequencing inject large transients.
• Miswiring and over-voltage: accidental connection to higher potentials or reversed polarity.
• Ground potential differences: remote sensor grounds shift, forcing large common-mode events.
• Shock/impact overload: output saturates and recovery becomes the limiting behavior.

Step 1 — Requirements (only fields that matter for charge amps)

• Qmax / event amplitude: sets Cf from allowed Vout swing.
• Target f_low: sets Rf/Cf time constant and recovery tail length.
• Target bandwidth (BW): sets integrated noise and stability margin needs.
• Cable uncertainty (Cin range): drives stability risk (length-dependent oscillation).
• Environment: humidity, contamination, cable handling, ESD/plug events.

Step 2 — Risks (what typically breaks charge amplifiers)

• Large / unknown Cin: noise-gain rise and phase-margin collapse → length-dependent ringing/oscillation.
• Ultra-low-frequency accuracy: leakage + bias current + dielectric absorption → baseline drift and memory tails.
• Overload events: saturation + stored charge → slow return to linear baseline.
• Wideband noise target: en × noise gain + BW integration dominates RMS noise.
• Protection leakage: clamp parts can become the dominant drift source if leakage is not controlled.

Step 3 — Specs to ask for (risk-mapped fields)

• Input bias current vs temperature: include worst-case at elevated temperature for drift ownership.
• Input structure / protection behavior: clamps, phase reversal behavior, and leakage implications.
• Noise (0.1–10 Hz + wideband) and current noise: choose en vs in based on Rf and BW.
• Stability guidance with capacitance: any recommended R/C damping or “stable with Cin” reference circuits.
• Overload recovery: time to return to linear region after large input events.
• Output swing and drive: especially if an ADC/DAQ input network is attached.
• EMI/ESD rating and leakage controls: verify the protection strategy does not become the drift source.

Step 4 — Acceptance tests (do not accept “specs only”)

Acceptance should follow the verification matrix: Cable / Temp / Humidity / Overload × Drift / Noise / Stability / Recovery. Specs are for screening; tests are for ownership.

Example part-number buckets (reference points)

Quick decision prompts (screening rules)

• Large / unknown cable capacitance: prioritize stable-with-Cin behavior, phase margin guidance, and repeat cable-length sweep tests.
• Ultra-low-frequency drift in humid/dirty environments: prioritize leakage ownership (bias current at temperature, guard strategy, cleanliness constraints), then validate with humidity/cleaning A/B.
• Frequent impact / overload: prioritize overload recovery and staged protection that does not store charge or add leakage.
• Wideband noise target: prioritize en under expected noise-gain rise, then validate with bandwidth-limited RMS noise.

RFQ / FAE question template (copy-paste)

1. Input bias current typical/max at 25°C and elevated temperature; include test conditions.
2. Input protection/clamp structure and behavior under reverse/over-voltage; leakage implications.
3. Stability guidance with total input capacitance (sensor + cable + Cin); any reference circuits.
4. 0.1–10 Hz noise and wideband noise density; current noise density for high-Rf use cases.
5. Overload recovery behavior (waveforms or typical time-to-linear) after large input events.
6. Output swing and drive ability into the intended DAQ/ADC input network.
7. ESD/EMI characteristics and any recommended PCB guarding/cleanliness practices for high-Z nodes.
8. Recommended verification plan across cable length, temperature, humidity, and overload.

Why does the baseline drift for minutes after a large shock input?

A long tail after shock is usually stored charge plus slow discharge paths, not random noise. The recovery time is often set by the Rf/Cf time constant and by dielectric absorption in Cf and nearby materials.

Most likely causes

• Op-amp saturation and overload recovery behavior.
• Dielectric absorption (DA) in Cf causing “memory” tails.
• Protection parts storing charge or adding leakage paths.
• Large Rf/Cf time constant making baseline return inherently slow.

First checks

• Confirm whether the op-amp output hits a rail during shock.
• Swap Cf to a low-DA type and compare tail length.
• Temporarily simplify protection and compare recovery (controlled test).

Fix direction

• Reduce saturation events (Cf sizing, input limiting) and improve overload recovery.
• Use low-DA feedback capacitors and minimize high-Z surface exposure.
• Rework protection so it does not store charge or add leakage.

Why does the output change when the cable is touched or moved?

Cable touch and motion inject displacement currents and change effective capacitance, which can modulate the high-impedance input node. Shield termination, guarding, and return-current routing usually decide whether this becomes a visible output shift.

Most likely causes

• Shield reference and return path allowing touch-induced currents into the high-Z node.
• Large cable capacitance increasing noise gain and reducing phase margin.
• Insufficient guarding around the input island (surface leakage modulation).

First checks

• Compare behavior with different cable lengths and a known-good shield termination.
• Verify the guard ring/trace surrounds the high-Z input node and is correctly referenced.
• Move return currents away from the high-Z island and re-test touch sensitivity.

Fix direction

• Improve shield termination strategy and keep shield returns away from the input island.
• Add input damping/compensation to regain stability margin with Cin.
• Implement driven guarding and reduce exposed high-Z surfaces.

How do Cf and Rf set the low-frequency cutoff and recovery time?

Cf sets the charge-to-voltage gain (Q→V), while Rf provides the DC return path that defines the low-frequency behavior. A larger Rf or Cf typically slows baseline return and extends recovery tails; a smaller time constant increases the low-frequency cutoff.

Most likely causes

• Rf·Cf time constant is set too long for the intended recovery speed.
• Low-frequency targets conflict with acceptable drift and tail behavior.
• Additional leakage paths effectively reduce Rf in uncontrolled ways.

First checks

• Compute the intended Rf·Cf time constant from f_low and compare to measured recovery.
• Measure baseline return after a known step input and record tail time.
• Check for contamination/connector leakage that changes effective Rf.

Fix direction

• Select Rf/Cf to meet both low-frequency response and recovery-time constraints.
• Control leakage with guarding/cleanliness so Rf behaves as designed.
• Use low-DA Cf to reduce apparent long tails.

What is the first thing to check when a charge amp oscillates with long cables?

First check the total input capacitance (sensor + cable) and the stability margin it creates. Long cables raise Cin, increase noise gain, and can collapse phase margin, causing ringing or oscillation only at certain lengths.

Most likely causes

• Excess Cin driving noise-gain rise and phase-margin loss.
• Missing input damping (series R) or compensation zero.
• Op-amp not suitable for capacitive input conditions.

First checks

• Repeat with a short cable; then sweep cable length to map stability boundary.
• Add a small input series resistor (damping) and compare ringing.
• Verify layout: short high-Z trace, guarding, and return-current separation.

Fix direction

• Add input damping and/or compensation to regain phase margin with Cin.
• Choose an op-amp with better phase behavior under the expected Cin range.
• Keep the high-Z island compact and well guarded.

Which capacitor dielectrics are safe for Cf in low-drift charge amplifiers?

Cf should minimize dielectric absorption and leakage because these create memory tails and baseline drift. “High-K” ceramics often introduce stronger DA and voltage/temperature effects; low-DA choices usually behave more predictably in low-drift designs.

Most likely causes

• Dielectric absorption in Cf creating slow “memory” after steps/overload.
• Capacitor leakage and humidity sensitivity shifting the baseline.
• Voltage coefficient causing gain and recovery changes across events.

First checks

• Replace Cf with a known low-DA dielectric and compare tail and drift.
• Run a repeatable step test and compare baseline return curves.
• Check Cf placement and cleanliness around the high-Z node.

Fix direction

• Prefer low-DA, low-leakage capacitor types for Cf and keep them close to the op-amp input.
• Minimize surface leakage with guarding and controlled solder mask strategy.
• Validate with overload and step-response tails before freezing the BOM.

How can humidity and PCB contamination create “mystery leakage” and drift?

On high-impedance nodes, a thin conductive film from humidity plus residue can create leakage comparable to or larger than bias currents. This shifts the baseline, changes recovery time, and makes behavior appear inconsistent across locations and handling.

Most likely causes

• Flux residue or ionic contamination forming a humidity-dependent leakage path.
• Solder mask openings and long exposed traces increasing surface conduction.
• Connector/cable insulation leakage dominating at high humidity.

First checks

• Run a cleaning A/B test and compare drift and recovery tails.
• Run a controlled humidity exposure test and compare baseline shift.
• Swap connectors/cables and compare leakage-driven drift changes.

Fix direction

• Use driven guarding and keep the high-Z island compact with controlled mask strategy.
• Enforce cleanliness and reduce exposure near connectors and handling zones.
• Choose low-leakage protection and connector materials for the environment.

When does current noise dominate over voltage noise in a charge amplifier?

Current noise dominates when the effective impedance at the input or feedback path is high (large Rf, low-frequency emphasis), while voltage noise dominates more often in wideband conditions where noise gain and bandwidth integration set the RMS floor.

Most likely causes

• Large Rf converting current noise into output noise.
• Low-frequency targets increasing the impact of 1/f-related noise terms.
• High Cin raising noise gain, amplifying voltage noise at higher bandwidths.

First checks

• Measure noise with a defined bandwidth limit and record RMS.
• Compare short-input vs capacitor-substitute configurations for attribution.
• Check whether Rf is driving the noise target (high-Rf scenario).

Fix direction

• Match op-amp noise type (en vs in) to Rf and bandwidth goals.
• Limit bandwidth intentionally rather than relying on accidental roll-off.
• Reduce noise gain rise by controlling Cin and stabilizing the input network.

How to design input protection without adding leakage that ruins accuracy?

Protection must absorb energy and limit current while keeping leakage off the high-impedance node. The safest approach is staged protection: handle energy near the connector, then limit current, then clamp with parts chosen for low leakage in the real environment.

Most likely causes

• Clamp parts with humidity/temperature leakage placed directly on the high-Z node.
• Protection storing charge that releases slowly after transients.
• Series resistance missing, causing large currents into clamps/op-amp input.

First checks

• Measure drift with and without the clamp population (controlled A/B build).
• Check clamp leakage across temperature and humidity exposure.
• Verify a current-limiting series resistor exists before the clamp stage.

Fix direction

• Move energy-handling to the connector side and keep the high-Z node “clean”.
• Select clamps for low leakage under worst-case environment, not just room conditions.
• Limit current and avoid clamp topologies that store charge on the high-Z node.

Why does the circuit behave differently across temperature even with the same sensor?

Temperature changes bias currents, leakage, dielectric absorption, and loop stability margin. Even with the same sensor, these shifts can change drift, recovery tails, and the stability boundary with cable capacitance.

Most likely causes

• Input bias current and board leakage increasing strongly with temperature.
• Op-amp open-loop gain/phase changing, shifting stability margin with Cin.
• Dielectric absorption and capacitor properties changing with temperature.

First checks

• Run a temperature sweep and record drift, ringing, and recovery tail metrics.
• Repeat the cable-length stability sweep at hot and cold points.
• Check leakage-sensitive areas for contamination and condensation risk.

Fix direction

• Choose parts and materials with controlled leakage and DA across temperature.
• Design stability margin for worst-case Cin and worst-case temperature.
• Use guarding/cleanliness as a temperature-robust leakage control.

How to validate stability without a network analyzer?

Stability can be validated with repeatable step stimuli and cable/capacitance sweeps. Ringing, overshoot, and length-dependent oscillation are practical indicators of insufficient phase margin in the real Cin range.

Most likely causes

• Hidden stability boundary that only appears at certain Cin or temperature points.
• Output loading or ADC input network adding extra phase lag.
• Layout coupling injecting perturbations near the high-Z node.

First checks

• Apply a controlled step and record overshoot/ringing at multiple cable lengths.
• Replace the sensor with a known capacitor to emulate worst-case Cin.
• Test with and without the intended output/ADC load network.

Fix direction

• Increase damping/compensation and validate across the full Cin and temperature range.
• Add output isolation/RC snubbers if the load network contributes to ringing.
• Ensure the high-Z island is compact and return currents are routed away.

What causes slow “memory effect” after overload, and how to reduce it?

“Memory effect” is usually dielectric absorption and slow charge release on high-impedance surfaces and protection structures. It can look like drift, but it often correlates with large prior events and disappears when low-DA materials and clean guarding are used.

Most likely causes

• Dielectric absorption in Cf and nearby capacitors/materials.
• Charge trapped on contaminated surfaces around the input island.
• Protection networks releasing charge slowly after clamping events.

First checks

• Run a repeatable overload/step pattern and compare tail repeatability.
• Swap Cf to a low-DA type and compare the memory tail magnitude.
• Clean and guard the input island and compare baseline behavior.

Fix direction

• Use low-DA Cf and reduce high-Z surface exposure with driven guarding.
• Rework protection so clamping does not store charge on sensitive nodes.
• Validate with defined overload tests before finalizing layout and BOM.

How to interface a charge amp output to an ADC without adding ringing or distortion?

ADC input networks can look like dynamic capacitive loads that excite ringing. The safest approach is to control the load seen by the op-amp output (isolation R, RC snubbers, and bandwidth shaping) and verify with real sampling activity.

Most likely causes

• ADC sampling transients creating a time-varying capacitive load.
• Output phase lag from load network reducing phase margin.
• Insufficient output isolation or missing damping/snubber network.

First checks

• Probe the charge-amp output with the ADC connected and sampling enabled.
• Add an output isolation resistor and compare ringing and settling.
• Try a small RC snubber at the output and compare stability and distortion.

Fix direction

• Isolate the op-amp output from the sampling network and tune damping for worst-case sampling activity.
• Keep output routing short and reference returns clean to reduce ringing excitation.
• Validate settling and distortion with the final ADC input network, not an ideal load.