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Op Amp DC Accuracy: Offset, Drift, CMRR/PSRR, Bias & Noise

Op Amp DC Accuracy: Offset, Drift, CMRR/PSRR, Bias & Noise

← Back to:Operational Amplifiers (Op Amps)

DC accuracy is the art of turning op-amp specs into a guaranteed reading: offset and drift set the baseline error, bias/leakage creates hidden DC shifts through source impedance, and CMRR/PSRR plus low-frequency noise decide whether the number stays stable in real hardware.

This page shows how to read datasheets by conditions, convert each spec into an error budget, and use quick tests to separate op-amp limits from PCB and cabling effects—without drifting into stability or high-speed topics.

What this page solves (Scope & boundary)

This page explains why DC measurements become inaccurate, drift over time or temperature, respond to common-mode and supply variation, and how low-frequency and wideband noise translate into real reading jitter.

Covers
  • Offset & drift (temp + time)
  • CMRR & PSRR (DC relevance)
  • Bias current & leakage errors
  • 0.1–10 Hz and wideband noise
  • Error budgeting and verification hooks
Does NOT cover
  • Stability / phase margin / compensation
  • High-speed dynamics (GBW, slew, settling)
  • Distortion metrics (THD/SFDR)
  • ADC driver and filter design
  • High-speed sampling chain integration
Jump-to siblings
  • Ringing/oscillation → Stability & compensation page
  • THD worse than expected → Low-distortion driver page
  • Bandwidth/step response → High-speed VFA/CFA pages
  • Filter corner/group delay → Filter pages
  • EMI/ESD layout → EMI/robust op amp page

A practical DC-accuracy workflow is to translate datasheet conditions into input-referred errors, then identify the dominant term on the real board using targeted tests.

Op amp DC accuracy error-term map Box diagram showing signal source into an op amp and measurement output, with labeled error terms: offset, drift, bias and leakage, CMRR, PSRR, and noise contributing to output error. Signal source Sensor / node Op amp DC accuracy terms Output Measurement Error @ output Supply rails PSRR Common-mode CMRR Offset Drift Bias + leakage Noise Goal: translate specs into input-referred errors, then isolate the dominant term on the board.

DC accuracy: how datasheets actually specify it (Spec map)

A datasheet number is only actionable when its test conditions match the real system. This section turns DC-accuracy specs into practical engineering fields and lists the conditions that must be verified before using them in an error budget.

1
Offset (VOS)
What it breaks
  • Constant DC reading error after calibration
  • Gain-stage output offset that looks like “sensor bias”
  • Range-dependent errors when output swing changes
Common misreads
  • Using typical VOS instead of max (guaranteed) VOS
  • Ignoring input common-mode location (near-rail behavior)
  • Assuming one number applies across all loads and swings
Conditions to check
  • Max vs typical, and temperature range used for the guarantee
  • Input common-mode point (mid-rail vs near rails)
  • Closed-loop gain configuration (buffer vs gain stage)
  • Output swing and load used during the test
2
Drift (dVOS/dT + time)
What it breaks
  • Readings that change with ambient or self-heating
  • Slow drift after rework, cleaning, or enclosure changes
  • “Good at 25°C, bad in production temperature” outcomes
Common misreads
  • Assuming drift is perfectly linear across the full range
  • Ignoring long-term drift / package stress effects
  • Using room-temperature drift to predict field behavior
Conditions to check
  • Max drift vs typical drift and temperature endpoints
  • Whether drift is specified as a slope or a peak-to-peak curve
  • Any long-term drift data and its time base
  • Package notes related to stress / humidity sensitivity
3
CMRR (DC vs low-frequency)
What it breaks
  • DC error that changes when cable or common-mode changes
  • Bridge/remote-sense errors that look like “mysterious bias”
  • Board-to-board accuracy spread from network mismatch
Common misreads
  • Using DC CMRR to predict behavior under low-frequency interference
  • Ignoring the input common-mode operating point
  • Forgetting external R/C mismatch often sets system CMRR
Conditions to check
  • Frequency (DC vs 50/60 Hz vs 1 kHz) used for the spec
  • Input common-mode level and gain configuration
  • Whether the spec assumes perfectly matched external networks
  • Any CMRR variation across the input common-mode range
4
PSRR (+ and − supplies)
What it breaks
  • DC reading changes with supply ripple or load steps
  • Accuracy degrades when using switching regulators
  • “Works on bench supply, fails in system” outcomes
Common misreads
  • Reading PSRR at 1 kHz and assuming low-frequency is the same
  • Not separating PSRR+ and PSRR− on dual supplies
  • Ignoring output swing/load conditions tied to the spec
Conditions to check
  • Frequency used for PSRR (DC/100 Hz/1 kHz)
  • Supply voltage level and ripple amplitude during test
  • Output load and output swing conditions
  • Single-supply vs dual-supply definition used by the datasheet
5
Bias current & leakage
What it breaks
  • Large DC error when source impedance is high
  • Errors that worsen sharply at high temperature
  • Board contamination effects that look like “sensor drift”
Common misreads
  • Using typical IB instead of max IB over temperature
  • Assuming leakage is constant across input voltage
  • Ignoring PCB surface leakage and connector leakage
Conditions to check
  • IB max and its temperature range
  • Input voltage / common-mode conditions during the measurement
  • Any notes on input protection structures affecting leakage
  • Recommended board cleanliness/guarding assumptions
6
Noise (0.1–10 Hz + wideband)
What it breaks
  • Reading jitter that limits repeatability
  • Slow wander that looks like drift at short time scales
  • Noise floor that dominates after offset is calibrated out
Common misreads
  • Treating 0.1–10 Hz noise as a simple density integral
  • Using noise density at 1 kHz as the only noise indicator
  • Ignoring current noise when source impedance is high
Conditions to check
  • Whether 0.1–10 Hz is RMS or peak-to-peak and test time window
  • Noise density frequency point and spectrum shape assumptions
  • Effective bandwidth in the target system (filtering/averaging)
  • Voltage noise (en) and current noise (in) availability
Datasheet spec map for op amp DC accuracy Tag-style diagram mapping each DC accuracy spec to the test conditions that must be verified: temperature range, common-mode level, frequency, load, gain configuration, and bandwidth assumptions. Spec Conditions to verify Offset max vs typ temp range CM level load Drift endpoints curve type time base stress CMRR freq CM point gain mismatch PSRR low-freq PSRR+ / − ripple load Bias max over T input V protection cleanliness Rule: a spec without matching conditions cannot be safely used in a DC error budget.

Offset: where it comes from and how it turns into system error

Input offset voltage (VOS) behaves like a small DC source at the input. After the closed-loop gain is applied, it becomes a measurable output bias. In precision systems, offset is best treated as an input-referred error term that can be budgeted, verified, and separated from reference or ground shifts.

Minimal offset-to-error mapping
Output error
VOUT, error ≈ VOS · ACL
Input-referred view
VIN, equiv ≈ VOS
Range impact
%FS error ≈ VIN, equiv / FS range
Use max across temperature Check common-mode point Validate under real output swing
Scenario 1: Buffer
Dominant path
  • VIN, equiv ≈ VOS (input-referred)
  • Output shows a fixed DC bias
Common trap
  • Using typical VOS and ignoring max over temperature
  • Assuming near-rail input behaves the same as mid-rail
First checks
  • Short input to the reference point and record output bias
  • Repeat at the real common-mode operating level
Scenario 2: Gain stage
Dominant path
  • VOUT, error ≈ VOS · ACL
  • Offset scales with gain and becomes range-visible
Common trap
  • Room-temperature calibration assumed valid across temperature
  • Ignoring output swing / load conditions tied to the spec
First checks
  • Measure offset at the real gain and output swing limits
  • Compare results at multiple temperature points
Scenario 3: Shunt / bridge front-end
Dominant path
  • VOS adds to reference and ground shifts
  • Input network imbalance can look like offset
Common trap
  • Blaming the op amp for a reference/ground-related bias
  • Not checking input resistor matching assumptions
First checks
  • Verify the reference point and ground offset at the amplifier pins
  • Compare results after swapping to a known-good device
Input-referred offset error flow in a closed-loop op amp Block diagram showing a signal source feeding an op amp with a small Vos source at the input, producing an output offset; labels indicate input-referred and output-referred error and the role of closed-loop gain. Signal Vin Op amp Closed-loop Output Vout VOS Input-referred error Output offset ACL Treat Vos as an input-referred term; validate max specs at the real CM level and output swing.

Drift: temperature, time, stress, warm-up (and what “low drift” means)

Drift is not a single number. It is the combined result of temperature dependence, long-term aging, mechanical stress, board-level contamination, and thermal settling after power-up. “Low drift” only holds when the datasheet conditions match the operating range and when the board-level stress and leakage paths are controlled.

Three real-world drift forms to separate
Warm-up settling

Output slowly converges after power-up until thermal gradients stabilize.

Temperature drift

Offset changes with ambient and self-heating; curves may be non-linear.

Long-term drift

Slow baseline shift from aging, package/PCB stress, and leakage paths.

Drift source pyramid (with verification hooks)
1) Die / architecture dependence
  • Check drift over temperature endpoints, not only near 25°C.
  • Compare devices under identical bias and common-mode conditions.
2) Package stress and mounting
  • Run a thermal cycle and compare pre/post offset baselines.
  • Compare packages or footprints when µV-level stability is required.
3) PCB stress, humidity, contamination
  • Compare measurements before/after cleaning or drying.
  • Repeat at high humidity to expose leakage-driven baseline motion.
4) Environment and warm-up
  • Record output vs time after power-up to set a stabilization time.
  • Repeat with airflow or enclosure changes to quantify sensitivity.

When drift correlates strongly with temperature, a system can record temperature and apply a simple correction model. The correction approach should remain stable over time; otherwise drift must be reduced at the hardware and process level.

Drift decomposition: warm-up, temperature sweep, and long-term windows Minimal plots showing output versus time after power-up for warm-up, offset versus temperature for temperature drift, and baseline change over weeks for long-term drift, with labeled measurement windows. Warm-up window Temp sweep window Long-term window time out settling temp off non-linear weeks base aging / stress Separate windows: warm-up (minutes), temp sweep (°C), long-term (weeks) to avoid mixing drift with noise.

0.1–10 Hz noise: why it matters and how to read it correctly

Low-frequency noise is a hidden limiter for DC accuracy. Even when offset is small, 0.1–10 Hz noise can appear as slow reading wander and long-term repeatability loss. This specification must be interpreted as a time-window behavior, not as a single noise-density point and not as a simple replacement for integrating nV/√Hz values.

What it limits
  • Slow reading wander at low update rates
  • Repeatability after offset calibration
  • Stability over minutes, not milliseconds
What it is
  • A low-frequency window (0.1–10 Hz)
  • Strongly related to 1/f behavior
  • Reported as RMS or peak-to-peak
Common misreads
  • Treating it as noise density at 1 Hz
  • Comparing parts with different definitions
  • Assuming averaging removes it indefinitely
From 0.1–10 Hz noise to displayed reading jitter
What is seen
  • Slow wander
  • Minute-scale jitter
  • Repeatability floor
What sets it
  • 0.1–10 Hz window
  • Measurement time window
  • Update/averaging behavior
How to use it
  • Match definitions (RMS vs p-p)
  • Compare same window
  • Budget as slow-jitter limit
Same window RMS vs p-p Time window matters

Zero-drift and chopper amplifiers often reduce 1/f-related slow jitter, but real systems may still show ripple-like behavior from modulation residue. When comparing parts, low-frequency noise should be evaluated together with any ripple-related notes and with the real measurement update behavior.

0.1–10 Hz noise: frequency window and time-domain slow jitter Two-panel diagram: left shows a noise spectrum with 1/f rise and a highlighted 0.1–10 Hz window; right shows time-domain slow jitter with update markers. Frequency domain Time domain freq noise 0.1–10 Hz window 1/f white time out update slow jitter 0.1–10 Hz noise describes low-frequency behavior; averaging helps white noise first, not slow jitter indefinitely.

Wideband noise: en/in, integrating bandwidth, and when source impedance dominates

Wideband noise sets the fast jitter floor. Noise density numbers (nV/√Hz and pA/√Hz) become real RMS noise only after the system’s effective bandwidth is defined. Source impedance is the key divider: voltage noise can dominate with low impedance, while current noise converted through source impedance can dominate with high impedance.

en (voltage noise)
  • Acts like a series input voltage source
  • Dominates with low source impedance
  • Cannot be judged from one frequency point
in (current noise)
  • Acts like a parallel input current source
  • Converts to voltage through RSOURCE
  • Often dominates with high source impedance
Typical mistakes
  • Using only en and ignoring in
  • Using a 1 kHz point as “total noise”
  • Ignoring resistor thermal noise
3-step wideband noise budgeting
Step 1: Source impedance
  • Use Thevenin R at the input
  • Include bias networks
  • Include sensor output resistance
Step 2: Effective bandwidth
  • Analog RC and front-end limits
  • Sampling and hold behavior
  • Averaging reduces bandwidth
Step 3: RMS contributors
  • en term over bandwidth
  • in·RSOURCE term
  • R thermal noise term
Stop mistakes
  • Use in when RSOURCE is high
  • Use real system bandwidth, not a single-point density
  • Include resistor thermal noise as a baseline floor
Noise dominance regions versus source impedance Diagram with a horizontal axis of source impedance split into three colored regions: en-dominated, in·R dominated, and resistor thermal dominated. Simple icons represent voltage noise, current noise, and resistor noise. Source impedance shifts which term dominates: en, in·R, or resistor thermal noise. Rsource en dominant in·R dominant R thermal dominant en in R low high

Bias current & leakage: the silent DC error through source impedance

Bias current and leakage create DC error by converting picoamps or nanoamps into voltage across source impedance. In high-impedance systems, the I×R conversion can dominate the error budget, and temperature or humidity can amplify leakage dramatically. This chapter treats bias/leakage as a measurable, preventable error chain, separated into device, PCB surface, and connector/cable sources.

Minimal I×R error mapping (input-referred)
Bias / leakage current

Ibias, Ileak can be pA–nA and varies with conditions.

Source impedance

Rsource turns small currents into measurable DC offsets.

Input error

Verror ≈ I × Rsource

High-Z magnifies I×R Temperature can worsen leakage Humidity reveals PCB paths
High-impedance DC error checklist (three layers)
1) Device bias/leakage
  • Use max specs across temperature
  • Check input common-mode operating point
  • Compare input structures (FET vs chopper)
First check
Swap to a known-good device on the same board and compare the DC baseline.
2) PCB surface leakage
  • Flux residue and contamination create pA–nA paths
  • Humidity forms a conductive surface film
  • High-Z nodes need leakage control practices
First check
Compare readings before/after cleaning or drying; repeat under higher humidity.
3) Connector/cable leakage
  • Surface contamination on connectors becomes a leakage bridge
  • Moisture and handling can shift DC baselines
  • Long cables can add distributed leakage paths
First check
Replace the connector or shorten the cable and observe DC baseline sensitivity.

High-impedance applications such as pH and electrochemical probes, as well as photodiode front ends with sensitive input nodes, often fail DC accuracy targets when leakage paths dominate. In these cases, a lower-bias amplifier only helps after PCB and connector leakage are controlled to the same order of magnitude.

Leakage paths injecting error into a high-impedance input node Block diagram with a central high-Z input node fed by three leakage sources: device leakage, PCB surface leakage, and connector/cable leakage. The node feeds an op amp and produces a DC error at the output. High-Z node I × Rsource Op amp input DC error Device PCB surface Connector Guard / clean / dry Separate leakage layers: device, PCB surface, connector/cable. Fix the dominant layer before changing parts.

CMRR in practice: DC vs AC, and why board-level CMRR collapses

CMRR is not a single number. It is the conversion of common-mode change into differential error under a specific set of conditions. Board-level asymmetry can collapse effective CMRR even when the datasheet value is high. This chapter focuses on DC and low-frequency CMRR behavior driven by impedance imbalance, parasitic coupling, and asymmetric input protection networks.

Why board-level CMRR collapses (three drivers)
Imbalance (ΔR / ΔC)
  • DC CMRR is set by resistor symmetry
  • Low-frequency CMRR is set by capacitor symmetry
  • Protection/filters must match on both inputs
First checks
  • Verify both input paths have the same R and C values
  • Verify both inputs see the same bias return path
Parasitic coupling
  • Unequal parasitic C to ground breaks symmetry
  • Unequal routing coupling injects differential error
  • Low-frequency CMRR degrades with frequency
First checks
  • Compare input-to-ground parasitics near the pins
  • Check symmetry of the two traces and neighbors
Asymmetric protection
  • Clamp/limit paths differ between inputs
  • One side can enter conduction earlier
  • CM changes become DM error
First checks
  • Match clamp parts and series resistors on both inputs
  • Simplify the protection network and re-test CMRR

To separate device CMRR from board-level collapse, a common-mode stimulus should be applied equally to both inputs while the output is monitored for differential error. Starting from a symmetric, simplified input network and adding real-world protection and filtering back step-by-step quickly reveals which external asymmetry dominates the conversion.

Common-mode to differential conversion from small mismatch Two-panel comparison: ideal symmetric input network shows near-zero differential error, while a small mismatch in resistor or capacitor creates differential error at the output from the same common-mode input. Ideal symmetry Small mismatch CM input CM input R R C C DM error ≈ 0 R ΔR C ΔC CM → DM error Small ΔR/ΔC and asymmetric protection convert common-mode change into differential error.

PSRR: supply ripple becomes DC error (and why “typical PSRR” is not enough)

Supply ripple and supply noise can turn into output error when power-supply rejection is limited under real operating conditions. PSRR is frequency-dependent and condition-dependent, so a single “typical PSRR at 1 kHz” value rarely predicts DC accuracy. Low-frequency supply movement is often the most damaging because it appears as drift-like output error and directly corrupts measurement repeatability.

What PSRR really means
  • Supply change is converted into output error
  • PSRR depends on frequency and conditions
  • Low-frequency PSRR matters for DC accuracy
Supply cases to separate
  • Positive vs negative supply PSRR can differ
  • Single-supply: AVDD and ground movement matter
  • Ripple at pins is more relevant than at the regulator
Common misreads
  • Using only 1 kHz PSRR
  • Using typical instead of minimum
  • Ignoring gain / CM / load / swing conditions
Supply ripple → PSRR → output error → measurement error
1) Supply ripple
  • Identify low-frequency movement
  • Measure at amplifier pins
  • Separate ripple from DC droop
2) PSRR(f) conditions
  • Use low-frequency data
  • Use minimum across temperature
  • Match gain / CM / load / swing
3) Output error
  • Convert ripple through PSRR(f)
  • Track worst-case corners
  • Watch low-frequency dominance
4) Measurement error
  • Map to input-referred units
  • Separate guarantee vs typical
  • Record assumptions and tests
Use PSRR(f) Low frequency matters Typical is not a guarantee
Supply injection path and PSRR versus frequency Block diagram showing supply ripple injecting through an internal gain path into output error, plus a small PSRR(f) plot that slopes downward with frequency and highlights low frequency importance. Supply ripple AVDD / rails Internal path bias / gain Output error measurement shift PSRR(f) frequency PSRR LF degrades with f Low-frequency PSRR and minimum values matter most for DC accuracy; a single 1 kHz typical number is insufficient.

Error budgeting: turn specs into a DC accuracy guarantee

A DC accuracy “guarantee” requires turning specifications into a structured error budget under system conditions. The budget must separate worst-case guarantees from typical/RMS design estimates, and it must explicitly map datasheet conditions (gain, temperature, common-mode, output swing, load, frequency and bandwidth) to the real application environment.

DC accuracy budgeting template (copyable field list)
Guarantee (worst-case)
Offset (max)
Spec value • Datasheet condition • System condition • Use/Derate value
Drift × ΔT
Drift spec • Temperature window ΔT • Use hot/cold corners • Use/Derate value
Bias/leakage: I × R
Ibias (max) • Rsource (max) • Humidity/contamination assumptions • Use value
CMRR injection
ΔVCM (worst) • Effective CMRR under imbalance • Use value (input-referred)
PSRR injection
ΔVS (worst) • PSRR(f) at low frequency • Use minimum values • Use value
Noise limits
0.1–10 Hz slow jitter • Wideband RMS (bandwidth-defined) • Map to system units
Total (guarantee)
Conservative sum of worst-case structured terms + bounded noise assumptions
Design estimate (typical/RMS)
Typical offset & drift
Typical values with measured temperature correlation; record assumptions.
Noise RMS with real bandwidth
Define effective bandwidth; compute wideband RMS; keep 0.1–10 Hz as slow-jitter limit.
Injection terms with measured system conditions
Use measured ΔVCM and ΔVS; use effective CMRR/PSRR after board effects.
Total (estimate)
RMS combine random noise terms; track structured errors separately for calibration decisions.
Condition mapping rule
  • Specs cannot be used directly unless datasheet conditions match system gain, common-mode, output swing, load, frequency and bandwidth.
  • If conditions differ, derate or measure effective values and record them in the budget.
DC accuracy error budget structure with stacked contributors Two stacked-bar illustrations: one for worst-case guarantee and one for typical/RMS estimate. Each bar is divided into labeled segments such as offset, drift, bias, CMRR, PSRR, 0.1–10 Hz noise, and wideband noise, with a total error marker. Budget structure: stack contributors; separate guarantee (worst-case) from typical/RMS behavior. Worst-case stack Typical/RMS view Offset Drift Ib·R CMRR PSRR 0.1–10 Wideband Total Offset Drift Ib·R CMRR PSRR 0.1–10 Wideband Total

Applications (only accuracy-driven patterns)

Application patterns help prioritize DC accuracy error terms without turning this page into full system schematics. Each card below lists dominant contributors, fast verification actions, and selection notes that stay strictly within DC accuracy scope.

Bridge / Weigh scale / Pressure
Dominant error terms
  • Drift (temperature and warm-up)
  • 0.1–10 Hz noise (slow jitter)
  • Offset (max) as a guarantee bound
Verification actions
  • Temperature sweep: cold → hot → cold (check hysteresis)
  • Warm-up log: 0–30 min after power-up (baseline stability time)
  • 0.1–10 Hz stability: ≥60 s capture; compare different averaging times
Selection notes (examples)

Prioritize drift(max) and 0.1–10 Hz noise; require min specs and full test conditions. Example anchors: TI OPA189, TI OPA333, ADI ADA4528-2, ADI ADA4522-2.

Thermocouple / RTD AFE
Dominant error terms
  • Drift × ΔT (system temperature window)
  • Bias/leakage through source impedance
  • 0.1–10 Hz noise for “stable reading time”
Verification actions
  • Correlation: error vs board temperature (build a “drift ownership” trace)
  • Static log: ≥10 min baseline record (slow drift and wander)
  • Bias check: change Rsource and confirm I×R scaling
Selection notes (examples)

Use drift(max) and Ib(max) across temperature as budget inputs; treat 0.1–10 Hz as a stability limit. Example anchors: TI OPA189, TI OPA333, ADI ADA4528-2, ADI ADA4522-2.

High-Z probe / Electrochemistry
Dominant error terms
  • Bias/leakage (device + PCB + connector/cable)
  • Humidity/contamination sensitivity (board-level first)
  • Offset becomes dominant only at very small ranges
Verification actions
  • Leakage A/B: before/after cleaning and drying
  • Humidity step: repeat baseline under higher RH
  • Temperature corners: confirm Ib/leak growth at hot
Selection notes (examples)

Bias/leakage specs must include temperature and input common-mode conditions; require board-level leakage controls. Example anchors: ADI ADA4530-1, TI LMP7721.

Remote / long-line differential
Dominant error terms
  • CMRR under real imbalance (ΔR/ΔC/parasitics)
  • Input network matching (often the primary limiter)
  • PSRR and ground movement as secondary drivers
Verification actions
  • Common-mode injection with zero differential input
  • Mismatch sensitivity: introduce small ΔR/ΔC and re-test
  • Low-frequency supply/ground movement sweep
Selection notes (examples)

Require CMRR(min) with frequency/gain/common-mode conditions; verify effective CMRR after the input network. Example anchors: TI INA333, ADI AD8421.

Applications versus dominant DC accuracy error terms Matrix diagram mapping four applications to six DC accuracy error terms. Primary terms are highlighted strongly, secondary terms are lightly highlighted. Primary Secondary Application → error-term priority Offset Drift Bias CMRR PSRR Noise Bridge Thermo/RTD High-Z Long-line

IC selection logic (parameters → risks → questions to vendors)

DC accuracy selection should map parameters to failure symptoms, and symptoms to verification evidence. The checklists below are structured for procurement and design teams: field names are grouped by error term, and each field ties back to measurable risk.

Parameters → risks (symptom language)
Reading shifts with temperature
  • drift(max) and temperature window ΔT
  • warm-up behavior and stress sensitivity
  • long-term drift data (time domain)
Reading follows supply/ground movement
  • PSRR(min) at low frequency with conditions
  • output swing/load dependence of DC error
  • single-supply: AVDD and ground noise equivalence
Reading shifts with cable/common-mode
  • CMRR(min) with frequency/gain/CM point
  • input network matching sensitivity (ΔR/ΔC)
  • board-level parasitics and coupling dominance
High-Z baseline error or humidity sensitivity
  • Ib(max)/leakage across temperature and CM range
  • PCB surface leakage as first-order risk
  • connector/cable leakage and handling effects
Reading “never settles” (slow jitter)
  • 0.1–10 Hz noise (p-p) and measurement time
  • wideband RMS noise with effective bandwidth
  • typical vs minimum noise reporting
Selection field checklist (grouped by error term)
Offset
  • VOS(max) across temperature
  • Input CM range vs temperature (where offset changes)
  • DC error behavior vs output swing and load
Example anchors: OPA189, OPA333, ADA4528-2, ADA4522-2
Drift
  • drift(max) and the test temperature range
  • warm-up behavior (baseline stabilization time)
  • long-term drift data and reporting method
Example anchors: OPA189, ADA4528-2
Bias / leakage
  • IB(max) at 25°C and hot corners
  • Leakage vs input CM and protection structures
  • Guidance for board-level leakage control (guard/clean/dry)
Example anchors: ADA4530-1, LMP7721
CMRR
  • CMRR(min) with gain, frequency, and CM point
  • Low-frequency CMRR data (not only a single number)
  • External network matching sensitivity expectations
Example anchors: INA333, AD8421
PSRR
  • PSRR(min) at low frequency (10–100 Hz emphasis)
  • Separate +PSRR and −PSRR if dual-supply
  • Test conditions: output swing, load, gain, CM point
Example anchors: OPA189, ADA4528-2
Noise
  • 0.1–10 Hz noise (p-p) with stated conditions
  • Wideband noise with defined effective bandwidth
  • Noise vs temperature if available
Example anchors: OPA189, ADA4528-2, ADA4522-2
Vendor questions template (copy/paste)
1) Please provide MIN specs and exact test conditions: – Vos(max), drift(max), Ib(max), CMRR(min), PSRR(min), 0.1–10 Hz noise, wideband noise – Temperature range, gain, input common-mode point, output swing, load, bandwidth 2) Please provide low-frequency evidence: – PSRR(f) and CMRR(f) data around 10–100 Hz (or the lowest available) – Clarify whether “typical” curves represent guaranteed behavior 3) Please provide variability and time-domain information: – Lot-to-lot distribution or guardband guidance (if available) – Long-term drift reporting method and time window – Warm-up behavior after power-up (baseline stabilization time)
DC accuracy selection decision flow Flow diagram showing: application to dominant error terms, to key parameters, to vendor evidence, to verification plan, to shortlist. Each step is a rounded rectangle connected by arrows. Application → dominant errors → key fields → evidence → verification → shortlist Application use-case constraints Dominant errors drift / bias / CMRR Key fields min + conditions Vendor evidence LF curves / limits Verification plan temp / CM / supply Shortlist few candidates Key rule Use MIN specs and require test conditions; verify effective values after board-level effects. Candidates should shrink only after evidence and verification hooks are aligned to system conditions.

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FAQs (DC Accuracy)

Short, actionable answers for common DC-accuracy symptoms (offset, drift, bias/leakage, CMRR/PSRR, and low-frequency noise). This section is intentionally narrow to avoid expanding beyond DC accuracy.

Why does the reading drift for the first few minutes after power-up?
Early drift is usually warm-up and thermal settling rather than true long-term drift. Self-heating and board temperature gradients shift the baseline until equilibrium is reached. Do this first: log the baseline for 0–30 minutes and define a valid reading time after the curve flattens.
What is the practical difference between offset and 0.1–10 Hz noise?
Offset is a fixed DC shift; 0.1–10 Hz noise is slow random baseline wander that limits how stable the reading looks. Do this first: use offset(max) for guarantee budgeting, and use 0.1–10 Hz noise to set the averaging time needed for a stable display.
Why does “typical offset” look great but worst-case accuracy is poor?
Typical values describe a midpoint; accuracy guarantees are set by max/min over temperature and conditions. Worst-case stacks spread, operating point, and test-condition differences that a single typical number does not cover. Do this first: budget with max/min specs and confirm datasheet conditions match system conditions.
How much CMRR is “enough” for long cables and remote sensors?
Enough CMRR is determined by the expected common-mode movement and the allowed DC error after board-level imbalance. Effective CMRR is often limited by the input network (ΔR/ΔC/parasitics), not the headline IC number. Do this first: run a common-mode injection test with zero differential input and measure the output error.
Why does CMRR look good on paper but collapse on the PCB?
PCB imbalance and coupling convert common-mode into differential error and can dominate over intrinsic CMRR. Mismatched R/C, asymmetric protection, and routing parasitics are common causes. Do this first: enforce symmetry and quantify sensitivity by introducing a small controlled ΔR or ΔC and re-testing.
How can input bias current create a large error even with a “precision” op amp?
Bias current through source impedance produces an input-referred DC error that looks like offset. Even small IB becomes large when RSOURCE is large, and it may rise strongly with temperature. Do this first: compute the error using IB(max) and the maximum source impedance, then validate by changing RSOURCE.
When does board leakage dominate over amplifier bias current?
Board/connector leakage dominates when it reaches the same order as the amplifier input bias and injects comparable DC current into the node. Residues and humidity can create strong leakage variation that swamps IC specs. Do this first: perform before/after cleaning and drying tests, and repeat under higher humidity to confirm leakage sensitivity.
How should PSRR be evaluated for 50/60 Hz and slow supply variation?
PSRR must be checked at low frequency using minimum specs and correct conditions, because slow supply movement can map directly into DC error. Many “good PSRR” numbers are quoted at higher frequencies or as typical curves. Do this first: inject a small 50/60 Hz ripple (or slow step) on the supply and measure baseline movement at the output.
Is zero-drift/chopper always better for DC measurements?
Not always—zero-drift reduces offset and 1/f effects, but DC accuracy can still be limited by bias/leakage, CMRR/PSRR, and board leakage. Some systems may also be constrained by time-domain baseline behavior rather than headline offset. Do this first: validate baseline stability over time and temperature in the real chain (not only by reading the offset spec).
How to separate drift from low-frequency noise during testing?
Drift is repeatable and correlates with temperature/time; low-frequency noise is random wander that does not repeat the same way run-to-run. Do this first: run repeated baseline logs and compare them to logs under controlled temperature steps. A strong baseline–temperature correlation indicates drift; persistent non-repeating wander indicates low-frequency noise.
Why does touching the cable change the measured DC value?
Touching the cable can change leakage, charge, shielding reference, or coupling, shifting the baseline—especially with high-impedance inputs or weakly-defined return paths. Do this first: ensure a defined bias/return path, keep impedance controlled, and verify shielding/ground reference consistency. Quick test: swap cables and repeat with inputs replaced by a known resistor network to isolate cable effects.
What quick tests isolate whether the error is from op amp, PCB, or cabling?
Use swap-and-inject tests to separate IC limits from board/network and cable/environment effects. Do this first: (1) replace the source with a known low-impedance reference, (2) inject common-mode and supply ripple, (3) swap cable/connector assemblies. If the error persists with a known reference and no cable, suspect PCB/network; if it follows the cable, suspect cabling/leakage; if it tracks supply injection, suspect PSRR/grounding.
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