High-Speed / Latched Comparator: ns Delay, Jitter, and Latch Timing

Q: Why does propagation delay change a lot with small overdrive?

Propagation delay is highly nonlinear at low overdrive and slow dV/dt near the threshold. Budget timing at OD(min), reduce ringing/multi-crossing, and increase dV/dt at VTH with buffering or proper termination.

Q: How to estimate timing jitter from input noise and input slew?

Estimate jitter with σt ≈ σv/(dV/dt) using noise near VTH and the real slope at the comparator input. Keep σt within about 10% of the system time bin by increasing dV/dt and reducing threshold modulation.

Q: Why does a latched comparator sometimes “miss” the event near the LE/CLK edge?

The crossing can land inside the latch aperture or setup/hold unsafe window, especially with LE/CLK jitter or input ringing. Phase-sweep LE/CLK, then place the crossing outside (setup+hold)+margin.

Q: What setup/hold margin is practical for ns comparators in real boards?

Use worst-case setup/hold and add clock jitter, routing skew, and crossing time-walk. A practical rule is effective margin ≥ 2×(setup/hold) + 3σ(clock/route/time-walk).

Q: Why does jitter get worse after adding input clamps/TVS?

Clamp capacitance can reduce dV/dt and introduce amplitude-dependent time-walk and ringing. Treat it as timing-critical if dV/dt drops >30% or if ringing causes multiple crossings; use low-C devices and damping/partitioned protection.

Q: How to tell if the scope/probe is creating the jitter you see?

Compare a ground spring vs long ground lead and passive vs active probes with fixed bandwidth/trigger settings. If jitter changes >25–30% from probing alone, the measurement is limiting and probing/loop area must be improved.

Q: When should a preamp/buffer be added before a high-speed comparator?

Add a buffer when σt(computed) exceeds ~10% of budget or when RTH×Cin consumes >10% of allowable edge-transition time at VTH. A preamp increases dV/dt and stabilizes OD(min) under real loading and kickback.

Q: Why does VICR near rails cause unpredictable switching timing?

Input-stage crossover and reduced headroom can change gain and delay behavior near rails. Validate at common-mode corners and treat the crossover/not-guaranteed region as high risk; shift bias or choose a device characterized for that VICR corner.

Q: Push-pull output looks clean, but FPGA capture still jitters—why?

Receiver threshold noise, ground bounce, and ringing at the FPGA pin can dominate timing. Measure at the receiver pin, verify termination and return paths, and consider differential signaling if digital activity modulates the capture timing.

Q: How to reduce kickback-induced errors in high-impedance sources?

Kickback current through high Thevenin resistance creates voltage steps and extra crossings. Lower RTH with buffering/driver strength and add Rseries near the comparator input to limit injection and damp ringing.

← Back to:Comparators & Schmitt Triggers

This page helps turn a “fast comparator” into a timing-accurate discriminator by budgeting propagation delay, jitter, and latch timing from real overdrive and edge slew. It shows how to build a repeatable measurement flow and a practical timing budget so timestamp error is predictable, not a surprise.

What this page solves (and what it does not)

This page helps convert “fast but unstable” switching into “fast and time-consistent” edges for timing chains. It focuses on delay vs overdrive, edge jitter / time-walk, and latch timing (setup/hold)—with practical measurement and budgeting methods.

Typical cases that truly need high-speed / latched comparators

TDC start/stop edges: small overdrive and tight timestamp repeatability. The main risks are time-walk (amplitude-to-time shift) and noise-to-time jitter.
ToF / first-echo pick-off: event amplitude varies, but the system must “decide” at a controlled instant. The key risk is enable/latch timing margin near the threshold crossing.
Squaring slow/noisy signals: low dV/dt turns voltage noise into timing uncertainty. The key lever is increasing effective slope (or choosing a more suitable bucket).

What this page provides (practical deliverables)

Timing budget template: tpd, dispersion, jitter/time-walk, and latch margin in one checklist.
Delay vs overdrive method: how to budget the worst case from datasheet curves (not “typical tpd”).
Latch timing rules: how to keep threshold crossing away from the latch edge (setup/hold margin strategy).
Measurement checklist: how to measure delay/jitter without probe-trigger artifacts.

Common mistakes that break timing repeatability

Using “typical tpd” as the budget: always budget using tpd vs overdrive at the minimum overdrive.
Ignoring dispersion: include temperature/VDD/lot spread as a separate timing term (it is not “noise”).
Forgetting dV/dt: if the input slope is small, voltage noise converts into large time jitter; fix slope first, then optimize parts.
Trusting a scope screenshot: clean-looking edges can still carry jitter from threshold modulation and ground bounce—validate with a repeatable method.

High-Speed vs Latched vs Regenerative: choosing the right bucket

These three buckets can look similar on a bench, but they behave very differently in timing chains. The choice should be driven by timing determinism (continuous vs sampled decision), clock/enable constraints, and the acceptable trade between power, latency, and threshold behavior.

Behavior-level differences (what matters in real timing chains)

High-speed (continuous): asynchronous decision; propagation delay depends on overdrive and input slope. Best when the system needs a real-time comparator output (no sampling instant).
Latched comparator: decision is captured at a controlled instant (LE/CLK/EN). Adds setup/hold margin and a defined output update time. Best when the system needs a “snapshot” decision for timing/ToF gating.
Regenerative (clocked dynamic): timing is clock-defined and naturally fits sampled systems (e.g., ADC/TDC front-ends). Internal details belong to the dedicated regenerative page.

Decision tree (fast routing without mixing page scopes)

Need a fixed sampling instant (capture the decision at a known time)? → choose Latched.
Need continuous asynchronous compare (works without a sampling clock)? → choose High-speed continuous.
A system clock is available and the front-end can be clocked dynamic? → route to Regenerative.
The main problem is slow ramps / debouncing / logic cleanup? → route to Schmitt Triggers (not covered here).
The main requirement is absolute threshold accuracy (offset/drift dominated)? → route to Precision comparators (not covered here).

Scope boundaries (to avoid cross-page overlap)

Regenerative internal mechanisms and dynamic front-end details belong to the Regenerative sub-page.
Debounce, chatter control, and hysteresis calculation belong to Design Hooks and Schmitt Triggers.
Offset/drift-driven absolute threshold accuracy belongs to the Precision comparator sub-page.

Internal signal path: preamp → decision core → output stage (conceptual)

A high-speed comparator can be treated as a short signal chain with measurable responsibilities at each stage. This viewpoint makes timing instability debuggable: input sensitivity and delay dispersion typically originate near the front-end, while output edge integrity is often set by the driver and the load return path.

What each stage “owns” (measurable outcomes)

Preamp / limiter: sets input sensitivity under small overdrive and controls how strongly input noise converts into timing spread. Dominant symptoms: tpd growth at low overdrive and jitter on slow ramps.
Decision core: resolves near-threshold differences into a logic decision. Dominant symptoms: deterministic timing shifts when supply/ground is modulated by switching activity.
Output stage: drives the outside world and defines edge integrity at the receiving threshold. Dominant symptoms: ringing/overshoot, false toggles, and capture variability driven by load + return path.

Dominant error source mapping (symptom → likely cause → quick check)

Small-overdrive slowdown: tpd increases sharply at minimum overdrive → front-end sensitivity / insufficient effective gain near threshold → validate by measuring tpd at two overdrives (small vs large); large separation indicates a front-end-dominated regime.
Jitter tracks input slope: slower edge produces much larger timing spread → noise-to-time conversion dominated by dV/dt near VTH → validate by increasing slope (stronger driver, preamp, or larger amplitude) and confirming jitter drops accordingly.
Jitter correlates with digital activity: timing varies with switching bursts → supply bounce / ground bounce modulates the decision threshold → validate by changing switching patterns or isolating supplies and checking whether the timing histogram shifts.
Edge looks fast but capture varies: different probes/loads change measured timing → output load coupling / ringing and return-path sensitivity → validate by reducing load capacitance, adding near-source damping, and keeping return loops short.

Critical reminder: clean edges do not guarantee low decision jitter

A fast 10–90% rise time on the output can coexist with large threshold-crossing variation at the receiver. Verify timing at the actual decision threshold used by the next stage.
If jitter changes significantly when the probe/ground lead changes, the measurement chain or return-path coupling is dominating the result.

Propagation delay: overdrive, slew rate, and delay dispersion

Propagation delay is not a single number. It changes with overdrive and with the effective input slope near the switching threshold. In timing chains, the key is budgeting the worst-case delay and its dispersion across temperature, supply, and process.

Three facts that govern delay in real designs

Overdrive sets speed: smaller overdrive typically produces a much larger delay.
Slew rate changes the effective overdrive: slow ramps introduce amplitude-to-time variation (time-walk).
Dispersion is a budget term: temperature/VDD/process spread shifts delay even at the same overdrive.

Budgeting method (action-oriented)

Define the minimum overdrive at the system corner: use worst-case signal amplitude and expected threshold uncertainty. Treat this minimum overdrive as the lookup point for delay.
Use the datasheet curve (tpd vs overdrive) and pick the worst-case point: avoid typical large-signal values. If curves are given for multiple supplies/temperatures, budget the slowest curve.
If the input is a slow ramp or small-signal edge, include time-walk: the threshold crossing time shifts with amplitude and slope. If time-walk dominates, improving dV/dt near VTH usually reduces the error more effectively than chasing a smaller typical tpd.
Validate with a two-point bench check: measure tpd at two overdrives (large and near-minimum) using the same fixture. A large delta confirms overdrive-dominated delay and helps calibrate the budget.

The most common budgeting mistake

Using large-signal typical propagation delay for ToF/TDC timing budgets usually fails. Timing chains must budget delay at minimum overdrive and include dispersion.

Timing uncertainty: edge jitter, noise-to-time conversion, and time-walk

In timing chains, “fast” is not enough: the decision instant must be repeatable. Timing uncertainty typically comes from three sources: input-referred noise, threshold uncertainty (offset/drift/common-mode sensitivity), and supply/ground-induced threshold modulation. The most practical way to budget jitter is to convert voltage uncertainty into time uncertainty around the switching threshold.

Three dominant contributors (what they look like on the bench)

Input-referred noise (σv): widens the timing histogram. It becomes severe when the input slope near VTH is small (slow ramps or small overdrive).
Threshold uncertainty (ΔVTH): shifts the mean decision time across temperature, supply, and common-mode conditions. Treat it as an equivalent voltage error at the threshold.
Supply/ground modulation: creates activity-correlated timing shifts (deterministic components), often changing with digital switching bursts, load steps, or return-path coupling.

Actionable budgeting (voltage → time)

Convert noise to time jitter at the threshold: use σt ≈ σv / (dV/dt) with dV/dt taken near VTH (the real slope at the crossing).
Improve dV/dt first: increasing the slope near VTH usually reduces σt more effectively than chasing a smaller typical propagation delay. Practical levers include stronger edges, preamp/limiting, and avoiding excessive input RC that flattens the crossing region.
Treat offset + drift as threshold voltage error: convert ΔVTH into time error using ΔtTH ≈ ΔVTH / (dV/dt). This term often shows up as a slow mean shift rather than purely random spread.
Separate random jitter vs deterministic time-walk: random jitter mainly widens the distribution; time-walk shifts the mean decision time with amplitude/slope. A quick check is to sweep input amplitude (or slope) and watch whether the mean crossing time moves.

If measured jitter increases, remove these traps first

Probe/ground coupling: use a short ground spring and consistent reference points; long ground leads can inject edge-dependent noise.
Trigger artifacts: avoid relying on single-shot screenshots; use a repeatable timing reference and histogram-based statistics.
Supply noise injection: change switching activity (or load steps) and check whether timing shifts are correlated.

Latch/Enable timing: aperture, setup/hold, metastability, and bubble errors

A latch adds timing determinism by capturing the decision at a controlled instant. The trade-off is a set of timing constraints: aperture, setup/hold, metastability risk, and an output update time. The goal is to budget these constraints without relying on internal latch implementation details.

What a latch changes (value and cost)

Value: captures the decision at a defined time, simplifying alignment and gating in ToF/TDC chains.
Cost: introduces setup/hold margins, metastability risk near the latch edge, and a finite Q update time.

Budgeting method (engineering steps)

Treat LE/CLK as a sampling window: define an aperture where the input must be valid and stable for a deterministic decision.
Budget setup/hold with worst-case datasheet values: keep the input threshold crossing away from the latch edge by at least setup(worst) + hold(worst) + guardband. Guardband should include input jitter, LE edge jitter, skew, and supply-induced threshold modulation.
Handle metastability with system tactics: use downstream synchronization (two-flop), allow more resolving time when possible, and reduce correlated threshold modulation by clean supply/return paths.
Interpret “bubble” or sporadic wrong decisions as margin failure: first increase timing margin (move crossing away from LE edge), then apply downstream validation or filtering if required by the system.

Incorrect use to avoid (scope boundary)

Using a latch as a debounce/chatter fix is a category error. Debouncing and slow-ramp multi-toggling belong to Schmitt/RC and design-hook methods, not to latch timing.

Input interface for ns comparators: impedance, kickback, clamps, and VICR traps

For ns-class comparators, the input interface often dominates the real-world timing outcome. Excess source impedance, reflections, input kickback, and protection capacitance can flatten the slope near the threshold and amplify time uncertainty. In addition, operating near input common-mode limits can introduce abrupt crossover behavior that breaks “rail-to-rail assumptions.”

The real enemies at the input (timing symptoms)

High source impedance: slows the threshold crossing (lower dV/dt), increasing jitter and time-walk.
Trace reflections: ringing near VTH can create double-triggering and inconsistent crossing time.
Kickback / injection: short disturbance pulses can feed back into the source and perturb the crossing instant.
Clamp/TVS capacitance: reduces bandwidth and flattens edges, often making amplitude-related time-walk worse.
VICR near rails: crossover behavior can change delay and sensitivity abruptly; “RR” must be verified, not assumed.

Actions and checks (threshold-oriented)

If source impedance is high: expect slower crossing and higher jitter/time-walk. Action: reduce Thevenin R (lower divider values) or add a front-end buffer so the slope near VTH is preserved.
If the trace is long relative to the edge: treat it as a transmission line. Action: add damping/termination and place the series resistor close to the comparator input (or terminate at the source, depending on the driver).
If protection is required: clamp/TVS capacitance can dominate timing. Action: choose low-capacitance parts and use staged protection (strong protection at the connector, light/low-C near the comparator).
If VICR is close to a rail: do not assume “rail-to-rail.” Action: verify datasheet crossover/VICR behavior under the intended overdrive and common-mode conditions.

A common trap that guarantees slow and jittery results

Feeding a ns comparator through a multimeter-style high-resistance divider (tens of kΩ to MΩ) typically destroys dV/dt near the threshold and amplifies kickback sensitivity, producing slow, noisy, and inconsistent timing.

Output stage & logic interfacing: edge integrity, loading, and level domains

In ns timing chains, the output is part of a system link: loading, return paths, and receiver thresholds decide whether a “fast edge” turns into a repeatable capture instant. This section focuses on edge integrity and timing determinism at the logic/FPGA/TDC input, rather than on a comprehensive output-type catalog.

Output timing is a link problem, not a pin problem

Load shapes the edge: Cload and routing determine overshoot/ringing and the slope at the receiver threshold.
Return path sets the reference: ground bounce shifts the effective threshold seen by the receiver.
Receiver threshold amplifies jitter: a noisy/slow transition at the receiver can widen the capture time distribution.

Actions that improve edge integrity and capture determinism

If loading is heavy: slower edges increase time uncertainty at the receiver. Action: reduce Cload, shorten routes, add a buffer, or add near-source damping (series resistor) to control ringing.
If the receiver threshold is noisy or mismatched: the same edge can produce different capture instants. Action: match logic levels and use a cleaner interface strategy when needed (buffer/level shift, controlled threshold input).
If ground bounce is present: reference movement creates deterministic timing shifts. Action: tighten return paths, keep high di/dt loops away from the comparator/receiver reference, and ensure local decoupling is effective.

When edges look fast but the system still jitters

A fast-looking waveform at the comparator pin does not guarantee stable timing at the receiver. The capture instant is set at the receiver threshold, and ground bounce or receiver noise can widen the timing distribution even when the edge appears “clean” on a scope.

Practical timing budget: from input slope to timestamp error

A usable timing budget turns datasheet plots and bench measurements into a repeatable template. The goal is to decompose timestamp error into a set of fillable terms so timing no longer depends on “typical” delay numbers or intuition. A practical template is: Total timestamp error = noise-to-time jitter + threshold-to-time + tpd dispersion + latch margin + measurement uncertainty.

A reusable template (what to add up)

Noise-to-time jitter: σt_noise from σv and dV/dt around VTH.
Threshold-to-time: Δt_th from ΔVTH and dV/dt (offset/drift/common-mode sensitivity folded into ΔVTH).
Delay dispersion: Δt_disp from tpd vs overdrive, supply, temperature, and lot spread.
Latch margin: Δt_latch from aperture + setup/hold + metastability guardband + skew.
Measurement chain: Δt_meas from trigger/reference jitter, probing, fixtures, and bandwidth limitations.

Budget fields (and how to obtain each term)

dV/dt @ VTH (input slope)

Get it from: measurement at the threshold region (real waveform). Use worst-case: smallest amplitude / slowest edge / worst load.

σv_equiv (voltage uncertainty near VTH)

Get it from: bench estimate/measurement of noise near VTH, or conservative allocation. Use worst-case: maximum bandwidth/noise mode.

σt_noise ≈ σv / (dV/dt)

Get it from: compute using σv_equiv and dV/dt@VTH. Use worst-case: max σv with min dV/dt.

ΔVTH (threshold uncertainty)

Get it from: datasheet worst-case offset/drift and any stated common-mode sensitivity. Use worst-case: temperature endpoints and VICR corners.

Δt_th ≈ ΔVTH / (dV/dt)

Get it from: compute using ΔVTH and dV/dt@VTH. Use worst-case: max ΔVTH with min dV/dt.

Δt_disp (tpd dispersion / spread)

Get it from: datasheet tpd vs overdrive curves and min/max specs; optionally lot statistics. Use worst-case: smallest overdrive + worst VDD/temp.

Δt_latch (aperture + setup/hold + guardband)

Get it from: datasheet setup/hold/aperture + system LE jitter + skew allocation. Use worst-case: max skew + worst setup/hold.

Δt_meas (measurement chain uncertainty)

Get it from: trigger/reference jitter, probing/fixtures, and bandwidth limits. Use worst-case: longest ground loops and noisiest trigger path.

The most common missing term

Probe/fixture/trigger jitter is frequently treated as zero and later “discovered” as unexplained system error. Always allocate a Δt_meas term and validate it by changing probing, triggering, and bandwidth settings.

Measurement & validation: how to measure delay and jitter without lying to yourself

Measurement must match the definition used by the system: delay is a time difference between a defined input crossing and a defined receiver crossing. Jitter is a distribution of crossing times, not a single screenshot. Reliable results require controlled stimulus (overdrive and slope), a clean reference/trigger path, and probing that does not inject its own ringing or ground movement.

Definitions that prevent silent mistakes

Delay reference: use the input crossing at the intended threshold (VTH), not an arbitrary “50%” point.
Receiver truth: the effective capture instant is set at the receiver threshold, not at a convenient probe point.
Jitter meaning: report a distribution (σ or percentiles) from repeated events.

Minimal reproducible workflow (setup → stimulus → capture → compute → checks)

Setup: define trigger/reference path and probe points. Keep return paths short and consistent.
Stimulus: control overdrive and record dV/dt around VTH. Avoid VICR corners unless they are part of the intended operating range.
Capture: collect repeated events and timestamp both the input crossing (at VTH) and the receiver-side crossing.
Compute: extract mean delay, delay spread (dispersion), jitter distribution, and time-walk (mean shift vs amplitude/slope).
Sanity checks: vary bandwidth/trigger/probing and confirm results follow physical expectations (no “magic improvements” from filtering).

If jitter looks “too small”, suspect the setup first

Bandwidth limitation: insufficient bandwidth can smooth edges and hide real crossing-time spread.
Trigger conditioning: trigger jitter or filtering can “average out” variations and under-report jitter.
Ground/probing artifacts: long ground leads and fixture loops can inject ringing and distort the crossing definition.

Engineering checklist: layout, decoupling, return paths, and isolation from digital trash

Ns comparators fail in predictable ways on real boards: input symmetry is broken, return currents detour through noisy paths, and output switching lifts the local reference so the effective threshold moves. The checklist below is designed for layout reviews and pre-bring-up validation to protect timing determinism (delay spread and jitter) under worst-case activity.

What this checklist protects

Stable crossing: preserve slope and symmetry at the inputs around the intended threshold.
Stable reference: keep comparator ground and supply from moving with digital or output return currents.
Repeatable capture: prevent coupling from output switching or nearby digital trash into the input reference region.

Layout review checklist (copy-ready)

Must-have

Inputs are short, direct, and do not cross plane splits or stitching gaps.
Input symmetry is preserved (routing length and environment are matched for differential; reference is consistent for single-ended).
Input return currents have a continuous reference plane directly under the input path.
Local decoupling is placed at the comparator supply pins with a minimal loop (VDD → C → GND → pin).
Threshold-related bias/reference networks are kept away from high di/dt digital and output return paths.
Output return currents do not share the input reference region around the comparator pins.

High-risk (review twice)

Output switching current loops are verified (no “hidden” return path through input ground reference).
Inputs are not routed next to clocks, fast digital buses, or switching nodes.
Clamp/TVS devices near the comparator are checked for capacitance impact on timing and ringing.
Operation near VICR limits is validated (crossover behavior is not assumed to be benign).
Latch/LE/CLK lines are routed with controlled return paths and do not couple into the input threshold region.

Optional optimizations

Guard/shield structures are used around sensitive input nodes with a clean return strategy.
Analog threshold region and noisy digital region are physically partitioned with controlled current convergence.
Damping resistors are positioned intentionally (near the sensitive node when reflection control is needed).
Local supply filtering is applied only when it does not create a large dynamic impedance at ns edges.

Verification hooks (bring-up tests)

Probe A/B loop check: short ground spring vs long ground lead should not radically change jitter.
Digital activity injection: toggle nearby IO/clocks and observe whether delay/jitter shifts.
Supply-noise sensitivity: vary decoupling/return placement and compare delay spread across conditions.
Threshold ringing check: confirm no multi-crossing near VTH under worst-case stimulus.
Latch phase sweep: sweep LE/CLK phase relative to crossing and map the unsafe window.

Typical failures that widen delay spread and jitter

Input symmetry is broken (one side detours, different reference environment, or crossing a split plane).
Return current crosses a plane gap so the reference shifts under digital switching.
Output return current flows through the input reference region and modulates the effective threshold.

Applications (recipes) for High-Speed / Latched Comparators

The recipes below are specialized for ns-class timing chains and latched decision points. Each recipe uses the same template: Goal → Topology → Key specs → Guardrails → Test, so routes can be compared quickly and validated consistently.

Recipe set (ns / latched-focused)

ToF / Ultrasound first-echo pick-off (gated + latched)

Goal: capture the first valid echo timestamp with low jitter and no false hits.
Topology: preamp → high-speed comparator → gate/latch → TDC/FPGA.
Key specs: jitter, dispersion, latch timing (aperture/setup/hold), min overdrive.
Guardrails: keep crossing away from the gate edge; preserve dV/dt at VTH; keep output return out of input reference.
Test: sweep echo amplitude and gate timing; log hit-rate and timestamp distribution.

TDC start/stop discriminator (time-walk controlled)

Goal: convert analog events into stable start/stop timestamps under amplitude variation.
Topology: input conditioning → comparator → optional latch → TDC capture.
Key specs: time-walk vs amplitude, dV/dt at VTH, dispersion under small overdrive.
Guardrails: budget Δt_walk explicitly; avoid high source impedance; control reflections and ringing near VTH.
Test: amplitude sweep + slope sweep; extract mean shift and jitter distribution.

Clock squaring / pulse cleanup (edge determinism)

Goal: create a repeatable digital edge from a noisy or slow analog transition.
Topology: conditioner/limiter → high-speed comparator → buffer/level → receiver.
Key specs: jitter at receiver threshold, output loading sensitivity, supply/ground modulation sensitivity.
Guardrails: prioritize dV/dt at VTH; limit output load; control return paths to prevent ground bounce.
Test: vary output load and digital activity; compare edge-timing distribution at the receiver.

Fast OCP/OVP cutoff (glitch immunity + fault latch)

Goal: trigger fast protection without false trips and hold the fault state deterministically.
Topology: sense → filter/blanking → comparator → latch → gate driver/eFuse logic.
Key specs: min overdrive behavior, dispersion under noise, latch timing margin, input clamp impact.
Guardrails: avoid using latch as a debouncer; stage protection to avoid large input capacitance at the comparator.
Test: inject controlled glitches and noise; verify trip time and false-trip rate.

Encoder edge shaping (high-speed + EMI-tough)

Goal: produce stable edges from long cables or noisy sensors with minimal timing spread.
Topology: cable clamp/termination → comparator → buffer/level → counter/decoder.
Key specs: input interface sensitivity (kickback/termination), receiver threshold stability, output return control.
Guardrails: treat the line as a transmission path; avoid high-R dividers; route returns to keep the threshold reference quiet.
Test: cable length sweep + EMI injection; measure false edges and timing spread.

IC selection logic

High-speed and latched comparators must be selected with a system timing budget in mind. A usable selection flow is: fields → risk mapping → RFQ template. The goal is to avoid designs that look fast on “typical tpd” but fail under small overdrive, slow slopes, noisy returns, or latch timing corners.

A) Minimum fields for high-speed / latched comparators

tpd vs overdrive curve + minimum overdrive conditions

Why: tpd is not a constant; small overdrive can dominate timing error.
Action: budget at overdrive = worst-case minimum and verify the stated test conditions.

Delay dispersion (VDD / temperature / lot spread)

Why: dispersion becomes timestamp spread even if “typical tpd” looks great.
Action: demand corner numbers (min/typ/max) or curves, not a single typical point.

Input-referred noise (for jitter conversion)

Why: voltage noise near VTH becomes time jitter through slope.
Action: convert with σt ≈ σv / (dV/dt) using the real dV/dt at VTH.

Latch timing: setup/hold, aperture, LE/CLK → Q update delay

Why: latch adds deterministic sampling, but introduces setup/hold windows and output update latency.
Action: budget worst-case setup/hold and keep the crossing away from the latch edge.

VICR + rail crossover behavior

Why: near-rail behavior can change abruptly; assumptions about “RR” can fail.
Action: validate at VICR corners with the intended common-mode and overdrive.

Output standard + logic levels + drive vs load

Why: edge integrity at the receiver threshold sets real timing determinism.
Action: match the output domain (LVDS/CML/PECL/CMOS) and plan termination + load.

Package & pin symmetry (parasitics + layout feasibility)

Why: parasitics and asymmetry directly widen dispersion and jitter on real boards.
Action: prefer layouts that preserve symmetry and keep input loops short and clean.

ESD/clamps and input capacitance impact (high-speed penalty)

Why: clamp capacitance and protection placement can slow the crossing and increase time-walk.
Action: quantify input C and validate with the real source impedance and edge rate.

B) Risk mapping: scenario → what to prioritize

Small overdrive (ToF / TDC)

Prioritize: tpd@OD=min, dispersion, input noise → σt.

Slow slope or high source impedance

Prioritize: dV/dt@VTH, input C / clamp loading, front-end buffering.

Latched sampling (fixed decision instant)

Prioritize: setup/hold, aperture, LE/CLK jitter + skew.

Receiver-domain timing (FPGA/TDC capture)

Prioritize: output standard, termination + load, return-path control.

C) RFQ template (ask suppliers for usable, budget-ready data)

Provide worst-case tpd at overdrive = XX mV, including temperature and VDD corners (not only typical).
Provide the measurement conditions for delay/dispersion/jitter: input slew rate, overdrive range, threshold definition, bandwidth, load and termination.
Provide dispersion (definition + min/typ/max or curves) across VDD and temperature, and clarify if lot-to-lot variation is characterized.
If latch/enable exists, provide setup/hold/aperture and LE/CLK → Q update delay at worst corner, including any constraints on pulse width or duty cycle.
Provide VICR and crossover behavior near rails under the intended common-mode, and specify any regions with degraded or undefined behavior.

Example part numbers to evaluate (verify outputs and latch pins in the datasheet)

These are common families used in ns timing chains. Use them as starting points for the field checklist above, not as a universal recommendation.

TI examples

TLV3901 • TLV3801 / TLV3802 • TLV3604 / TLV3605 / TLV3607 • LMH7322

Analog Devices examples

ADCMP572 / ADCMP573 • ADCMP580 / ADCMP581 / ADCMP582 • ADCMP561 / ADCMP562 • ADCMP566 • AD8465

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FAQs – High-Speed / Latched Comparator

Short, actionable answers for ns timing chains. Each FAQ uses the same structure: Symptom / Likely causes (Top3) / Quick checks / Threshold / Action / Avoid.

Why does propagation delay change a lot with small overdrive?

Symptom

Delay (tpd) increases sharply and becomes unstable when the input only barely crosses the threshold.

Likely causes (Top3)

Operating in the low-overdrive region (tpd vs OD is highly nonlinear).
Low slope at VTH (slow dV/dt increases time-walk and sensitivity to noise).
Ringing/multiple crossings near VTH (reflection or clamp capacitance).

Quick checks

Compute worst-case overdrive at the decision point: OD = Vin_peak − VTH (at VTH crossing).
Compare tpd at two OD levels (e.g., 2× amplitude) to see if tpd shifts strongly.
Check the waveform near VTH for ringing or repeated crossings.

Threshold

Treat the regime as “small overdrive” when OD(min) < 5–10× σv (input RMS noise near VTH), or when a 2× OD change shifts measured tpd by >30%.

Action

Increase OD at the decision point (gain, lower threshold, or better coupling).
Increase dV/dt at VTH (preamp/limiter, reduce source impedance, control reflections).
Damp ringing near the comparator input (Rseries near the pin, proper termination).

Avoid

Do not budget timing using “large-signal tpd (typ)” when the real system OD is small.

How to estimate timing jitter from input noise and input slew?

Symptom

Timestamp spread grows when the edge is slower or when noise near the threshold is higher.

Likely causes (Top3)

Higher input-referred noise (σv) at the decision node.
Lower slope at threshold (dV/dt) due to loading or bandwidth limits.
Threshold modulation from supply/ground bounce coupling into the input reference.

Quick checks

Measure dV/dt at the crossing point (use the local waveform at the comparator input).
Estimate σv at VTH using the intended bandwidth (or input-referred noise spec + bandwidth).
Check if jitter correlates with digital activity (clock bursts, IO toggling).

Threshold

Use σt ≈ σv / (dV/dt). A practical budget rule is σt ≤ 0.1× the system time bin (or ≤ 10% of the total timing budget).

Action

Increase dV/dt at VTH (preamp/limiter, reduce source impedance, terminate long lines).
Reduce σv at the decision node (clean supply/ground, filter or limit noise sources).
Prevent threshold modulation (tight decoupling loop, controlled return paths).

Avoid

Do not chase “lower tpd” if dV/dt at VTH is the dominant jitter limiter.

Why does a latched comparator sometimes “miss” the event near the LE/CLK edge?

Symptom

The event is present at the input but the latched output does not update or updates inconsistently.

Likely causes (Top3)

Crossing occurs inside the latch aperture / setup-hold unsafe window.
LE/CLK edge jitter or skew moves the sampling instant into the unsafe window.
Input ringing causes multiple crossings near the sampling moment.

Quick checks

Phase-sweep LE/CLK relative to the crossing and record “miss rate”.
Measure LE/CLK edge integrity and local return path (ground bounce).
Check for ringing at the input around VTH at the latch moment.

Threshold

Keep the crossing at least (setup + hold) + margin away from the LE/CLK edge. A practical margin is ≥ 3× (LE/CLK jitter + skew + routing uncertainty).

Action

Move LE/CLK so the crossing lands in a safe region (use phase sweep data).
Reduce ringing and multi-crossing (termination, damping, cleaner stimulus).
Improve LE/CLK return paths and reduce clock-edge noise coupling.

Avoid

Do not use latch/enable as a debouncer; the fix is timing margin and clean crossings.

What setup/hold margin is practical for ns comparators in real boards?

Symptom

Even with “meeting setup/hold on paper,” occasional capture errors appear on the bench.

Likely causes (Top3)

Clock jitter and routing skew were not included in the margin.
Input time-walk moves the crossing closer to the latch edge under amplitude variation.
Ground bounce shifts the effective threshold or latch timing instant.

Quick checks

Measure LE/CLK edge jitter at the comparator pins (not only at the source).
Sweep input amplitude and observe crossing-time movement (time-walk).
Toggle nearby IO/clocks and check if the unsafe window widens.

Threshold

A practical rule is effective margin ≥ 2× (worst-case setup/hold) plus 3σ of (LE jitter + skew + crossing time-walk).

Action

Budget using worst-case setup/hold and add clock + routing + time-walk terms explicitly.
Increase dV/dt at VTH to reduce time-walk and jitter (preamp/termination).
Improve return paths to reduce ground-bounce timing modulation.

Avoid

Do not assume “datasheet setup/hold” is sufficient without adding system jitter, skew, and time-walk.

Why does jitter get worse after adding input clamps/TVS?

Symptom

Timing spread increases after adding protection devices even though the waveform “still crosses threshold.”

Likely causes (Top3)

Added capacitance reduces dV/dt at VTH (σt increases).
Nonlinear capacitance adds amplitude-dependent time-walk.
Protection placement creates reflections/ringing → multi-crossing near VTH.

Quick checks

Compare dV/dt at VTH before vs after adding clamps.
Check for ringing around VTH and count crossings near threshold.
Temporarily bypass the clamp to confirm causality (controlled condition only).

Threshold

Treat the clamp as timing-critical when it causes dV/dt@VTH drop > 30%, or when ringing creates more than one threshold crossing per event.

Action

Use lower-capacitance protection devices and validate their C vs V behavior.
Partition protection: rugged at the connector, low-C near the timing node.
Add damping/termination so the clamp does not create ringing near VTH.

Avoid

Avoid adding “large C for protection” directly at the comparator input in ns timing paths.

How to tell if the scope/probe is creating the jitter you see?

Symptom

Measured jitter changes drastically when the probe style, ground lead, or bandwidth settings change.

Likely causes (Top3)

Long ground lead inductance creates ringing near VTH.
Probe capacitance loads the timing node and slows dV/dt.
Trigger/bandwidth filtering hides or reshapes real timing variation.

Quick checks

Use a ground spring (short return) and compare against a long ground clip.
Compare passive probe vs active probe at the same node (same bandwidth).
Measure at the comparator pin and at the receiver pin; compare timing distributions.
Repeat with fixed bandwidth and fixed threshold definition across all runs.

Threshold

If the measured jitter changes by > 25–30% when only the probing method changes, treat the result as measurement-limited until proven otherwise.

Action

Use shortest possible ground return and minimize loop area at the probe point.
Use appropriate bandwidth and keep it consistent across comparisons.
Capture enough events for statistics and report the threshold definition used.

Avoid

Do not declare “ultra-low jitter” if bandwidth/trigger settings can suppress the apparent variation.

When should a preamp/buffer be added before a high-speed comparator?

Symptom

The comparator is fast on paper but the system jitter/time-walk is large with small signals or high source impedance.

Likely causes (Top3)

Insufficient OD(min) at the threshold under real amplitude and noise.
Insufficient dV/dt@VTH due to source impedance and input loading.
Kickback/reflections corrupt the high-impedance source near VTH.

Quick checks

Compute σt from σv and dV/dt; compare to the timing budget.
Estimate RC loading: RTH(source) × Cin(total) near the comparator input.
Check for input node disturbance when the comparator toggles (kickback signature).

Threshold

Add a buffer/preamp when σt(computed) > 10% of budget, or when RTH × Cin consumes > 10% of the allowable edge-transition time at VTH.

Action

Use a limiter/fast buffer to increase dV/dt at VTH and stabilize OD(min).
Lower effective source impedance (driver, transformer stage, or dedicated buffer).
Keep buffer close to the comparator to control reflections and kickback.

Avoid

Avoid feeding ns comparators through high-value divider networks without verifying slope, loading, and kickback.

Why does VICR near rails cause unpredictable switching timing?

Symptom

Timing and threshold behavior changes abruptly when the input common-mode approaches a supply rail.

Likely causes (Top3)

Input-stage crossover region changes gain and delay behavior.
Reduced headroom distorts the crossing slope (dV/dt) near VTH.
Supply/ground noise has higher leverage when operating near limits.

Quick checks

Run the same stimulus at multiple common-mode levels and compare tpd/jitter.
Check datasheet VICR and any crossover notes; do not assume “RR” equals identical behavior.
Measure local supply noise while toggling output and nearby digital lines.

Threshold

Treat operation as high-risk when VCM is inside the datasheet “crossover / not-guaranteed” region, or when a small VCM shift causes > 20% change in tpd/jitter under the same stimulus.

Action

Shift the common-mode away from the crossover region (bias network or coupling strategy).
Use a device characterized for the intended VICR corner and validate at temperature/VDD extremes.
Strengthen local decoupling and return-path control to reduce threshold modulation.

Avoid

Avoid assuming timing performance is unchanged across the full “rail-to-rail” common-mode span.

Push-pull output looks clean, but FPGA capture still jitters—why?

Symptom

The comparator output edge looks fast on the scope, but the FPGA/TDC timestamp distribution is wide.

Likely causes (Top3)

Receiver threshold + IO supply noise converts edge noise into time variation.
Ground bounce and return-path sharing shifts the receiver reference.
Interconnect loading/termination creates ringing and multiple crossings at the receiver pin.

Quick checks

Measure at the FPGA pin (not only at the comparator pin) and compare crossings.
Toggle neighboring IO and check if timestamps shift or broaden.
Check for ringing at the receiver threshold and verify termination strategy.

Threshold

Treat the receiver as the limiter when the timing spread correlates with digital activity, or when the edge at the receiver is slow enough that ΔVthreshold / (dV/dt) is a meaningful fraction of the budget.

Action

Improve receiver-domain signal integrity (shorter route, proper termination, controlled return path).
Reduce IO supply noise and ground bounce (decoupling + partitioning + return control).
Consider differential signaling (LVDS/CML) when the environment is noisy.

Avoid

Avoid judging capture quality from a single probe point that is not the receiver pin.

How to reduce kickback-induced errors in high-impedance sources?

Symptom

The source node shows disturbances when the comparator switches, and timing becomes unstable.

Likely causes (Top3)

Comparator input switching injects transient current into the source (kickback).
High Thevenin resistance converts kickback current into a large voltage step.
Ringing and reflections around VTH create multi-crossing timing noise.

Quick checks

Probe the source node while toggling the comparator; look for step-like disturbances.
Increase source drive strength temporarily; check if timing improves.
Add a small series resistor near the comparator pin and check for reduced ringing.

Threshold

Kickback is timing-critical when the observed source disturbance is > 0.2× OD(min) or when it can cause additional VTH crossings.

Action

Lower Thevenin resistance (buffer/preamp, stronger driver, closer source).
Add Rseries near the comparator input to limit kickback current peaks and damp ringing.
Use controlled routing/termination so switching energy does not reflect back into the source.

Avoid

Avoid “fixing” kickback by adding large shunt capacitance at the timing node without re-checking dV/dt and time-walk.

What’s the right way to measure delay dispersion over temperature?

Symptom

Delay statistics vary run-to-run across temperature, and results do not match expectations from datasheet curves.

Likely causes (Top3)

Stimulus conditions are drifting (OD, slope, common-mode, load, trigger point).
Insufficient thermal soak causes slow drift during capture.
Measurement chain dominates (probe/trigger jitter changes with temperature).

Quick checks

Freeze the definition: same threshold reference, same bandwidth, same load, same probe method.
Log OD(min) and dV/dt@VTH at each temperature point (do not assume constant).
Capture enough events (statistics) and report percentile (e.g., 99% window), not only mean.

Threshold

Consider the point “thermally settled” when temperature drift is < 0.2°C over 60 s, or when measured delay mean changes by < 5% of the target timing margin over the same window.

Action

Use a fixed stimulus chain (same cabling, attenuation, biasing, termination) across all temperatures.
Soak, then capture: record temperature and supply at the device pins during the capture window.
Report dispersion as a distribution (mean + percentile window) and include test conditions.

Avoid

Avoid changing trigger definition or probe configuration between temperature points.

Latch output shows occasional wrong polarity—metastability or ringing?

Symptom

Rare events produce the wrong latched state, often clustered around certain timing or input conditions.

Likely causes (Top3)

Sampling inside setup/hold unsafe window (metastability risk).
Input ringing causes multiple crossings near the latch moment.
LE/CLK edge integrity issues (bounce or coupling into the input reference).

Quick checks

Phase-sweep LE/CLK and map error rate vs phase (metastability signature).
Capture the input around VTH and count crossings near the latch moment (ringing signature).
Compare errors under quiet vs high digital activity (coupling signature).

Threshold

If errors disappear when moving LE/CLK by > 2× the worst-case setup/hold away from the crossing, the dominant issue is likely timing window / metastability risk. If errors persist and multiple crossings exist, treat it as ringing.

Action

Increase setup/hold margin (move LE/CLK, reduce skew, reduce time-walk).
Eliminate ringing (damping, termination, reduce stub length, improve return path).
Retiming strategy: add a clean downstream capture stage with sufficient resolving time.

Avoid

Avoid diagnosing “metastability” without a phase sweep; ringing and multi-crossing can look similar.

High-Speed / Latched Comparator: ns Delay, Jitter, and Latch Timing

High-Speed / Latched Comparator: ns Delay, Jitter, and Latch Timing

What this page solves (and what it does not)

Typical cases that truly need high-speed / latched comparators

What this page provides (practical deliverables)

Common mistakes that break timing repeatability

High-Speed vs Latched vs Regenerative: choosing the right bucket

Behavior-level differences (what matters in real timing chains)

Decision tree (fast routing without mixing page scopes)

Scope boundaries (to avoid cross-page overlap)

Internal signal path: preamp → decision core → output stage (conceptual)

What each stage “owns” (measurable outcomes)

Dominant error source mapping (symptom → likely cause → quick check)

Critical reminder: clean edges do not guarantee low decision jitter

Propagation delay: overdrive, slew rate, and delay dispersion

Three facts that govern delay in real designs

Budgeting method (action-oriented)

The most common budgeting mistake

Timing uncertainty: edge jitter, noise-to-time conversion, and time-walk

Three dominant contributors (what they look like on the bench)

Actionable budgeting (voltage → time)

If measured jitter increases, remove these traps first

Latch/Enable timing: aperture, setup/hold, metastability, and bubble errors

What a latch changes (value and cost)

Budgeting method (engineering steps)

Incorrect use to avoid (scope boundary)

Input interface for ns comparators: impedance, kickback, clamps, and VICR traps

The real enemies at the input (timing symptoms)

Actions and checks (threshold-oriented)

A common trap that guarantees slow and jittery results

Output stage & logic interfacing: edge integrity, loading, and level domains

Output timing is a link problem, not a pin problem

Actions that improve edge integrity and capture determinism

When edges look fast but the system still jitters

Practical timing budget: from input slope to timestamp error

A reusable template (what to add up)

Budget fields (and how to obtain each term)

The most common missing term

Measurement & validation: how to measure delay and jitter without lying to yourself

Definitions that prevent silent mistakes

Minimal reproducible workflow (setup → stimulus → capture → compute → checks)

If jitter looks “too small”, suspect the setup first

Engineering checklist: layout, decoupling, return paths, and isolation from digital trash

What this checklist protects

Layout review checklist (copy-ready)

Typical failures that widen delay spread and jitter

Applications (recipes) for High-Speed / Latched Comparators

Recipe set (ns / latched-focused)

IC selection logic

A) Minimum fields for high-speed / latched comparators

B) Risk mapping: scenario → what to prioritize

C) RFQ template (ask suppliers for usable, budget-ready data)

Example part numbers to evaluate (verify outputs and latch pins in the datasheet)

Recommended topics you might also need

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FAQs – High-Speed / Latched Comparator

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