Zero-Crossing Comparator for AC Zero Detect & Phase Sync
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Zero-cross detection is not a “perfect mathematical zero” but a noisy switching zone—this page shows how to make it trigger exactly once per half-cycle and keep phase error measurable and budgeted.
It links comparator specs, hysteresis, filtering, output interfacing, measurement, and layout into a practical workflow that rejects mains bursts and common-mode pickup while preserving timing accuracy.
What this page solves (Zero-cross detect & phase sync)
A zero-crossing comparator turns a noisy AC crossing into a single, repeatable digital edge that can be used for timer capture, phase synchronization, and mains-related control. The engineering goal is not “detect 0 V perfectly”, but to achieve stable triggering and a phase-error budget that can be verified on the bench and held across temperature, noise, and wiring.
Typical use cases
- Mains zero-cross detect for timing, dimming, and switching synchronization
- Phase sync / phase comparison (timestamp edges and close the loop in digital control)
- AC metering triggers and robust time-stamping under mains noise
- Sync-rectification / “zero-cross aligned” control to reduce EMI and stress
- Over-zero / under-zero gating for safety interlocks and line-state monitoring
What “good” looks like (acceptance language)
- One edge per crossing: no chatter bursts around the crossing zone.
- Predictable timing: phase error can be decomposed (offset/drift, hysteresis, delay, filtering).
- Noise immunity: mains spikes, cable touch, and ground bounce do not create false edges.
- Bench-verifiable: timing jitter and drift can be measured repeatably with simple setups.
Scope boundary (to avoid topic overlap)
Focus is zero-cross triggering and phase-sync quality. Window-comparator systems, Schmitt-gate logic families, and full safety/insulation standards are not expanded here.
Diagram intent: zero-cross performance is set by the entire chain (acquisition → filtering/protection → comparator → digital capture/sync).
Definition & scope: what “zero crossing” really means in real systems
In real hardware, “zero crossing” is not a mathematical point. It is a crossing zone around the threshold where the input may wander due to noise, offset/drift, source impedance, and even measurement probe injection. Near the crossing, the waveform slope is smallest, so the same voltage disturbance becomes a larger timing disturbance.
Two error classes (drives the rest of the page)
- Structured shift: offset/drift and bias-current × source-R move the effective crossing level in a predictable direction.
- Event-driven jitter: mains spikes, burst noise, ground bounce, and cable pickup create random-looking timing scatter and false edges.
Practical definition (engineering-ready)
A zero-cross event is the moment the input crosses a threshold band. The band width is set by the input noise and the chosen hysteresis; the event timing shifts with offset/drift and front-end phase shift. The design target is to make this event single-shot and time-accurate enough for the control system.
Fast triage language (for debugging)
- If multiple toggles cluster near the crossing: suspect insufficient hysteresis or too much noise pickup.
- If timing drifts with temperature: suspect offset drift or bias-current × source-R threshold shift.
- If timing shifts after adding RC protection: suspect phase shift from the front-end filter.
Diagram intent: near the crossing, a small voltage disturbance becomes a larger timing disturbance; without hysteresis, noise can create multiple toggles.
Comparator behaviors that matter for zero-cross (offset, drift, input range, output)
A zero-cross design fails in four recognizable ways: phase error, false triggers, missed crossings, and EMI sensitivity. The fastest path to a robust solution is to translate a handful of datasheet specs into these system outcomes and then validate each outcome with a targeted bench check.
Phase error (timing shift that repeats)
- Offset & drift shift the effective crossing level; the shift becomes timing error near the low-slope crossing region.
- Input bias current × source impedance adds an extra threshold shift that often looks like “mysterious drift”.
- Propagation delay at small overdrive can stretch and become less predictable right where the zero-cross slope is smallest.
Practical check: compare edge timestamps at two input amplitudes. If timing improves strongly with amplitude, small-overdrive behavior is dominating.
False triggers (extra edges around the crossing)
- Insufficient input-range margin (VICR near rails or crossover regions) can create irregular toggles or “sticking”.
- Output edge return paths can inject noise back into the input reference (ground bounce → self-triggering).
- High source impedance turns cable pickup and burst noise into threshold modulation.
Practical check: add temporary hysteresis (or reduce source impedance) and observe whether multi-toggling collapses into a single clean edge.
Missed crossings (missing an expected edge)
- VICR not covering the real input point (single-supply + mid-bias schemes are common pitfalls).
- Weak pull-up on open-drain can make edges too slow to cross digital thresholds reliably on long wiring.
- Delay dispersion at low overdrive may shift edges outside a digital capture window or deglitch logic.
Practical check: probe the comparator output directly at the pin and at the MCU pin; differences indicate wiring, pull-up, or ground-return issues.
Output type selection (OD vs push-pull) — impact on wiring immunity
- Open-drain: pull-up sets edge speed and noise margin; better for cross-voltage domains but sensitive to wiring length.
- Push-pull: clean edges without pull-up, but fast edges demand disciplined return paths to avoid self-injection.
Use the mapping to prioritize debug: identify the dominant outcome (phase / false / missed / EMI), then test the matching spec pathway first.
Symmetric hysteresis: why it’s used and what it breaks
Symmetric hysteresis turns the crossing into a single-shot event under noise, long wiring, and slow ramps. The trade-off is timing: the effective switching points move from an ideal “0” to ±VHYS/2, shifting the edge time. A robust design chooses hysteresis large enough to prevent chatter, then verifies that the induced timing shift fits the phase budget.
When hysteresis must be larger
- Slow crossing (low dV/dt near zero): small voltage noise becomes large timing jitter.
- High burst noise: mains spikes and cable pickup create multiple threshold crossings.
- Long wiring: capacitive and inductive pickup modulates the threshold without a strong hysteresis band.
When hysteresis must be smaller
- Phase-accuracy driven systems: time-stamping and phase loops require a tight, predictable edge location.
- Small signal near the crossing: a large band may shift the edge too early/late.
- Consistency over temperature: avoid using a “huge band” to hide drift problems that should be budgeted explicitly.
Practical sizing workflow (engineering-safe)
- Measure the noise band at the crossing (peak-to-peak in the zoomed region).
- Choose VHYS so the band is not crossed repeatedly under expected burst events.
- Convert VHYS into timing shift using the local slope (dV/dt) and compare against the phase budget.
- If timing shift is too large, reduce noise injection first (front-end, wiring, grounding), then reduce VHYS.
Diagram intent: hysteresis suppresses multi-toggling but shifts the switching time from an ideal zero to ±VHYS/2 crossings.
Phase error budget: offset + hysteresis + delay + filter phase shift
A zero-cross edge becomes useful for synchronization only after its timing error is decomposed into a small set of measurable terms. A practical budget separates fixed shift (front-end phase), structured drift (offset/drift and bias effects), and random jitter (noise and small-overdrive delay dispersion).
Universal conversion near the crossing (engineering-safe)
Near the crossing, small voltage terms turn into time terms: Δt ≈ ΔV / (dV/dt). The local slope dV/dt is set by the waveform frequency and amplitude, so the same ΔV produces a larger Δt when the crossing is slow.
Practical check: measure timing jitter at two amplitudes. If jitter collapses at higher amplitude, the dominant problem is a slow crossing (small dV/dt).
Term 1 — Comparator propagation delay (tpd vs overdrive)
- Mean delay creates a mostly fixed phase shift.
- Delay dispersion increases as overdrive becomes small near the crossing, adding jitter-like scatter.
Practical check: sweep input amplitude (or threshold band) and plot timestamp spread. A strong dependence indicates small-overdrive behavior is dominating.
Term 2 — Front-end RC/EMI phase shift (filter φ(f))
- Any RC or EMI network adds phase shift at 50/60 Hz and its harmonics.
- This term is often a repeatable offset (good for calibration) but can drift if the network is temperature sensitive.
Practical check: temporarily bypass the RC element and measure the mean phase change. A clean step in mean phase points to filter φ(f) as the main fixed term.
Term 3 — Offset & drift (VOS, dVOS/dT) → threshold shift
- Offset and drift shift the effective threshold away from zero; treat this as a ΔV term.
- Convert to timing with Δt ≈ ΔV / (dV/dt) at the crossing.
- Input bias current × source resistance adds an additional ΔV term and can mimic drift.
Practical check: record mean phase vs temperature. A smooth monotonic trend suggests structured drift rather than random EMI.
Term 4 — Symmetric hysteresis (±VHYS/2) → timing shift
- Hysteresis suppresses chatter by requiring the input to traverse a band.
- The switching points move to ±VHYS/2, creating a predictable timing shift that grows when the crossing is slow.
Practical check: increase VHYS until chatter disappears, then reduce noise injection paths before shrinking VHYS to meet the phase budget.
Verification language (mean shift vs jitter vs drift)
- Mean phase error: average offset from the desired phase reference.
- Jitter: spread of timestamps around the mean (random term).
- Temperature drift: mean phase slope vs temperature (structured term).
Diagram intent: treat phase error as a sum of four measurable contributors; tune each contributor with targeted tests.
Front-end recipes for mains/noisy AC (divider, biasing, coupling, clamps)
The front-end determines how much noise and phase shift are injected into the crossing zone. Three practical templates cover most systems: direct divider, single-supply mid-bias coupling, and transformer/CT acquisition with secondary protection. Each template must be evaluated for false triggers, missed crossings, and phase shift.
Template A — Direct divider into the comparator
- Simple and low cost for mains timing and basic zero-cross detection.
- High divider impedance increases pickup and bias-current-induced threshold shift.
- RC filtering improves burst immunity but adds phase shift that must be budgeted.
Template B — Divider + AC coupling + mid-bias (single-supply)
- Common when the comparator input must sit around a mid-rail reference.
- Mid-bias noise and impedance directly modulate the threshold and add jitter.
- Coupling networks can shift 50/60 Hz phase; treat as a budget term.
Template C — Transformer/CT acquisition + secondary protection
- Improves common-mode immunity and enables safer/noisier environments.
- Secondary clamps can be nonlinear; avoid disturbing the crossing region.
- Sensor phase characteristics must be included in the total phase budget.
Common rules (zero-cross specific)
- Any protection/filtering that changes waveform shape near the crossing can create false edges.
- Reduce injection paths first (wiring/grounding/return paths), then reduce hysteresis for phase accuracy.
- Validate at the comparator pin and at the MCU pin; differences isolate wiring and pull-up problems.
Diagram intent: three copyable front-end templates; each must be checked for phase shift, false triggers, and missed crossings.
Mains-noise rejection & glitch immunity (harmonics, bursts, common-mode)
Zero-cross failures are rarely caused by “random noise” alone. The dominant enemies are event bursts (spikes, EFT-like trains, switching edges) and common-mode injection (long cables, ground bounce, touch). Immunity improves fastest when the injection path is identified and the countermeasure is placed where it closes the smallest loop.
Harmonics & waveform distortion (repeatable phase shift)
- Distortion changes the local crossing shape and slope, increasing sensitivity to offset and hysteresis.
- This often appears as a stable mean phase error that depends on load or mains conditions.
Quick check: compare mean phase at two loads or two input levels. A repeatable offset suggests waveform-shape dependence rather than random EMI.
Bursts & spikes (extra edges and phase jumps)
- Switching spikes can create extra crossings inside the hysteresis band, causing multi-toggling.
- Clamps placed in the wrong location can add nonlinearity near the crossing and trigger “phantom edges”.
Quick check: scope the comparator input with a short ground spring. If spikes coincide with extra output edges, the problem is burst injection, not baseline noise.
Common-mode injection (cables, ground bounce, touch)
- Long wiring and undefined return paths convert common-mode disturbance into differential threshold modulation.
- Fast output edges with poor return paths can self-inject through ground bounce and appear as input “noise”.
Quick check: touch or move the cable while monitoring timestamp spread. Strong correlation indicates common-mode pickup and return-path problems.
Engineering actions (place-by-place)
- Series R at the input pin: limits injected current and tames burst edges locally.
- RC near the comparator: closes a small loop for high-frequency energy and reduces multi-toggling.
- Clamp where energy is absorbed: avoids reshaping the crossing region at the sensitive node.
- Shielding + defined return: prevents common-mode current from traversing the comparator reference.
- Hysteresis strategy: increase VHYS to stop chatter, then reduce injection to shrink VHYS for phase accuracy.
Diagram intent: map event bursts and common-mode pickup to the most effective placement of series R, RC, clamps, and shielding.
Output interfacing: OD vs push-pull, level shift, timer capture, isolation option
The output stage determines edge integrity at the MCU pin. Open-drain outputs depend on pull-up and wiring capacitance, while push-pull outputs produce strong edges that demand disciplined return paths. Timer capture is preferred for phase work, and isolation is an option when common-mode and safety constraints dominate.
Open-drain output (pull-up sets edge behavior)
- Pull-up + wiring capacitance set the rising edge rate and noise margin at the MCU input.
- Weak pull-up can create slow edges that are vulnerable to interference and can be mis-captured.
- Stronger pull-up improves edge integrity but increases static current during low output states.
Quick check: measure rise time at the comparator pin and at the MCU pin. A large difference indicates wiring capacitance and pull-up placement issues.
Push-pull output (clean edges, return-path discipline)
- Produces strong edges without pull-up and improves logic-level certainty.
- Fast edges can create ground bounce if return paths are long or shared with sensitive references.
- Output and input must be separated to avoid self-injection into the crossing node.
Quick check: observe whether extra toggles appear only when the output edge rate is increased. If yes, the failure is return-path coupling.
MCU timing capture (interrupt vs capture, deglitch strategy)
- Timer capture is preferred for phase work; interrupt latency can translate into timing error.
- Deglitch windows must suppress burst edges without creating missed crossings.
- Validate edge count per cycle; multiple edges indicate injection or insufficient hysteresis.
Isolation option (concept placement only)
- Isolation can break common-mode paths and improve safety margins in harsh environments.
- Key risks are delay, jitter, and CMTI limits of the isolation link.
- Edge integrity and timer capture strategy still matter after isolation.
Diagram intent: show two common interfacing chains and the key risk keywords (edge rate, ground bounce, CMTI, delay, jitter).
Measurement & validation: how to measure zero-cross jitter and phase accurately
Meaningful validation separates three outcomes: mean phase error (repeatable shift), jitter (random spread), and event errors (extra edges or missed crossings). The goal is statistical evidence, not a single screenshot. Measurement setups must also control probe loading and grounding, because they can create “problems” that do not exist in the real system.
What to measure (three buckets)
- Mean phase error: average time/phase shift versus a chosen reference point.
- Jitter: statistical spread of timestamps around the mean (RMS + high-percentile).
- Event errors: extra edges per cycle, missed crossings, burst-correlated phase jumps.
Instruments (use the right one for the question)
- Oscilloscope: best for seeing the crossing zone and measuring time intervals statistically.
- Logic analyzer: best for long-run counts (extra edges / missed edges), not for fine analog jitter.
- MCU timer capture: closest to system reality; validates capture strategy and deglitch windows.
Reference source strategy (clean first, real later)
- Function generator: establishes the circuit baseline with a clean waveform.
- Isolated AC source / transformer: improves safety and repeatability for sweeps.
- Real mains: final acceptance; includes harmonics, bursts, and load-dependent distortion.
Measurement traps (probe loading and grounding)
- High-impedance nodes can shift when loaded by probe capacitance (apparent phase change).
- Long ground leads can inject ringing and create extra threshold crossings.
- Wrong trigger reference can hide phase error by referencing an already-shaped node.
Acceptance language (how to set thresholds)
- Define phase margin in the control or capture window, then allocate a portion to zero-cross error.
- Use RMS + high-percentile jitter for stability, plus an event-error criterion for bursts.
- Specify drift as a mean-phase slope versus temperature or line conditions.
Diagram intent: a copyable test setup showing stimulus choices, capture options, and the top two pitfalls (probe loading and grounding).
Layout & grounding for zero-cross comparators (ground bounce, symmetry, shielding)
Layout problems in zero-cross designs usually show up as extra edges, missed crossings, or phase jumps. The most effective layout rules focus on keeping the sensitive input node quiet and forcing fast digital return currents to stay out of the comparator reference region.
Priority layout checks (zero-cross critical)
- Input symmetry: keep input routing balanced and loops small to reduce differential pickup.
- Protection/RC at the pin: place clamp, series R, and RC close to the comparator input pin.
- Output return isolation: keep fast output return currents away from the input reference region.
- High-impedance node control: shorten high-Z traces and avoid nearby high dv/dt copper.
- Single connection strategy: define a controlled analog/digital return connection point.
Quick debug hint (layout-driven coupling)
If extra toggles appear only when the output edge is fast, the dominant mechanism is usually ground bounce or return-path coupling from output to input reference. Fix return paths first before increasing hysteresis.
Diagram intent: a top-view mental model separating sensitive and dirty zones, emphasizing placement and return-path control.
Engineering checklist (design review + test hooks)
This checklist consolidates the design into reviewable gates. Each item is written as check → pass/fail → test hook, so phase sync issues can be debugged quickly and validated consistently across temperature, noise bursts, and real mains conditions.
Requirements gate (define acceptance language)
- Phase error budget: allocate from the control/capture window margin (leave system headroom).
- Jitter budget: specify RMS + a high-percentile (e.g., “tail” metric) rather than single-shot.
- Event errors: define max extra edges per cycle and missed-cross rate under burst tests.
Circuit review (knobs that dominate zero-cross quality)
- VHYS target: large enough to stop chatter under worst noise, then reduced after injection paths are fixed.
- Filter placement: RC located to close a small loop at the comparator input; treat phase shift as a budget term.
- Protection strategy: series-R and clamps placed to limit injected current without reshaping the crossing node.
- Interface strategy: OD vs push-pull, pull-up placement, and capture method (timer capture preferred for phase).
Layout review (zero-cross critical)
- Input symmetry: keep the sensitive loop small; avoid running near high dv/dt copper.
- Pin-close protection/RC: clamp, series-R, and RC near the input pin.
- Output return control: fast return currents must not cross the input reference region.
- High-Z node control: minimize high-impedance trace length; avoid contamination/creep paths.
- Return predictability: define a controlled analog/digital return connection point.
Validation plan (stress what actually breaks zero-cross)
- Temperature: mean phase vs temperature slope (drift), plus event-error checks at corners.
- Burst injection: switching spikes / EFT-like trains; verify “no extra edges per mains cycle”.
- Common-mode: cable touch/motion, ground disturbances; verify jitter tail and event-error counts.
- Supply disturbance: brown-in/out and droop; verify no false toggles during supply transients.
Production test hooks (make it measurable on the line)
- Test points: IN node, bias mid, Vref, OUT, and a clean return reference.
- Config options: selectable VHYS/RC or pull-up placement to isolate root cause quickly.
- Line metrics: edge count per cycle, timestamp spread, and burst-triggered event error rate.
Applications (only zero-cross related recipes)
These recipes stay strictly within zero-cross use cases: phase sync, low-EMI switching, metering timestamps, and line-synchronized control. Each recipe lists the minimal signal chain, key knobs, common failure modes, and example part numbers to search.
Note: example part numbers are search anchors (not purchase recommendations). Final selection must be validated against datasheets and system constraints.
Recipe 1 — AC phase sync (phase-locked timing / synchronized switching)
- Signal path: AC sense → zero-cross → timer capture → phase control.
- Key knobs: VHYS vs phase accuracy, RC placement, capture vs interrupt, edge count per cycle.
- Failure modes: phase jumps under bursts, extra edges near crossing, drift over temperature.
- Example parts to search: LM393 / LM2903, MCP6561 / MCP6562, ADCMP600 (family), LTC6752 (family)
Recipe 2 — Zero-cross triac/SSR control (lower EMI switching)
- Signal path: AC sense → zero-cross → delay/angle → triac/SSR drive.
- Key knobs: glitch immunity, burst rejection, pull-up edge rate (OD), cable/return control.
- Failure modes: false triggering from spikes, multi-toggling near crossing, missing crossings under noise.
- Example parts to search: LM393 / LM2903, MCP6561 / MCP6562, MOC3063, MOC3023
Recipe 3 — AC metering trigger & timestamping (time base alignment)
- Signal path: line sense → zero-cross → timestamp → metering computation.
- Key knobs: reference selection, jitter statistics (RMS + tail), stable capture at the MCU pin.
- Failure modes: timestamp tails under common-mode pickup, drift with temperature, probe-induced “fake” jitter.
- Example parts to search: LM393 / LM2903, MCP6561 / MCP6562, ADCMP600 (family)
Recipe 4 — Motor drive line sync / grid-tied timing (concept only)
- Signal path: line sense → zero-cross → sync gate → controller timing.
- Key knobs: event-error suppression first, then phase budget; consider isolation only if common-mode dominates.
- Failure modes: burst-driven false edges, ground-bounce injection from fast outputs, capture window collapse.
- Example parts to search: LM393 / LM2903, ISO7721, ADuM110N (family)
Diagram intent: four minimal “copyable” signal chains with only block names (no long text), suitable for mobile viewing.
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FAQs (zero-cross long-tail)
These FAQs target practical zero-cross issues: chatter, phase shift, jitter, mains bursts, OD pull-ups, biasing, measurement traps, and layout-driven false triggers. Answers are short, action-oriented, and structured for repeatable troubleshooting.
Why does the output toggle multiple times near zero (chatter)? What are the top 3 things to check first?
Symptom: More than one edge appears around each crossing, or edge count per cycle varies.
Likely causes (Top 3): (1) VHYS too small vs noise + slow slope, (2) burst/common-mode injection into the input reference, (3) probe/ground loop creating ringing at the crossing node.
Quick checks: Count edges per mains cycle on the MCU pin; temporarily increase VHYS; move the probe to a lower-impedance node and use a short ground spring; compare “quiet source” vs real mains.
Threshold: Exactly one valid edge per half-cycle under worst expected noise/burst conditions; no “extra edges” during burst tests.
Action: Fix injection paths and return currents first (layout/grounding, pin-close RC/clamp), then set VHYS just above worst-case noise at the crossing node, then verify edge count again at the MCU pin.
Avoid: Do not “solve” chatter only by increasing VHYS if return-path coupling is the true trigger; always validate at the receiving pin, not only at the comparator output.
After increasing hysteresis, phase shifted noticeably. How to estimate whether VHYS or RC is the main contributor?
Symptom: The crossing timestamp shifts earlier/later after changing hysteresis or input filtering.
Likely causes (Top 3): (1) VHYS moves the effective switching level away from zero, (2) RC/filter phase shift at 50/60 Hz and harmonics, (3) overdrive-dependent delay changes after reshaping the input.
Quick checks: Change VHYS only (keep RC constant) and observe proportional timestamp shift; then change RC only (keep VHYS constant) and observe frequency/harmonic sensitivity; compare mean shift vs jitter spread to separate deterministic vs random terms.
Threshold: Mean phase shift must stay within the allocated phase budget after the worst-case VHYS/RC setting is applied.
Action: If VHYS dominates, reduce VHYS by fixing noise injection (layout/CM paths) and improving slope at the crossing; if RC dominates, move/resize the RC to reduce phase shift while keeping burst suppression.
Avoid: Do not tune VHYS and RC simultaneously during root-cause; change one knob at a time and measure at the MCU pin.
How to keep 50 Hz and 60 Hz compatibility without adding too much phase shift from filtering?
Symptom: Filtering improves noise immunity but introduces a measurable timing/phase offset.
Likely causes (Top 3): (1) RC corner too close to 50/60 Hz or strong low-order harmonics, (2) filter placed at a node that reshapes the crossing slope, (3) parasitic capacitance creates an unintended extra pole.
Quick checks: Measure mean phase at 50 and 60 Hz separately; sweep input amplitude to see if timing depends on slope; compare phase with/without the capacitor to detect parasitic-dominated behavior.
Threshold: Phase shift difference between 50 and 60 Hz must not collapse the control/capture window margin.
Action: Place the noise filter where it blocks injected bursts but does not heavily reshape the crossing slope; reduce unintended poles by tightening layout and controlling high-Z nodes; validate 50/60 Hz phase separately.
Avoid: Do not assume “cleaner waveform” always means “better timing”; always measure the phase budget impact.
Why is it stable during the day but noisy at night or when motors start? What injection path is most common?
Symptom: Random phase jumps and extra edges correlate with load switching, motor starts, or time-of-day.
Likely causes (Top 3): (1) burst noise riding on the line (dv/dt spikes), (2) ground bounce/return-path coupling from fast digital edges, (3) common-mode pickup via long cable/shield/earth reference.
Quick checks: Count extra edges during a controlled “burst window”; compare behavior with an isolated AC source; move the cable and observe sensitivity; check whether extra edges correlate with local digital switching.
Threshold: Under worst expected bursts, edge count per half-cycle must remain at 1 and missed-cross must remain below the defined field rate.
Action: Add pin-close series-R and clamp where injected current is limited; enforce return-path separation between output and input reference; adjust VHYS only after injection is reduced; validate again under the real burst condition.
Avoid: Do not rely on “quiet lab mains” as acceptance; validate on the noisiest expected line environment.
How to choose an OD pull-up resistor, and what happens if the edge is too slow?
Symptom: OD output rise time is slow, input sees multiple transitions, or timing varies with cable length.
Likely causes (Top 3): (1) pull-up too weak for the total capacitance (pin + trace + cable), (2) level-shift node is too “soft” and susceptible to noise pickup, (3) receiver input threshold/hysteresis is not sufficient for slow ramps.
Quick checks: Measure rise time at the MCU pin; shorten cable/trace and compare; temporarily reduce pull-up value to see if edge-count errors improve; check ground reference stability during rising edges.
Threshold: Rise time must be fast enough that the receiver sees one clean transition per event with margin against injected noise.
Action: Choose pull-up based on worst-case capacitance and noise environment; place pull-up where it improves edge integrity at the receiver; if cable is long/noisy, add a controlled edge-shaping stage at the receiver side.
Avoid: Do not judge edge quality at the comparator pin only; verify at the receiving MCU pin under worst cable and noise.
Single-supply input cannot reach 0 V. What is the most stable AC-coupling + mid-bias approach?
Symptom: The comparator cannot sense near ground, or the crossing point shifts with source impedance and bias leakage.
Likely causes (Top 3): (1) VICR does not include the intended crossing region, (2) bias network is too high impedance and sensitive to leakage/IB, (3) coupling capacitor + bias creates an unintended time constant that reshapes the crossing slope.
Quick checks: Verify VICR at the actual bias point; measure bias node stability under temperature/humidity; reduce bias impedance temporarily and observe whether phase/jitter improves; verify the coupling time constant does not distort the zero region.
Threshold: The biased crossing region must stay inside VICR across supply and temperature, and the bias node must remain stable enough that mean phase drift stays within budget.
Action: Bias the input around a quiet mid-point inside VICR; keep the bias network low enough impedance to dominate leakage and IB effects; place RC/clamp at the comparator pin to block bursts without distorting the crossing slope.
Avoid: Avoid very high-impedance bias nodes without guarding/layout control; they drift and pick up common-mode noise easily.
Divider resistors are very large to save power, but false triggers increase. What should be changed first?
Symptom: More event errors appear after increasing divider resistance or when humidity/handling changes.
Likely causes (Top 3): (1) higher source impedance makes the crossing node sensitive to IB/leakage, (2) parasitic capacitance and contamination create slow/unstable ramps, (3) noise injection dominates because the node is “soft.”
Quick checks: Temporarily lower divider impedance and re-measure edge count and jitter tails; compare behavior after cleaning/guarding; measure the crossing node with a low-loading method to detect “soft-node” distortion.
Threshold: Edge count per half-cycle must remain stable under cable touch and burst conditions; drift must not exceed the allocated mean-phase budget.
Action: First reduce the effective source impedance (lower R or buffer/bias node) and tighten layout around the high-Z node; then re-tune VHYS/RC for noise immunity with minimal phase penalty.
Avoid: Avoid extreme divider values without a plan for leakage, contamination, and parasitic capacitance control.
The comparator output edge looks clean, but the MCU still false-triggers. Is it ground bounce or crosstalk?
Symptom: False interrupts/captures happen even when the comparator output looks “good” locally.
Likely causes (Top 3): (1) ground bounce shifts the MCU input reference during fast edges, (2) crosstalk from adjacent fast nets injects into the input/capture pin, (3) slow OD rise plus noise pickup creates multiple threshold crossings at the MCU.
Quick checks: Probe at the MCU pin with short ground; correlate false triggers with other switching events; temporarily slow/shape the offending aggressor edge or change routing/return; compare timer capture vs interrupt behavior.
Threshold: At the MCU pin, exactly one transition must be observed per crossing event with margin against local switching noise.
Action: Enforce return-path separation (keep output returns out of the input reference region), improve pin-side filtering, and harden the receiver input path; validate using edge count and long-run event-error logging.
Avoid: Avoid validating at the source only; system acceptance must be measured at the receiving MCU input.
How to measure zero-cross jitter/phase so results are repeatable?
Symptom: Measurements vary between sessions, instruments, or probing methods.
Likely causes (Top 3): (1) probe loading and ground loop differences, (2) reference trigger point is not consistent, (3) stimulus source changes (generator vs real mains) alter harmonics/bursts.
Quick checks: Use the same reference definition (timestamp at MCU pin); collect statistics (mean, RMS, tail percentile) over long runs; compare clean source baseline vs real mains acceptance; change only one knob per experiment.
Threshold: Jitter must be specified as a distribution (RMS + tail) and must keep control/capture margin positive under worst conditions.
Action: Standardize probing and grounding, lock the reference definition, log edge counts and timestamps, and test both baseline and real mains scenarios.
Avoid: Avoid concluding from single-shot scope screenshots; use statistical evidence and long-run event logging.
After temperature sweep, phase drifted. Is it offset drift or bias × R?
Symptom: Mean timestamp shifts with temperature even under stable stimulus.
Likely causes (Top 3): (1) comparator input offset drift changes the effective switching threshold, (2) IB/leakage times source impedance shifts the bias point, (3) the bias network itself drifts (resistor TC, contamination, humidity).
Quick checks: Repeat with reduced source impedance to see if drift shrinks (bias×R signature); compare drift slope versus temperature with and without the high-Z bias/divider; verify VICR margin at temperature corners.
Threshold: Mean-phase slope versus temperature must remain within the allocated drift budget after worst-case impedance and leakage are considered.
Action: If bias×R dominates, lower impedance or buffer the node and control leakage paths; if offset drift dominates, reduce the required threshold accuracy (via improved slope/noise immunity) or choose a lower-drift comparator.
Avoid: Avoid attributing all drift to comparator offset without first testing source-impedance sensitivity.
On the PCB, phase shift is much larger than simulation. What parasitic is most common?
Symptom: Measured mean phase is worse than SPICE, or changes with routing/cable handling.
Likely causes (Top 3): (1) high-impedance node parasitic capacitance creates an unintended pole, (2) return-path coupling injects edge-related disturbance into the reference, (3) component tolerances and real mains harmonics shift the effective waveform near zero.
Quick checks: Measure sensitivity to probe/cable (parasitic-C signature); shorten high-Z routing and re-test; compare phase on isolated AC source vs real mains; temporarily bypass/relocate the RC capacitor to isolate unintended poles.
Threshold: Phase error on the real PCB must meet the system budget at both 50 and 60 Hz, under worst burst conditions.
Action: Reduce high-Z node sensitivity (lower impedance, shorten routing, control contamination), then re-tune RC for burst immunity; enforce return-path separation; validate at the MCU pin.
Avoid: Avoid relying on ideal stimulus and ideal parasitics in simulation; add parasitic-C and return-path coupling assumptions during design.
Should zero-cross detection add shaping/deglitch (one-shot)? When is it mandatory?
Symptom: Event errors occur under bursts or slow ramps even when basic hysteresis is applied.
Likely causes (Top 3): (1) burst noise produces multiple valid threshold crossings inside a short time window, (2) slow OD edges or slow input slope makes the receiver vulnerable, (3) system requires a single “qualified” edge for timing.
Quick checks: Log edge count per half-cycle during worst bursts; apply a firmware capture window and see if event errors disappear; compare interrupt vs timer capture with deglitch.
Threshold: If “extra edges” cannot be eliminated by analog fixes without violating phase budget, a deglitch window becomes mandatory.
Action: Use a one-shot or capture-window qualification sized from measured jitter tails and burst duration; keep the window small enough to preserve phase margin; validate long-run missed-cross rate.
Avoid: Avoid using an overly large deglitch window that hides real crossings and increases missed events under frequency/line variation.
