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Comparator Hysteresis (VHYS): Built-In vs External, Sizing

Comparator Hysteresis (VHYS): Built-In vs External, Sizing

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Hysteresis (VHYS) is a single knob that trades robustness for accuracy: it stops chatter from noise and slow ramps, but it also creates a threshold “error band” and timing shift. This page shows how to size, compute, and validate VHYS so false triggers disappear without causing misses or unacceptable drift across real-world corners.

What this page solves: hysteresis stops chatter, but creates an error band

Hysteresis (VHYS) turns a fragile “single threshold point” into a two-threshold band (VTH+ / VTH−) so noise and slow ramps stop causing multi-toggling. The trade-off is an error band: the switching point depends on direction, so absolute threshold accuracy becomes a range.

A) Field symptoms that VHYS is meant to fix

  • Slow ramp → multiple edges: the input lingers near the threshold and toggles repeatedly.
  • Noise/ ripple → random triggers: small disturbances cross the threshold back and forth.
  • Cable touch / movement: injected charge or EMI coupling causes false edges.
  • Weak pull-up (open-drain): slow rising edges stay in the transition region longer.
  • Too much VHYS: “no trigger” or late trigger (missed events) because the band is overly wide.

B) Root causes (kept strictly within VHYS scope)

1) Time-in-band is long
Slow slopes (low dV/dt) and slow edges (large pull-up R, heavy C) increase how long VIN stays near the switching region, giving noise many chances to cross.
2) Noise amplitude is comparable
Any coupled ripple / EMI / ground bounce that is “big enough” near threshold will push VIN across a single threshold repeatedly.
3) Threshold is not truly fixed
Bias/leakage with source resistance shifts the effective threshold. VHYS provides a deliberate band so small shifts do not produce extra edges.

C) The only three knobs used on this page (and how to choose fast)

Knob 1: Add / size VHYS
Makes two thresholds (VTH+ / VTH−) so noise cannot bounce across a single point. Cost: an error band (direction-dependent switching).
Knob 2: Add RC (only after VHYS)
Lowers noise amplitude at the cost of delay. If RC is the only thing preventing chatter, the design is trading response time for robustness.
Knob 3: Lower source impedance
Reduces threshold shift from bias/leakage and shortens time-in-band by making VIN “stiffer” near the switching region.
Quick decision rules
  • Slow edge or slow ramp near threshold → prioritize VHYS, then consider RC.
  • Chatter persists with small noise → check source R × bias/leakage shifting the effective threshold.
  • Missed triggers after adding VHYS → VHYS is too wide or the threshold center is not controlled (VTH+/VTH− must be computed and verified).
  • RC “fixes everything” but response is now slow → re-balance: increase VHYS and reduce RC delay.
Symptom to cause to knob map for hysteresis (VHYS) Three-column block diagram mapping field symptoms to root causes and to the three knobs: add VHYS, add RC, and lower source impedance. Symptoms Root causes Knobs Chatter Noise trigger Slow ramp Cable touch Time-in-band low dV/dt Amplitude ripple / EMI Drift bias × R Add VHYS VTH+ / VTH− Add RC reduce noise Lower Z stiffen VIN

Definitions: VTH+, VTH−, and VHYS as a bidirectional threshold band

A hysteretic input does not switch at one single voltage. It switches at two thresholds: VTH+ on the rising direction and VTH− on the falling direction. The hysteresis size is VHYS = VTH+ − VTH−. This band is what blocks chatter: small noise can move within the band without flipping the output.

A) The page convention (keeps math and measurements unambiguous)

  • VTH+: the VIN value where the output flips when VIN rises.
  • VTH−: the VIN value where the output flips when VIN falls.
  • VHYS: always defined as VTH+ − VTH− (a positive number).

This convention is independent of whether the comparator is wired “non-inverting” or “inverting”. The definition follows VIN direction, not output polarity.

B) How to read VTH+ / VTH− from a waveform (practical)

Step 1: sweep VIN slowly
Use a slow ramp (or triangle) so the switching points are easy to capture without timing ambiguity.
Step 2: record two VIN values
When output flips on rising VIN → VIN is VTH+. When output flips on falling VIN → VIN is VTH−.
Step 3: compute VHYS
VHYS = VTH+ − VTH−. This is the noise-tolerant band that blocks multi-toggling near the threshold.
Waveform and transfer curve for hysteresis (VTH+, VTH−, VHYS) Top panel shows a slow VIN ramp crossing VTH+ and VTH− with a clean output transition. Bottom panel shows a hysteresis loop transfer curve with two switching points. Time-domain readout Static transfer view VIN t VTH+ VTH− VOUT VHYS VOUT VIN VTH+ VTH−

Built-in vs external hysteresis: what stays constant, what moves with VDD and temperature

“Built-in VHYS” is fast to use, but its value may change with VDD, temperature, and input structure. “External VHYS” is more controllable because it is set by resistor ratios and reference levels, but it introduces new error sources such as bias/leakage × source resistance and resistor tolerance.

A) Common built-in VHYS models (how to think about drift)

Fixed-voltage VHYS
VHYS behaves like a roughly fixed mV number across VDD. It can still move with temperature and input stage conditions, so worst-case margins must include drift.
VDD-ratio VHYS
VHYS scales with VDD (or changes in steps vs VDD). Low-voltage designs may see “more spread” or “less margin” than expected if VHYS is supply-proportional.
Symmetric vs asymmetric
VTH+ and VTH− may not be centered. This matters when “absolute threshold accuracy” is required: the switching direction can shift the apparent trip point.
Datasheet readout focus
  • Is VHYS specified as mV or as a fraction of VDD?
  • Are VTH+ and VTH− both provided, or only a single “VHYS typ”?
  • Is there a VDD or temperature dependence graph / range?

B) External VHYS is controllable, but adds error sources

Bias/leakage × resistance
Input bias or leakage current flowing through source/divider resistance shifts the threshold. This grows with temperature and with high-value resistors.
Resistor tolerance & TC
The resistor ratio sets both VHYS and the threshold center. Tolerance and tempco move both; high precision thresholds require worst-case ratio analysis.
Reference source impedance
A “soft” reference node can be modulated by the feedback network, creating direction-dependent jitter and drift. Buffer or lower node impedance if needed.
Practical mitigations
  • Keep divider/feedback node impedance reasonable; avoid “MΩ-first” designs unless leakage is proven small.
  • Use stable resistor ratios (matched network) when threshold accuracy matters.
  • Buffer/filter the reference node if feedback can inject noise into the threshold.

C) Selection rules: threshold accuracy vs anti-chatter robustness

Accuracy-first
  • Prefer external VHYS with a controlled reference.
  • Model Ibias/leakage × R and ratio tolerance as threshold error.
  • Verify VTH+ / VTH− across VDD and temperature corners.
Robustness-first
  • Built-in VHYS is acceptable if its corner drift is validated.
  • Expect VHYS to vary with VDD if supply-proportional.
  • If slow edges dominate, prioritize VHYS and then tune RC / source impedance.

When the design cannot tolerate direction-dependent switching error, treat VHYS as a parameter that must be computed + verified, not merely “assumed from typ”.

Built-in versus external hysteresis implementation blocks Block diagram showing a comparator core with two hysteresis implementations: built-in internal feedback block and external resistor feedback loop, with drift sources VDD, temperature, and bias times resistance. Comparator core VIN VREF VOUT Built-in VHYS internal feedback fixed / ratio sym / asym External VHYS resistor feedback R1 Rf R2 Drift sources VDD Temp Ibias × R Ratio tolerance

Threshold math (external VHYS): compute VTH+ and VTH− step-by-step

External hysteresis is created because the threshold node depends on the output state. The output can be near VOH or VOL, so the switching condition must be solved twice: once for the rising direction (VTH+) and once for the falling direction (VTH−). The hysteresis is then VHYS = VTH+ − VTH−.

A) Canonical non-inverting threshold + positive feedback (symbol map)

  • VIN drives the + input.
  • The − input sees a threshold node formed by VREF and feedback from VOUT.
  • R1, R2, Rf set both the threshold center and VHYS.
  • VOH and VOL must match the real output swing (including load or pull-up).

B) Reusable template: solve the same node twice (VOH vs VOL)

Step 1: write the threshold node
Treat the − input node as a resistive mix of VREF and VOUT. The weights are set by the resistor network.
Step 2: rising threshold (VTH+)
Assume the output is in the state that applies during a rising crossing, substitute VOUT = VOH (or the relevant state), then solve the equality condition VIN = V(−node) to get VTH+.
Step 3: falling threshold (VTH−)
Repeat the same solve for the falling direction with VOUT = VOL (or the relevant state) to obtain VTH−.
Step 4: compute the two design outcomes
  • VHYS = VTH+ − VTH− (noise-tolerant band).
  • Center (direction-averaged trip) must land where the system expects; otherwise VHYS may be correct but the whole window shifts.

C) Reverse design flow (from a target VHYS to resistor values)

  1. Pick a node impedance range: choose resistor magnitudes that do not amplify leakage/bias into large threshold shifts.
  2. Set a ratio for VHYS: adjust the feedback ratio so the computed VTH+ − VTH− matches the required noise margin.
  3. Re-center the threshold: tune the divider/reference so the band is centered on the desired trip region.
  4. Corner-check VOH/VOL: include load and pull-up; the output swing directly moves VTH+/VTH−.
  5. Corner-check Ibias × R and tolerance: treat these as additional threshold error that must fit inside the allowed band.

If the computed VHYS works only with “typ” VOH/VOL or with “zero leakage” assumptions, the design is not robust.

D) Why measured thresholds differ from math (must be budgeted)

Input bias / leakage
Turns resistor values into voltage error. The drift is often temperature dependent, so verify with a temperature sweep and worst-case node impedance.
Source resistance (Rsource)
If VIN is not a stiff voltage source, Rsource participates in the threshold equation and shifts both VTH+ and VTH−. Use a lower source impedance or buffer if needed.
Reference output impedance
A soft VREF node can be pulled by feedback currents, turning output noise into threshold noise. Reduce impedance or buffer the reference node.
External hysteresis threshold network for VTH+ and VTH− computation Circuit block diagram showing a comparator with VIN on the non-inverting input, a threshold node on the inverting input formed by VREF and feedback from VOUT through R1, R2, and Rf. Labels indicate VTH+, VTH−, VOH, and VOL. Comparator + − VIN VTH node VTH+ / VTH− VREF R1 R2 VOUT VOH VOL Rf Compute VTH twice: VOH case and VOL case

How to size VHYS: noise, ramp rate, and false-trigger probability (a practical workflow)

VHYS is best sized as a margin budget, not as a guessed “typical” number. The input sees a mixture of random noise (σ) and deterministic disturbances (ripple / ground bounce / injected charge). A slow ramp increases the time spent near threshold, raising the chance of multiple crossings. The workflow below converts these effects into a VHYS target, then checks the cost as an error band and missed-trigger risk.

Step 1 — Estimate input disturbance at the comparator pin

  • Random noise: use σ (rms) near the threshold region.
  • Deterministic: peak ripple / ground bounce / injected transients (treat as peak).
  • Measure at the comparator input node, not only at the source.
Output: σ_noise and A_disturb_peak

Step 2 — Choose a false-trigger tolerance using k·σ (not a single magic number)

Convert random noise into a peak-like margin using a selectable factor k. Larger k reduces false triggers but increases the error band and missed-trigger risk.

Rule of thumb representation
Random-noise margin ≈ k · σ_noise

Step 3 — Account for slow ramp: time-in-band increases crossing opportunities

  • Lower dV/dt near the threshold means longer time-in-band.
  • Propagation / filter delays extend the effective “linger window”.
  • Slow edges are often the hidden reason why tiny noise becomes repeated toggles.
Output: a slow-ramp margin term to be added to the VHYS budget.

Step 4 — Synthesize VHYS_min, then check missed-trigger and error-band cost

Budget form
VHYS_min ≥ (k·σ_noise) + A_disturb_peak + slow-ramp margin + guardband
Mandatory checks
  • Missed trigger: the signal must still cross VTH+ / VTH− under worst-case amplitude.
  • Error band: direction-dependent threshold range must fit the system requirement.
  • Center shift: VHYS may be right while the threshold center drifts out of spec.

Step 5 — Convert VHYS to resistor ratios and validate worst-case corners

  • Use the threshold math template to map VHYS_target → R ratios.
  • Corner-check VOH/VOL (load / pull-up), resistor tolerance, temperature drift.
  • Include Ibias/leakage × R and reference-node impedance as additional threshold error.

A robust design satisfies VHYS_min and the threshold center range under worst-case conditions, not only at typical room temperature.

VHYS sizing budget: noise, ripple, slow-ramp margin, and guardband Stacked budget bar showing contributions from k-sigma noise, ripple and ground bounce, slow-ramp margin, and guardband that sum to a VHYS target. Includes check boxes for missed-trigger and error-band checks. VHYS margin budget → target Noise (k·σ) Ripple / bounce Slow ramp GB VHYS target Mandatory checks Missed-trigger Error band Center shift Inputs to the budget σ_noise, ripple peak, dV/dt delay, guardband

Slow ramp & chatter: why transitions linger and how hysteresis interacts with RC

Slow ramps create chatter because the input spends a long time near the threshold. During this “linger” window, even small noise can cross the threshold many times. Hysteresis adds a voltage band (VTH+ / VTH−) so noise can move inside the band without toggling the output. RC filtering can reduce noise, but it also reduces slope and adds delay—often making the linger problem worse if used as the primary fix.

A) Mechanism: long time-in-band + noise crossings → multiple toggles

  • Low dV/dt makes the threshold region “wide in time”.
  • Noise adds repeated crossings when only a single threshold point exists.
  • VHYS turns that point into a band, preventing multi-toggling.

B) RC and VHYS are not interchangeable

RC benefit
Reduces high-frequency noise amplitude and short glitches.
RC cost
Slows edges (lower dV/dt) and adds delay, which can extend time-in-band.

C) Practical tuning order: VHYS first, then minimal RC

  1. Measure chatter under the slowest expected ramp (count extra pulses).
  2. Increase VHYS until multi-toggling disappears with margin.
  3. If short glitches still trigger, add the smallest RC that removes the glitch energy.
  4. Re-check response delay and missed-trigger risk across temperature and VDD.
Slow ramp chatter versus hysteresis band Two-panel waveform diagram. Left shows slow ramp with noise crossing a single threshold causing multiple output pulses. Right shows the same ramp with VTH+ and VTH− hysteresis band producing a clean single transition. Includes a simple knob row for VHYS and RC. No (or tiny) VHYS With VHYS band VIN VOUT VTH VIN VOUT VTH+ VTH− VHYS Knobs VHYS band RC filter VHYS first → RC minimum

Error vs robustness: VHYS creates an accuracy band and timing skew

Hysteresis improves robustness by preventing chatter, but it also creates two costs that must be written into system specifications: (1) an accuracy band because VTH+ and VTH− are different, and (2) a timing skew because the effective overdrive at the switching instant changes with the threshold band. Designs that need an exact trip point or tight edge timing must keep VHYS bounded.

A) Accuracy band: the trip is direction-dependent (VTH+ vs VTH−)

  • There is no single “threshold point”. Rising and falling transitions use different thresholds.
  • VHYS turns the trip into an interval, so the system must tolerate a direction-dependent band.
  • When absolute thresholds matter, budget: accuracy band + offset/drift + node errors.
Spec-ready wording
“Trip is direction-dependent: VTH+ and VTH− define an accuracy band; the system must tolerate the band width under worst-case conditions.”

B) Timing skew: VHYS changes overdrive, which changes propagation delay

For a given input slope, moving the effective threshold shifts the crossing time. At the same time, the overdrive at the decision instant changes, and propagation delay typically depends on overdrive—especially in fast paths where small overdrive can slow and spread the timing.

  • Voltage-domain cost: a wider band increases direction-dependent trip uncertainty.
  • Time-domain cost: the crossing happens earlier/later, and delay can change with overdrive.
  • High-speed timing chains should treat VHYS as a timing-budget parameter, not only a noise knob.

C) When VHYS must be small (accuracy or timing sensitive)

Precision window / exact trip
VHYS directly becomes an error band. If the allowed threshold error is smaller than the band, VHYS must be reduced or the front-end noise must be lowered.
Closed-loop timing sensitive
Trigger timing shifts can alter effective phase and delay. VHYS should be tuned with the loop’s worst-case timing budget.
Edge capture / ToF / timestamp
Threshold placement and overdrive-dependent delay both translate into time error. Validate timing across VDD, temperature, and input slope.
VHYS trade-off: wider accuracy band and larger timing shift Waveform diagram showing one input ramp and two hysteresis settings. Small VHYS produces a narrow VTH+ and VTH- band with small timing shift; large VHYS produces a wider band with a larger timing shift. Brackets mark Delta V and Delta t. VIN VTH+ (small) VTH− (small) VTH+ (large) VTH− (large) ΔV (band) t_small t_large Δt (timing skew) Accuracy band Timing skew Bound VHYS when accuracy/timing is tight

External hysteresis pitfalls: bias current × source R, leakage, and resistor tolerance

External VHYS can be precise only if the threshold node behaves like the math assumptions. In practice, tiny bias or leakage currents can create large threshold shifts when combined with high source or divider resistance. Resistor ratio drift moves both VHYS and the threshold center, and a noisy or high-impedance reference can turn the threshold into a jitter source.

Error mapping 1 — Ibias / leakage × resistance → threshold drift (ΔVTH)

Injection
Bias or leakage current flows through Rsource and threshold-node resistances.
Impact
Direction-dependent center shift that worsens with temperature; high-value resistors amplify the error.
Actions
  • Lower node impedance (avoid MΩ-first designs).
  • Buffer the source if Rsource cannot be reduced.
  • Verify with temperature sweep under worst-case humidity/contamination.

Error mapping 2 — Resistor ratio drift → ΔVHYS and center shift

Injection
Tolerance and temperature coefficient shift the resistor ratio that defines VHYS and the threshold center.
Impact
VHYS can be correct at room temperature but drift out of range across corners; the trip center can shift even when VHYS looks stable.
Actions
  • Use matched resistor networks for ratio stability.
  • Budget ratio tolerance/TC as threshold error, not as a “nice-to-have”.
  • Verify VTH+ and VTH− corners, not only VHYS typ.

Error mapping 3 — VREF noise / impedance → threshold jitter

Injection
A noisy or high-impedance reference node is modulated by feedback currents.
Impact
Threshold becomes a jitter source, increasing false-trigger probability even when VHYS is large.
Actions
Lower the node impedance, buffer/filter VREF, and keep the threshold node local and clean.
External hysteresis error injection paths Block diagram showing a central threshold node with three error injection paths: Ibias/leakage through resistance causing delta Vth, resistor tolerance causing delta VHYS and center shift, and reference noise/impedance causing jitter. Output boxes show center shift, band width change, and timing jitter. Threshold node VTH Ibias / leakage × Rsource ΔVTH R tolerance ratio drift ΔVHYS VREF noise / Zref Center shift Band width change Timing jitter

Built-in hysteresis characterization: how to read datasheets and what they omit

Datasheets often list VHYS as a simple number, but the switching behavior is defined by VTH+ and VTH− under specific conditions. Many parts provide only typical values and omit worst-case drift versus VDD, temperature, source impedance, and output loading. Treat built-in VHYS as a verify-required parameter unless min/max and corner conditions are explicitly stated.

A) Common datasheet formats for built-in hysteresis

  • VHYS (typ): a single typical band width, often without min/max.
  • VTH+ / VTH−: rising and falling switching thresholds (sometimes only one direction is shown).
  • Test conditions: VDD, temperature point, input waveform and source impedance, output load or pull-up.
  • Switching curve (if present): can hint symmetry, but rarely provides worst-case corners.

B) Readout traps: what “VHYS” may not guarantee

Typical only
If min/max is missing, VHYS cannot be treated as a guaranteed specification without validation.
No VDD / temp drift
The band width and center can shift across VDD and temperature, especially at low-voltage rails.
No symmetry statement
Without VTH+ and VTH− (or a curve), the band may be non-centered and direction-dependent.
Hidden circuit conditions
Input source impedance and output load/pull-up can change real switching behavior even with “built-in” hysteresis.

C) Engineering strategy: treat VHYS as verify-required (minimum checklist)

Record
Measure VTH+, VTH−, VHYS, and threshold center.
Sweep
Run corners for VDD (min/typ/max) and temperature (low/room/high).
Vary conditions
Change source impedance and pull-up/load to match the real system.
Robustness
Validate chatter behavior with slow ramps and injected ripple/noise near the band.

If a datasheet omits min/max and corner dependencies, the only safe assumption is “typical only”.

Datasheet VHYS fields mapped to engineering meaning and omissions Three-column mapping diagram. Left shows common datasheet fields such as VHYS typ, VTH+ and VTH-, and test conditions. Middle shows engineering meaning such as band width and direction-dependent trip. Right shows what is often omitted such as no min/max, no VDD or temperature drift, and no source impedance or pull-up corners. Datasheet fields Engineering meaning Often omitted VHYS (typ) VTH+ / VTH− Test conditions Band width Direction-dependent trip Depends on conditions No min / max No VDD / temp drift No Z / pull-up corners Treat VHYS as verify-required

Measurement & validation: capture VTH+, VTH−, chatter rate, and worst-case corners

Validation should prove two things: (1) the switching thresholds VTH+ and VTH− (and therefore VHYS and center) remain within limits across corners, and (2) the design does not false-trigger under the worst expected slow ramp and injected disturbance. Use a repeatable test script so the results are comparable across boards and lots.

1) Measure VTH+ and VTH− with a slow ramp (or slow triangle)

  • Drive a slow triangle/ramp into the DUT input, and probe VIN at the DUT pin and VOUT simultaneously.
  • Use VOUT as the trigger; record VIN at the moment VOUT switches.
  • Extract VTH+ (rising) and VTH− (falling), then compute VHYS and center.

2) Chatter test: inject controlled disturbance near the band and count toggles

Setup
Bias the input near the threshold region and inject ripple/noise with adjustable amplitude.
Metric
Count extra output toggles per crossing (or a false-trigger rate) using a scope counter or pulse counter.

3) Worst-case corners: VDD, temperature, source impedance, pull-up/load

Sweep axes
Temperature (low/room/high), VDD (min/typ/max), Rsource (low/med/high), pull-up/load (light/heavy).
Record set
VTH+, VTH−, VHYS, center, plus a chatter metric at the worst-case corner.
Pass criteria
VHYS_min ≥ requirement, center within limits, and no false triggers under injected disturbance.

4) Avoid measurement artifacts: probe capacitance and ground inductance

  • Use a short ground spring (or coax-style probing) to avoid fake ringing.
  • Probe VIN at the DUT pin; long leads can change the effective RC and the observed chatter behavior.
  • If behavior changes significantly when probing, treat it as probe loading first, not as a design conclusion.
VHYS measurement setup: ramp, injection, DUT, scope and counter Block diagram showing a signal source generating a slow ramp or triangle, an optional disturbance injection block, a divider or RC and source impedance block, the DUT comparator, and measurement instruments including oscilloscope and counter. Corner sweep tags list temperature, VDD, source impedance, and pull-up or load. Signal source slow ramp Disturb injection noise / ripple Rsource / RC divider DUT comparator Oscilloscope Counter Probe VIN & VOUT Corner sweep Temperature VDD Rsource Pull-up / load Short ground / low-C probing to avoid fake ringing

Engineering checklist (copy/paste): VHYS design review + bring-up tests

Use this checklist to lock hysteresis requirements into measurable acceptance criteria. Each line includes a Check, a measurable Threshold, and a concrete Action. Keep the scope strictly hysteresis-centric: VHYS sizing, threshold drift, chatter immunity, and corner validation.

A) Design review checklist (VHYS-centric)

Check Threshold Action
Requirement statement is measurable Defines: allowed band, allowed false-trigger rate, and allowed timing skew (if timing-sensitive) Rewrite requirements into pass/fail metrics before choosing VHYS
VHYS budget complete (noise + ripple + slow ramp) VHYS_min ≥ (Noise_pk + Ripple_pk + Ramp-linger margin) × Guardband Increase VHYS or reduce coupling; treat slow-ramp linger as a first-class budget term
Accuracy band acceptable VHYS_max ≤ allowed error band (and any phase/time error equivalent) Reduce VHYS or re-define the detection method if absolute trigger point is critical
Threshold center stays within the intended window Center = (VTH+ + VTH−)/2 remains within system limits across corners Adjust divider/feedback ratio; lower impedance; buffer the source if needed
Bias/leakage-induced shift bounded |Ibias|max × Rsource|max ≤ allowed center shift (include board leakage worst-case) Lower R, add guard/cleanliness, conformal coat, or add a buffer stage
Resistor tolerance + TC accounted (external hysteresis) Worst-case VHYS_min and center are valid across Rtol and temperature drift Tighten tolerance/TC, reduce ratio sensitivity, or calibrate at production if allowed
VDD dependency captured VTH+/VTH− and VHYS remain within limits at VDD_min and VDD_max Prefer implementations with stable thresholds, or re-center using an external reference
RC interaction understood (if present) RC does not push response time beyond system limit and does not create “linger” risk Size VHYS first, then add only the minimum RC required for noise shaping
Open-drain pull-up corner included (if open-drain) No chatter/regression across pull-up values and bus capacitance extremes Reduce pull-up, improve edge conditioning, or increase VHYS with bounded accuracy impact
Verification plan exists before layout freeze Defines test waveform, probes, corners, and pass/fail acceptance criteria Do not rely on “typical VHYS”; treat VHYS as verify-required unless guaranteed

B) Bring-up tests (lab script)

Check Threshold Action
Threshold scan Measure VTH+, VTH−, VHYS, center (VIN at DUT pin) Fix probing first; then adjust divider/feedback or reduce Rsource
Chatter count near the band Extra toggles per crossing (or false-trigger rate) meets system target Increase VHYS or reduce injected coupling; re-check error band
Slow-ramp stress No multi-toggling during slow ramps at worst noise/ripple condition Re-size VHYS before adding heavy RC that breaks response time
Pull-up / load corner (open-drain) No regression across pull-up extremes and bus capacitance Change pull-up, edge conditioning, or VHYS; re-run chatter metric
Source impedance corner VTH center and VHYS remain within limits across Rsource changes Lower divider impedance, buffer the source, improve cleanliness/guarding
Touch / cable disturbance check No false toggles under realistic cable touch/move scenarios Increase VHYS or reduce coupling path; improve shielding and return path

C) Freeze criteria (design is “done”)

  • VHYS_min meets robustness budget across VDD and temperature corners.
  • Center stays inside the allowed threshold window across source-impedance and pull-up/load corners.
  • Worst-case corner meets the defined chatter metric (no multi-toggles / acceptable false-trigger rate).
  • Bring-up logs include test conditions, probe method, and pass/fail results for reuse.

D) Copy/paste template (fill in per project)

Check Threshold Action
[Fill] [Fill] [Fill]
[Fill] [Fill] [Fill]
[Fill] [Fill] [Fill]
VHYS engineering flow: define, budget, compute, corner, validate, freeze A simple six-step flowchart for hysteresis design: Spec, Budget, Compute, Corner, Lab validate, and Freeze. Each step includes a small set of key outputs. Spec metrics Budget noise Compute VTH/VHYS Corner VDD/T/Z Lab validate scan/count Freeze criteria Outputs VHYS budget sheet Corner test plan Bring-up log Pass/fail freeze note

Applications (hysteresis-centric recipes): wake-up, alarms, zero-cross, and edge shaping

Each recipe stays hysteresis-centric: how to think about VHYS, what to verify, and what commonly breaks. Example part numbers are starting points for datasheet lookup and bench validation; final selection must be driven by the VHYS workflow and corner tests.

1) Battery wake-up / threshold wake

  • VHYS goal: stop ripple and load-step noise from causing repeated wake pulses.
  • Size logic: VHYS_min ≥ (battery ripple_pk + coupled noise_pk + slow-ramp linger margin) × guardband.
  • Main pitfall: mega-ohm dividers save power but amplify bias/leakage errors and drift.
  • Verify: scan VTH+/VTH− at VDD_min/max and T_low/high; run chatter count near the band.
  • Example parts: TI TLV3691 (nanopower comparator), ADI LTC1540 (reference + programmable hysteresis).

2) Open-drain alarm line (wired-OR, cross-domain pull-ups)

  • VHYS goal: prevent slow rising edges (large pull-up + bus C) from lingering near thresholds and chattering.
  • Size logic: size VHYS first for noise immunity; then add only minimal RC if required.
  • Main pitfall: pull-up value and bus capacitance are real corners; “lab looks fine” is not sufficient.
  • Verify: sweep pull-up and bus capacitance; count extra toggles per crossing.
  • Example parts: TI TLV3011 (open-drain + reference), TI TLV4082-Q1 (open-drain + integrated reference + internal hysteresis), onsemi LM393 (open-collector baseline).

3) Zero-cross / phase detect (mains or AC sync)

  • VHYS goal: suppress noise at the crossing while bounding phase error caused by the hysteresis band.
  • Size logic: choose VHYS_min from noise; cap VHYS_max from allowable time/phase error (band → time shift).
  • Main pitfall: oversizing VHYS reduces chatter but moves the effective trigger point too far.
  • Verify: inject ripple/noise near crossing and measure trigger time spread at worst corners.
  • Example parts: onsemi LM393 (external hysteresis baseline), TI TLV3201 (higher-speed comparator family reference point).

4) Encoder / edge shaping (slow sensors, long cables)

  • VHYS goal: convert slow/noisy edges into clean logic transitions and prevent double-count events.
  • Size logic: set VHYS_min from cable-coupled noise_pk; keep VHYS bounded to avoid large timing skew.
  • Main pitfall: heavy RC “debounce” can create delay and duty distortion; rely on VHYS first.
  • Verify: slow ramp + injected noise; count edges and confirm stable state changes.
  • Example parts: TI SN74LVC1G17 (Schmitt-trigger buffer, direct logic interface).

5) Custom brown-in / brown-out window (supervisor-like behavior)

  • VHYS goal: define a stable power-valid window and avoid on/off oscillation near the threshold.
  • Size logic: VHYS_min ≥ (rail ripple_pk + load-step droop/overshoot_pk) × guardband; VHYS_max ≤ allowed window width.
  • Main pitfall: divider impedance and leakage can shift the window center at low voltage rails.
  • Verify: power ramp up/down across VDD corners; run chatter count at the worst corner.
  • Example parts: TI TLV6703 (1.8–18 V monitor comparator with internal reference, open-drain), TI TLV3011 (reference-based threshold starting point).

Reference examples (part numbers; starting points only)

These part numbers speed up datasheet lookup and bench validation. Selection must be driven by VHYS requirements, error-band constraints, and corner measurements.

  • Ultra-low power wake / threshold: TI TLV3691, ADI LTC1540
  • Open-drain alarm line: TI TLV3011, TI TLV4082-Q1, onsemi LM393
  • Higher-speed timing / zero-cross reference point: TI TLV3201
  • Logic-level edge shaping: TI SN74LVC1G17
  • High-voltage rail monitoring: TI TLV6703
VHYS application map: five use-cases and the hysteresis focus point A central VHYS knob connects to five application boxes: Wake-up, Open-drain alarm, Zero-cross, Encoder shaping, and Brown-in/out. Each box lists two hysteresis focus keywords. VHYS knob Wake-up ripple · leakage OD alarm line pull-up · slow rise Zero-cross symmetry · phase Encoder shaping cable noise · edges Brown-in/out window · stability

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FAQs: Hysteresis (VHYS) — short, actionable, and measurable

These FAQs only cover VHYS: threshold band behavior, chatter immunity, drift/error injection, and quick validation. Each answer uses a fixed data structure: Trigger → Check → Threshold → Action.

1 Built-in VHYS is “typ only” (no min/max). How to do worst-case?
Trigger: Field chatter or missed events are suspected, but VHYS is only specified as “typ”.
Check: Locate the test condition (VDD, temperature, input source impedance) and any VTH+/VTH− curves; verify whether symmetry and VDD scaling are stated.
Threshold: Treat VHYS as verify-required: define VHYS_min for robustness and VHYS_max for allowed error band; both must hold across corners.
Action: Run a corner sweep: (VDD_min/max) × (T_low/high) × (Rsource, pull-up/load extremes). Measure VTH+/VTH− and chatter count; if fails, move to external hysteresis or a part with guaranteed limits.
2 Why does the same Schmitt gate threshold look “more floating” at 1.8 V? Which two items to check first?
Trigger: Threshold varies noticeably board-to-board or over time at low VDD.
Check: (1) Guaranteed VTH+/VTH− (or VIH/VIL) at 1.8 V (not typ). (2) Input leakage/bias vs allowed source impedance (or input current conditions).
Threshold: Ensure VHYS / Noise_pk remains comfortably > 1 at the lowest VDD; if the guaranteed threshold band is wider than the allowed system window, instability is expected.
Action: Lower source impedance, reduce coupled noise, or move to external hysteresis with a fixed reference/ratio; validate with VTH+/VTH− scan at VDD corners.
3 External hysteresis uses MΩ resistors. What happens, and how to tell Ibias vs leakage?
Trigger: Threshold center drifts or becomes humidity/touch sensitive after using very large resistors.
Check: Use the “resistor scaling” test: change the effective resistance by ~2× while keeping topology; observe whether threshold shift scales similarly. Compare clean/dry vs humid/contaminated conditions.
Threshold: Estimate drift: ΔV ≈ I_error × R_eq. If a small I_error (nA-level) yields an unacceptable ΔV at MΩ, the design is impedance-limited.
Action: Reduce impedance by 10× (typical first fix), add guarding/cleanliness/conformal coat, or buffer the node. Re-run VTH+/VTH− scan and chatter test.
4 Slow ramp input chatters. Add VHYS first or RC first? What is the criterion?
Trigger: Multiple toggles appear when the input crosses slowly through the threshold region.
Check: Estimate threshold “linger time”: t_linger ≈ VHYS / (dVIN/dt). If t_linger is long, noise has many chances to re-cross.
Threshold: Set VHYS_min ≥ k · Noise_pk (k is the robustness factor). Only then add RC if a specific noise component still dominates.
Action: Size VHYS first; then add the minimum RC that reduces the offending coupling without violating response time or creating extra delay-related misses.
5 VHYS increased, but trigger time is later (or time jitter looks worse). How to verify “overdrive” is the reason?
Trigger: A larger hysteresis band changes timing behavior in a timing-sensitive chain.
Check: Log trigger time distributions at two VHYS settings using the same input waveform; also compute the effective crossing point shift.
Threshold: If Δt ≈ ΔV_cross / (dVIN/dt) matches the observed delay shift, the change is dominated by the moved crossing point (overdrive distribution).
Action: Cap VHYS_max using the allowed time error budget, or increase edge slope/reduce noise to keep a smaller VHYS while meeting chatter targets.
6 Open-drain pull-up: how to choose Rpull so it does not chatter, but still saves power?
Trigger: Large pull-up values cause slow edges and multi-toggling near thresholds.
Check: Estimate rise time: t_r ≈ 2.2 · Rpull · Cbus. Treat (Rpull, Cbus) as corners and validate at extremes.
Threshold: t_r must be below the system’s allowed edge/linger limit, and VHYS / Noise_pk must remain above the robustness target.
Action: First pick Rpull to satisfy timing; then use VHYS to handle residual noise. If power is still too high, reduce coupling or edge-load rather than pushing Rpull into the chatter region.
7 VHYS is too large and causes missed events. How to back-calculate a reasonable range from a noise budget?
Trigger: Robustness improves, but the detection window becomes too wide and misses valid crossings.
Check: Build a two-sided window: compute VHYS_min from noise/ripple/slow-ramp linger, and VHYS_max from allowed error band (or timing error).
Threshold: Must satisfy VHYS_min ≤ VHYS ≤ VHYS_max. If VHYS_min > VHYS_max, constraints conflict.
Action: Reduce coupling/noise, increase slope, lower impedance, or re-center the threshold so a smaller VHYS still meets chatter targets.
8 Datasheet VHYS test circuit differs from the real source impedance. How much can thresholds shift?
Trigger: Bench thresholds do not match expectations even when the part is “correct”.
Check: Compare datasheet test Rsource to real Rsource and identify the dominant error current (bias + leakage + board leakage worst-case).
Threshold: First-order estimate: ΔVth ≈ I_error · (Rsource_real − Rsource_test). If ΔVth is not negligible, measurement is required.
Action: Include Rsource as a corner in validation; lower impedance or buffer the node if the system window cannot tolerate the shift.
9 How to quickly measure VTH+ and VTH− in the lab without specialized instruments?
Trigger: VHYS needs verification, but only a function generator and oscilloscope are available.
Check: Apply a slow triangle/ramp into the DUT input pin; trigger the scope on output transitions; read VIN at the switching instant (use short ground spring and minimize probe loading).
Threshold: Repeatability must hold across repeats and corners (VDD, temperature, Rsource). Large variation indicates loading/coupling dominates the observation.
Action: Fix probing first, then repeat. Record VTH+/VTH−, compute VHYS and center, and run a short chatter stress near the band.
10 Schmitt gate VHYS vs comparator with external hysteresis: when is the latter required?
Trigger: The application needs an accurate threshold center or a predictable window across VDD/temperature.
Check: Determine whether the system needs (a) an absolute threshold tied to a reference, (b) adjustable VHYS/center, or (c) guaranteed min/max limits.
Threshold: If allowed threshold error band is smaller than the guaranteed logic-threshold band (or guarantees are missing), a reference/ratio-controlled external hysteresis is required.
Action: Use a comparator + external feedback with controlled impedance and a defined validation plan; measure VTH+/VTH− across corners to freeze the design.
11 Does hysteresis “filter noise”? Why can chatter still happen with VHYS?
Trigger: VHYS is present, but occasional false toggles still appear.
Check: Identify whether noise amplitude occasionally exceeds the band (rare spikes), or whether slow ramp linger creates repeated crossings inside the band.
Threshold: Robustness requires VHYS_min ≥ k · Noise_pk for the dominant disturbance, and t_linger must not be long enough to allow many re-cross opportunities.
Action: Increase VHYS (bounded by error band) and/or reduce spikes at the source; if linger dominates, increase slope or reduce coupling before adding heavy RC.
12 Built-in VHYS changes with VDD/temperature. How to decide if external hysteresis is needed?
Trigger: A stable threshold band is needed, but VHYS/thresholds appear supply- or temperature-dependent.
Check: Determine whether VHYS is specified as fixed voltage, VDD-proportional, or “typ only”; check if center drift is specified or must be measured.
Threshold: If (VHYS_min at worst corner) fails robustness, or (center/VHYS_max at worst corner) violates the allowed error band, built-in hysteresis is insufficient.
Action: Switch to external hysteresis with controlled resistor ratios and bounded impedance (and/or a stable reference), then validate VTH+/VTH− across corners before freeze.
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