Adding Hysteresis to a Comparator (VTH+ / VTH− Design)
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Adding hysteresis turns a noisy, slow-moving threshold into two deterministic trip points that you can calculate, guardband, and verify. This page shows how to compute VTH+/VTH−, choose resistor values safely (including source-R and bias/leakage), and measure the real thresholds on the bench.
What this page solves
Adding hysteresis turns a noisy or slow-changing threshold into two deterministic trip points (VTH+ and VTH−) that can be measured, guarded, and reproduced across temperature and load.
Common failure modes this page fixes
- Likely cause: a single threshold is crossed repeatedly by noise while the input dwells near the transition.
- What breaks: double-count edges, spurious interrupts, false alarms, unstable state machines.
- Likely cause: Rs, Ib, Ileak, and real VOH/VOL shift the effective threshold node.
- What breaks: window limits, brown-in/brown-out points, calibration assumptions, margin.
- Likely cause: hysteresis is computed with ideal rails, but the board sees non-ideal output swing and input loading.
- What breaks: nuisance faults or missed faults under temperature, supply ripple, or load changes.
What this page delivers (copyable engineering outputs)
Compute VTH+ and VTH− using real output swing (VOH/VOL) and resistor ratio, then apply guardband for tolerance and temperature.
Start with a VHYS target → pick resistor ratio → pick absolute resistance range that keeps Ib×R and Rs-loading errors below the allowed threshold shift.
Account for Rs, Ib, Ileak, VOH/VOL, input clamps/leakage, and temperature coefficients—each maps to a measurable ΔVTH.
Sweep input up/down to measure VTH+/VTH−, add controlled noise/ripple to confirm no re-trigger, run temperature corners, then convert results into production pass/fail limits.
Next steps on this page: define terms precisely, then compute VTH+/VTH− with non-ideal effects (Rs, Ib, Ileak, real VOH/VOL) and verify using up/down sweeps across corners.
Definition: hysteresis, VHYS, VTH+ and VTH−
Hysteresis creates two switching thresholds rather than one. The rising transition occurs at VTH+, and the falling transition occurs at VTH−. Their difference is the hysteresis width: VHYS = VTH+ − VTH−
Terms that must stay consistent
- VTH+: the input level that triggers the output when the input is rising.
- VTH−: the input level that triggers the output when the input is falling.
- VHYS: the separation between the two trip points; it is not “noise margin” by definition, but it can be used as a noise margin when sized correctly.
- Measure or estimate the effective disturbance at the threshold node (noise + ripple coupling + ground bounce + spikes).
- Choose VHYS_target large enough that disturbances do not cross both thresholds during one event (a common starting point is several times the observed peak-to-peak disturbance, then refine by test).
- Verify by injecting ripple/noise and confirming no re-trigger when the input sits near the transition.
Common traps that cause “mystery” thresholds
- Assuming VOH = VDD and VOL = 0, then discovering real output swing shifts both trip points.
- Measuring only one sweep direction and calling it “the threshold” instead of separating VTH+ and VTH−.
- Using very large resistors while ignoring Ib×R and leakage, which can dominate the intended hysteresis.
- Taking noise at the signal source as the disturbance, while the real disturbance is at the threshold node due to coupling and ground bounce.
Hysteresis must be specified and verified using two sweep directions: rising to capture VTH+ and falling to capture VTH−. Any design step that changes the threshold node (output swing, source resistance, bias/leakage, clamps) shifts these points and must be included in the sizing and guardband.
Principle: positive feedback creates two stable states
Positive feedback makes the decision boundary depend on the current output state. That is why a hysteretic comparator has two trip points: VTH+ for a rising input and VTH− for a falling input.
Two-state viewpoint (state machine)
- State S0: OUT = L. The feedback term is based on VOL, so the boundary is one line.
- State S1: OUT = H. The feedback term is based on VOH, so the boundary shifts to a second line.
- Key rule: the trip point is computed using the pre-transition output state (before the output flips).
Why the threshold is not a constant
The input node is a weighted mix of sources through resistors. A compact way to think about it is:
Thevenin intuition (engineering view)
- The feedback network makes the threshold node look like an equivalent source whose value depends on Vout.
- With OUT=L, the equivalent source is closer to VOL; with OUT=H, it is closer to VOH.
- The comparator flips when the node crosses the reference boundary, producing two distinct trip points.
This principle is the reason the next section computes trip points by writing one node equation and solving it twice: once with Vout = VOL and once with Vout = VOH.
Core equations: compute VTH+ and VTH−
The goal is a copyable method that produces VTH+ and VTH− using the real output swing (VOH/VOL). The same recipe works for both common external-hysteresis topologies; only the mapping of which output state applies to “rising” vs “falling” changes.
Unified recipe (one equation, solved twice)
- Write the threshold-node equation in weighted form: Vnode = a·Vin + b·Vref + c·Vout
- Apply the switching condition (ideal comparison boundary): Vnode = Vref (or the internal reference boundary).
- Solve for Vin twice: Vout = VOL gives one trip point; Vout = VOH gives the other.
- Assign results to VTH+ and VTH− using the rule below.
| Input sweep | Use Vout state | Trip point name |
|---|---|---|
| Vin rising | the output level before it flips | VTH+ |
| Vin falling | the output level before it flips | VTH− |
In a non-inverting threshold detector the rising trip typically uses VOL, while in an inverting configuration it often uses VOH. The equation is the same; the assignment differs.
Case A: non-inverting (Vin to +, Vref to −)
With Rin from Vin to the + node and Rf from Vout to the same node, the node voltage is the weighted mix:
Switching occurs when V+ = Vref, so:
Case B: inverting (Vin to −, Vref to +)
The inverting topology has the same weighted-node math at the − node, and switching occurs when V− = Vref. The important difference is the assignment of which output level applies to rising vs falling trips.
- VTH+ (Vin rising): often flips the output H → L, so use Vout = VOH as the pre-transition state.
- VTH− (Vin falling): often flips the output L → H, so use Vout = VOL as the pre-transition state.
If a specific implementation flips in the opposite direction, the assignment must follow the same rule: use the pre-transition output level.
Case C: non-ideal output swing (VOH ≠ VDD, VOL ≠ 0)
- Do not substitute VDD and 0 unless the output swing is guaranteed under the real load.
- Use the datasheet conditions (load current, pull-up, temperature) to pick worst-case VOH and worst-case VOL for threshold guardband.
- Then apply the same equations with those substituted values; hysteresis width scales with (VOH − VOL).
The next step is resistor sizing: pick a VHYS target, then choose a resistor ratio and an absolute resistance range that keeps source-R and Ib/leakage from shifting the computed thresholds beyond guardband.
Design workflow: from required VHYS to resistor values
Use the equations to land on practical resistor values. The workflow outputs VTH+/VTH−, a resistor ratio, and an absolute-value range that remains valid across corners.
5-step workflow (inputs → action → outputs)
- Inputs: noise/ripple/ground-bounce/sensor jitter seen at the threshold node.
- Action: pick a margin factor (typical 3× to 10× the disturbance peak-to-peak).
- Outputs: VHYS_target, margin factor.
- Inputs: corner values VOH(min) and VOL(max) under the real load/pull-up.
- Action: compute available swing: ΔVout = VOH − VOL.
- Outputs: ΔVout_corner.
- Action A (ratio): choose Rin/Rf to hit VHYS_target while placing VTH+/VTH− where needed.
- Action B (absolute): choose a resistance range that does not overload the source and does not amplify bias/leakage errors.
- Outputs: Rratio, initial Rin/Rf, and Rabs range.
- Inputs: input common-mode range VICR, intended input range, and computed thresholds.
- Action: verify both trip points and the pre-transition node voltages remain within VICR (especially near rails at low VDD).
- Outputs: pass/fail and the adjustment direction (change Vref, ratio, or part).
- Inputs: resistor tolerance/TC, VOH/VOL drift, Vref tolerance/TC.
- Action: compute VTH+_min/max and VTH−_min/max; then define guardband for production.
- Outputs: corner thresholds and a validation window.
Common pitfalls (fast checks)
- Using VDD/0 instead of real VOH/VOL under load.
- Choosing very large resistors first, then discovering Ib and leakage dominate threshold error.
- Targeting VHYS for noise only and ignoring ground-bounce or coupled spikes at the threshold node.
- Checking typical values only (no corners across temperature/load).
- Skipping a monotonic sweep test for both directions (no clean verification of VTH+ and VTH−).
Outputs recap (copy to the project notes)
- VHYS_target = disturbance_pp × margin_factor
- Rratio chosen to hit VHYS and place VTH+/VTH− correctly
- Rabs range chosen to limit bias/leakage error and source loading
- Corner thresholds: VTH+_min/max and VTH−_min/max
The next section converts non-idealities into an explicit ΔVTH budget to bound the guardband and resistor range.
Non-idealities: source-R, input bias/leakage, and a threshold error budget
Real thresholds shift because the input node is not ideal. Treat every non-ideality as an injected ΔVTH term, then budget the total shift before finalizing resistor values and production guardbands.
Source resistance (Rs): loading changes the divider ratio
- Mechanism: Rs adds series impedance to the Vin path, changing the effective weighting at the threshold node. This can shift both trip points and shrink the achieved VHYS.
- Worst-case inputs: Rs corner (sensor output impedance, divider source resistance, or upstream filter R), plus resistor tolerances.
- Budget form: treat the effect as ΔVTH_Rs and recompute thresholds with Rs included in the node equation.
- Lower the network impedance (reduce Rin/Rf absolute values) to make the node less sensitive to Rs.
- Buffer the source if Rs is unavoidable (keep the threshold node stiff).
- Recompute VTH+ / VTH− at Rs corners and add guardband before committing to values.
Input bias current (Ib): DC offset through the node resistance
- Mechanism: bias current through the node’s Thevenin resistance creates a DC voltage shift at the input, translating directly into a threshold shift.
- Worst-case inputs: Ib_max across temperature/process, and the effective node resistance seen by the input.
- Reduce Rabs (but keep source loading and power acceptable).
- Select a comparator with lower Ib corners when absolute thresholds matter.
- Re-allocate the VHYS/guardband if Ib-driven shift is a dominant term.
Input leakage / clamps: “hysteresis changed” symptoms
- Clamp conduction: protection diodes or internal clamps can conduct during overshoot/undershoot, pulling the node and shifting the apparent trip point.
- Environmental leakage: contamination/humidity can create leakage paths that behave like an extra current source at the node.
- Budget form: treat leakage as an injected current that creates ΔVTH through the node resistance.
- Lower node impedance so leakage produces less ΔVTH.
- Add current limiting and control overshoot to avoid clamp conduction.
- Verify with slow sweeps and environmental stress if leakage is suspected (repeatability matters more than a single run).
Error budget template (fill with datasheet numbers)
| Error source | Mechanism | Worst-case inputs | Worst-case estimate | Mitigation | How to verify |
|---|---|---|---|---|---|
| Rs | ratio change | Rs_max, R tolerance | ΔVTH_Rs (recompute) | reduce Rabs / buffer | sweep with Rs corners |
| Ib | DC shift | Ib_max, Rth | Ib_max · Rth | lower Rabs / better part | temp sweep |
| Ileak | node pull | Ileak_max, clamp events | Ileak_max · Rth | limit overshoot / lower R | repeat sweeps, env test |
A conservative total can be formed as ΔVTH_total = Σ |ΔVTH_i| and applied as guardband to the corner thresholds.
Slow ramp & chatter: combining hysteresis with RC debounce (without over-filtering)
Slow edges plus noise and short spikes are the most common reason a threshold circuit toggles more than once. Hysteresis stabilizes the decision boundary; RC suppresses high-frequency glitches. The design must control false toggles without creating excessive delay or “moving” thresholds.
Why slow ramps cause chatter (and sometimes extra power)
- Multiple crossings: when the input moves slowly through the decision region, small noise can cross the boundary repeatedly.
- Long dwell time: the longer the signal spends near the trip level, the more opportunities noise has to create extra edges.
- Downstream logic effects: a non-Schmitt digital input can draw higher current when held near its threshold (linear region), so slow edges can appear as “power spikes” during transitions.
- Record Vin slope at the threshold and count output edges per event.
- Measure supply current during the transition window to confirm “dwell-time” correlation.
Hysteresis vs RC: what each one solves
- Solves: noise-driven uncertainty around the boundary by creating two trip points (VTH+ / VTH−).
- Does not solve: very short spikes that jump over VTH+ briefly.
- Side effects: a wider decision window; absolute threshold targets must include error budget.
- Solves: high-frequency glitches by reducing their amplitude at the threshold node.
- Does not solve: a noisy slow ramp by itself if the boundary remains a single point (no VHYS).
- Side effects: adds delay and can amplify Rs/Ib/Ileak-driven threshold shifts via increased node impedance.
- Noise chatter on a slow ramp → add hysteresis first.
- Short spikes causing false edges → add RC after VHYS is set.
- Both present → VHYS for stability + RC for spikes, then budget delay and threshold error.
How to set RC (start from delay budget, then spike/noise targets)
- Define t_delay_budget from system timing.
- Use the worst-case input slope and corners (temperature/supply/loading).
- Keep RC-induced delay below the budget at the trip point.
- Identify glitch duration (pulse width) and the dominant noise band at the node.
- Choose τ so short spikes are attenuated enough that the node does not cross VTH+.
- Avoid choosing τ so large that normal edges become timing failures.
- RC increases the effective impedance seen at the input node in many real layouts.
- Re-check ΔVTH_Rs, ΔVTH_Ib, and ΔVTH_Ileak after adding RC.
- Update guardband with corner values before locking R and C.
Output swing matters: VOH/VOL, saturation, and topology notes (OD vs push-pull)
External hysteresis uses output feedback, so thresholds depend on the real output levels. Do not assume VDD and 0. Always use VOH(min) and VOL(max) under the real load and temperature corners.
Why VOH/VOL must be “real” (not ideal rails)
- Feedback amplitude: the effective hysteresis injection scales with ΔVout = VOH − VOL.
- Corners matter: lower VOH(min) or higher VOL(max) can shrink achieved VHYS and move both trip points.
- Action: compute VTH+ / VTH− using VOH(min) and VOL(max) at the same load and temperature assumptions used in the system.
OD vs push-pull: threshold drift paths (only what affects hysteresis math)
- VOH is external: determined by pull-up, load, leakage, and temperature; treat VOH(min) as a corner value.
- VOL is specified: use VOL(max) at the actual sink current corner.
- Implication: feedback injection varies with conditions → thresholds vary unless corners are budgeted.
- VOH/VOL are usually more defined for a given load, which helps keep thresholds predictable.
- Edge energy is higher: fast transitions and ground bounce can couple into the input node and appear as extra “noise” at the decision boundary.
- Implication: keep hysteresis sized for real node disturbances and verify on the PCB with worst-case switching activity.
Saturation / recovery: when “threshold shaping” looks wrong
- Observed symptom: large overdrive events or deep output states can show longer-than-expected recovery before the output becomes a clean logic level.
- Relevance here: if Vout is used in the feedback network, delayed or distorted VOH/VOL behavior can alter the apparent trip timing and the measured thresholds.
- Action: validate with worst-case overdrive and temperature; avoid design conditions that force deep saturation when timing/shape is critical.
- VOH(min) and VOL(max) at real load/pull-up corners
- Temperature corners used for those values
- Recomputed VTH+_min/max, VTH−_min/max, VHYS_min/max
- Basic timing checks: propagation and any recovery behavior relevant to the application
Protection & layout: clamps/series-R/TVS can shift thresholds
Input protection is not electrically “transparent”. Series resistance, clamps, and TVS devices can introduce leakage, capacitance, and ground-bounce coupling that change the effective threshold node and increase false triggers. The design must keep the protection benefits while preserving VTH+/VTH− predictability.
How series-R shifts thresholds (and why it can amplify leakage errors)
- DC shift path: any clamp/TVS leakage current creates a node error through resistance: ΔV ≈ Ileak × R(series-to-node).
- Hidden amplifier: larger resistance makes the threshold node more sensitive to Ib/Ileak, so “safe” protection can become a threshold-drift driver.
- Action: size series-R for protection needs, then re-check the worst-case threshold window using node Thevenin resistance.
- Repeat VTH sweeps at hot temperature to expose leakage-dominated shifts.
- Compare VTH results with and without the protection population (same board, same stimulus).
Clamps/TVS: leakage and capacitance change both DC threshold and false-trigger risk
- Corner behavior: leakage often rises strongly with temperature and board contamination, appearing as threshold drift.
- Worst-case estimate: use the maximum leakage at the relevant node voltage and temperature corner.
- Budget template: convert leakage into threshold shift using the node resistance.
- Fast transients: TVS/clamp capacitance and parasitics can couple fast edges into the threshold node.
- Observed symptom: false toggles with EFT-like spikes even when DC thresholds look correct.
- Action: verify with pulse/noise injection and measure whether the node crosses VTH+ under worst-case coupling.
Layout rules that directly improve threshold stability
- Keep the input loop small: short path from connector to the threshold node with tight return to reduce pickup.
- Keep the reference clean: avoid sharing sensitive comparator ground/reference return with high di/dt switching currents.
- Avoid asymmetric routing: asymmetry turns ground bounce into effective differential input noise, increasing the needed VHYS.
- Place protection intentionally: TVS close to the connector; keep the threshold node short, compact, and low-impedance.
Verification: how to measure real VTH+ / VTH− and hysteresis (bench + temp)
Calculations are only the first pass. The practical goal is to measure real trip points and hysteresis under the same conditions that define the application: VDD, temperature, load, VOH/VOL, and source impedance. The workflow below produces data that can be migrated into production screening.
Step 1 — Sweep up/down and log trip points (baseline bench method)
- Stimulus: drive the input with a slow monotonic ramp using a DAC, SMU, or a function generator with offset control.
- Trip logging: capture the exact input level when the output changes state on an up-sweep (VTH+) and on a down-sweep (VTH−).
- Debounce rule: count a trip only if the output remains stable for N consecutive samples (or for a minimum hold time).
Step 2 — Repeat across corners (temperature, VDD, load, VOH/VOL, Rs)
- Temperature points: cold / ambient / hot to reveal bias and leakage changes.
- Supply corners: repeat at minimum and maximum VDD used in the system.
- Output condition: record VOH/VOL under the real load or pull-up conditions (especially critical for open-drain).
- Input source impedance: repeat with worst-case Rs to bound the node error and settling effects.
Step 3 — Noise/ripple/spike stress: verify false-trigger rate
- Ripple test: add controlled ripple near the threshold region and check if the node crosses VTH− and returns, causing extra edges.
- Spike test: inject short pulses and log whether the threshold node briefly crosses VTH+.
- Metric: report a false-trigger count per time window or per input event count.
Engineering checklist + IC selection logic (fields → risk mapping → vendor questions)
This section turns “hysteresis math” into a repeatable tool: a prioritized checklist, a datasheet-field risk map, and vendor questions that prevent threshold drift, chatter, and false trips at corners.
A) Prioritized engineering checklist (tick-box ready)
- Reference: Vref accuracy / TC / noise → Record: Vref(min/max) at corners.
- Output swing: VOH(min)/VOL(max) under real load → Record: VOH/VOL vs load and temperature.
- Resistors: tolerance + tempco → Record: R ratio range (min/max).
- Bias/leakage: Ib/Ileak at temperature → Compute: ΔVTH = I × Rth(node).
- Source impedance: Rs worst-case → Check: Rs does not re-divide the hysteresis network.
- Noise/ripple at the node: estimate peak-to-peak at worst case → Set: VHYS margin (e.g., multiple of observed p-p).
- Ground bounce coupling: layout-driven effective input noise → Action: fix return paths before inflating VHYS.
- RC delay: t_delay vs system timing → Record: t_delay_meas at corners.
- False trigger metric: Report: false_trigger_rate (per time or per event).
- Series-R: does it raise Rth(node) and amplify Ib/Ileak errors?
- Clamp/TVS: Ileak vs temp/humidity → Compute: ΔVTH_leak.
- Capacitance: Cnode injects spikes → Verify: pulse test does not cross VTH+.
- Layout symmetry: asymmetric routing converts bounce to input noise.
- Sweeps: temperature sweep · supply sweep · load sweep · source-R sweep.
- Stress: ripple/noise injection · spike injection.
- Outputs: VTH+ · VTH− · VHYS · P-P jitter · false-trigger rate.
- Decision rule: define debounce criterion (stable N samples / hold time).
B) Selection logic: datasheet fields → risks → actions (guardband-friendly)
Each row below forms a closed loop. If a field is weak or poorly specified at corners, the risk becomes visible and the action becomes specific.
C) Vendor questions (copy-paste checklist)
- Ib vs temperature: min/typ/max at defined VIN and VDD.
- Input leakage vs temperature: Ileak(min/max) with VIN polarity and magnitude stated.
- VOH/VOL conditions: IOH/IOL, pull-up value (if open-drain), load type, and temperature corners.
- VICR / crossover behavior: behavior near rails and under overdrive; any known crossover region constraints.
- Built-in hysteresis guarantee: VHYS min/max across process and temperature (if present).
- Propagation delay vs overdrive: curve/table at small overdrive.
D) Reference part numbers (starting points only; verify corners)
The part numbers below are provided to accelerate datasheet lookup for hysteresis-based threshold design. Selection must be driven by the checklist and field-to-risk mapping above.
Application recipes (hysteresis-focused; copy-and-adapt)
Each recipe stays inside the “adding hysteresis” boundary: it shows when hysteresis is needed, the minimum wiring, the key numbers to fill, and concrete reference part numbers to speed up prototyping and vendor conversations.
Recipe 1 — Slow sensor threshold: avoid multi-trigger on noisy slow ramps
- Input crosses a threshold slowly and carries noise/ground bounce.
- Output shows multiple edges near the threshold region.
- Comparator + external positive feedback (Rf, Rin) to create VTH+ and VTH−.
- Optional small RC at the input only after delay budget is defined.
Recipe 2 — Brown-in / Brown-out: hysteresis window as a simple “valid power” detector
- Supply rises/falls through a noisy region and causes repeated resets or state toggles.
- Two trip points are required: enter-valid (VTH+) and exit-valid (VTH−).
- Divider + comparator reference + external hysteresis (or a window device if a two-limit detector is needed).
- Compute VTH+/VTH− using VOH(min)/VOL(max) and divider tolerance.
Recipe 3 — Noisy digital input cleanup: comparator hysteresis vs Schmitt buffer
- Long cable / slow edges / EMI spikes produce double edges in logic inputs.
- Threshold must be defined and stable across temperature and supply variation.
- Schmitt buffer: fastest, simplest digital cleanup when the input is already logic-domain.
- Comparator + external hysteresis: better when logic thresholds are not suitable or when level translation is needed.
Recipe 4 — Level translation threshold: open-drain + pull-up defines the logic-domain swing
- Analog threshold detection must drive a different logic voltage domain.
- VOH is defined by the pull-up rail and load, so VOH(min) must be used in VTH math.
- Open-drain comparator output + pull-up to the target logic rail (VOH depends on pull-up/load).
- External hysteresis network computed using VOH(min)/VOL(max) under the real load.
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FAQs (adding hysteresis) — short, actionable, data-structured
Each answer follows a fixed structure: Cause → Quick check (numbers/conditions) → Fix (one action). No diagrams. No scope creep beyond external hysteresis design.
