Sub-1V / nano-power comparators are only “real” when they stay output-valid on slow cold-start ramps and keep thresholds stable with mega-ohm dividers.
This page shows how to budget leakage and hysteresis, prevent cross-domain back-power, and verify false-wake rate with measurable pass/fail limits.
What this page solves (and what it does NOT)
This page focuses on Sub-1V / nano-power comparators used in energy-harvesting and always-on wake-up chains:
where cold-start ramps, high-impedance thresholds, and cross-domain outputs decide whether the system wakes reliably
or drains its stored energy.
What this page helps you build
Cold-start enable: turn on the main power stage only after the storage rail is truly usable.
Wake-up thresholds: detect a voltage/current/sensor threshold at nA–µA budget without false triggers.
Always-on monitoring: keep a supervisor-like decision running while the rest of the system is off.
Cross-domain outputs: avoid back-powering and phantom current paths when interfacing to logic/MCUs.
Why nano-power is not “just a slower comparator”
Leakage-dominated behavior: PCB and input leakage often set the real threshold error, not offset alone.
Dynamic biasing: ultra-low Iq is frequently achieved with duty-cycled or dynamic front-ends, so “valid decision” windows matter.
Slow-ramp pathology: slow rails and noisy thresholds can cause multi-toggling unless hysteresis + deglitch are planned.
Output energy cost: pull-ups and domain interfacing can dominate the system power even if the comparator is nA-class.
What this page does NOT cover (to avoid page overlap)
High-speed timing / edge jitter and latched sampling (belongs to High-Speed / Latched Comparator).
Precision threshold accuracy deep-dive as a primary topic (belongs to Precision Low-Offset Comparator).
General OD vs push-pull tutorial beyond nano-power implications (belongs to Output Types pages).
Generic hysteresis math textbook (belongs to Design Hooks; only nano-power pitfalls are touched here).
Window / zero-crossing theory as a main focus (belongs to Window Comparator / Zero-Crossing pages).
Definition: Sub-1V / Nano-Power Comparator — what “nano” really means
“Sub-1V” and “nano-power” must be read as system-level guarantees, not marketing labels. The key question is:
Can the comparator make a correct decision early enough on a slow storage ramp, without leakage and output interfacing draining the budget?
What “Sub-1V” must clarify (three different voltages)
VDD(start): the minimum rail where the internal bias/reference can start operating.
VDD(valid decision): the minimum rail where the comparator decision is guaranteed correct within stated conditions.
VDD(output valid): the minimum rail where the output logic level and leakage meet interface requirements.
A design that “starts” but does not provide valid output early enough will still fail cold-start enable and wake-up sequencing.
What “Nano-Power” must clarify (two currents that behave differently)
Iq(sleep/monitor): the true always-on budget while continuously watching a threshold.
I(active/pulsed): transient or duty-cycled bias used to reach ultra-low average current.
The system must budget startup time and valid-decision windows when dynamic biasing is involved.
The practical “spec set” this page uses (record these fields)
For nano-power wake-up chains, threshold accuracy and reliability depend on a small set of specs that map directly to failure modes:
cold-start failure, false wake-up, drift/leakage threshold shift, and cross-domain back-powering.
VDD(min) / Cold-start
Determines earliest usable rail for the chain.
tSTART
Sets when a decision becomes valid after ramp.
Iq (sleep / active)
Defines always-on budget and wake latency trade-offs.
Input bias / leakage
Dominates high-Z divider threshold errors.
VOS / Drift
Sets the best-case floor once leakage is controlled.
VICR near rails
Critical when sensing near GND or VDD during ramps.
VHYS
Stops chatter on slow/noisy thresholds.
Output (type / leakage)
OD pull-ups and back-power paths can dominate power.
Power-on output state
Prevents accidental PFET/eFuse enable during the uncertain part of a cold-start ramp.
Core architectures used for sub-1V & nano-power
Sub-1V and nano-power behavior is largely determined by how the front-end is biased and how the threshold is generated.
The goal is not transistor-level analysis, but a practical map from architecture choices to system outcomes:
valid-decision windows, leakage-dominated threshold error, and cross-domain output energy cost.
Two macro-classes: static nano-power vs duty-cycled dynamic bias
Static nano-power keeps the input stage biased continuously. Behavior is intuitive for slow thresholds, but high-Z leakage and input bias current often dominate the threshold error.
Duty-cycled / dynamic bias reduces average current by sampling or pulsing bias. It can reach very low average Iq, but introduces a valid-decision window and ramp-rate sensitivity.
Threshold generation: where “the reference” really comes from
MOS-based ref
Enables low-voltage operation, but pay attention to startup and drift under temperature and process variation.
Low-V bandgap
Improves threshold stability, but verify VDD(valid) and tSTART on slow ramps before enabling loads.
Divider-only
Simplifies the IC, but the system becomes leakage-dominated; PCB contamination and humidity can outweigh offset.
Why open-drain dominates in nano-power systems
Domain-flexible: pull-up can be placed in the target logic domain without forcing shared rails.
Safer power-up behavior: default states and leakage paths are easier to control in cold-start chains.
Lower back-power risk: avoids pushing current into unpowered domains through output structures.
The practical trade-off is that the pull-up network can dominate energy cost; record output leakage and pull-up current budgets in the selection table.
What to record per architecture (field set that maps to failures)
Valid window
VDD(valid decision), tSTART, and ramp-rate sensitivity.
Threshold credibility
ILEAK / input bias, VOS / drift, and whether a built-in reference is used.
Interface cost
Output type, output leakage, pull-up current, and domain back-power checks.
Cold-start & power-ramp behavior (the make-or-break chapter)
In energy-harvesting and storage-cap systems, the rail often rises slowly. The failure mode is not “does it start,” but
when the decision becomes valid and whether the output is stable enough to safely enable the load.
A correct design treats cold-start as a staged timeline: VREF valid → comparator valid → output stable → load enable.
The four items that must be verified on a slow ramp
1) VDD(min) vs “output valid”
Record VDD(start), VDD(valid decision), and VDD(output valid). A chain can “run” but still produce an
unstable or incompatible output before the main domain is ready.
Record
VDD(valid), VDD(out-valid), output leakage at low VDD.
2) Startup time window
Verify tSTART under the expected ramp rate. Enabling the load inside the startup window can trigger a brown-in/brown-out loop.
Action
Add a delay gate (RC / lockout / latch) so EN is only allowed after output is stable.
3) Power-on default output
Confirm the POR output state and whether short glitches can appear during the uncertain part of the ramp.
A single unintended PFET/eFuse enable can drain the storage node.
Record
POR state (0/1/Z), worst-case glitch width, ramp-rate used.
4) Brown-in / brown-out hysteresis strategy
System-level stability requires more than a small VHYS. Define VTH_on and VTH_off so the load does not
repeatedly start and stop near the threshold.
Action
Use a gate/lockout so once enabled, disable requires a stronger condition than enable.
Ramp competition: reference settling vs “decision sampling”
On slow ramps, the comparator and its reference/bias may pass through intermediate states. The safe rule is:
treat early outputs as “unsafe” until the chain reaches output-stable, then allow EN through a simple gate (delay / latch / lockout).
Threshold accuracy under mega-ohm dividers: error budget that actually matters
In nano-power designs, divider resistors often reach MΩ to 100MΩ. At these impedances, threshold error is usually not
dominated by offset; it is dominated by leakage paths that steal or inject current at the divider node. The practical goal is to
convert “leakage risk” into a simple budget: how many nA are allowed for a given threshold error target.
Error sources ranked for nano-power dividers (highest impact first)
Comparator input bias / input leakage (device-dependent and temperature-dependent)
Resistor tolerance / TC (ratio error and ratio drift)
Offset / drift (often not the dominant term in mega-ohm systems)
Reference noise (more visible as repeatability / chatter than as DC bias)
A practical budget model: convert leakage current into threshold voltage error
1) Divider node impedance
Use the Thevenin resistance at the sense node:
RTH ≈ (RTOP ∥ RBOT).
2) Leakage-to-error mapping
Any net current stealing/injecting at the node produces an error:
VERR ≈ ILEAK,total × RTH.
3) Reverse budget from a target
For a target threshold error |VERR| ≤ VTARGET, the allowed leakage is:
ILEAK,allowed ≈ VTARGET / RTH.
A simple engineering rule to “get it working first”
Choose divider current so leakage becomes a small fraction of the node current:
Divider current guideline
IDIV ≥ 50–100 × ILEAK,worst
This does not replace a full budget, but it is a reliable starting point for early prototypes and for identifying
whether the dominant problem is leakage or something else.
Temperature / humidity / cleanliness: actions that actually reduce leakage
Guard ring around the high-impedance node (tie to a low-impedance reference potential).
Solder mask keepout and larger spacing near the divider node to reduce surface conduction.
Board cleaning to remove flux residue (a frequent hidden leakage path).
Conformal coating for outdoor/high-humidity operation where MΩ nodes must remain stable.
Keep probes and fixtures honest: measurement setups can add leakage paths that do not exist in the final product.
Record these fields (selection + validation sheet)
Hysteresis & slow-ramp chatter (nano-power specific, not generic)
Slow ramps combined with small ripple can cause multiple threshold crossings and false wake-ups. In nano-power designs,
the source impedance is often extremely high, so hysteresis must be sized and implemented to stop chatter while keeping
leakage risk and output pull-up energy under control.
Why chatter happens on mega-ohm nodes
Slow dV/dt makes the input spend more time near the threshold.
Ripple / noise becomes large relative to the instantaneous headroom, causing multiple crossings.
High source impedance makes the node easier to disturb by leakage, probing, or pull-up coupling.
Built-in vs external hysteresis: nano-power trade-offs
Built-in VHYS
Minimal external high-impedance feedback paths. Typically the most robust option when PCB leakage is the dominant risk.
External feedback (R)
Feedback resistors often become MΩ-class, introducing new pitfalls: feedback leakage, bias-current induced shifts,
and sensitivity to humidity and contamination.
OD pull-up cost
Pull-up energy can dominate system power. Budget it explicitly using IPULLUP ≈ V / R and the expected output duty.
“Enough” hysteresis: a practical sizing rule
VHYS guideline
VHYS ≥ 3 × Vripple,pp
When the cost of a false wake-up is high (for example, enabling a load that collapses the storage rail), a more conservative
margin can be used. After setting VHYS, re-check the threshold budget from the mega-ohm divider section.
Anti-chatter stack: lowest-cost combinations that work
VHYS to prevent multiple crossings at the threshold.
RC to reduce high-frequency ripple on the divider node (keep components close to the input).
Lockout / delay / latch so wake-up becomes a one-time event and does not retrigger on small rebounds.
Speed / energy / wake-up latency trade-offs (how to budget it)
In nano-power wake-up chains, “too slow” is usually a system-budget problem: the comparator decides under small overdrive,
while the overall wake-up time is dominated by boot and measurement stages. The practical approach is to budget both
time and energy as a timeline, then decide where nano-power detection ends and where the accurate chain begins.
Propagation delay under small overdrive (engineering use, not theory)
Small overdrive → longer delay near the threshold region, especially on slow ramps.
Longer delay → larger exposure to ripple, increasing the probability of false toggles.
Budget delay against VOD(min) (minimum Vin–VTH margin), not against a single “typical delay” number.
A usable energy budget (quick math that guides architecture)
Per-event energy (first-order)
E ≈ VDD × I × t
Always-on monitoring
Use I_sleep and total monitoring time to estimate the baseline drain.
Decision window
Use I_active and the decision time window to estimate event cost.
Two-stage strategy: wake-up detection vs accurate measurement
Nano-power comparator handles wake and coarse threshold under tight energy limits.
After wake-up, the system switches to MCU ADC / precision chain for accurate measurement and confirmation.
A second confirmation step reduces energy wasted on false wakes without forcing the nano-power stage to be fast.
Budget the chain by segments (find the real bottleneck)
Detect window
Comparator decision under VOD(min).
Wake interrupt
IRQ routing and domain handoff.
MCU boot
Reset release, clock start, firmware entry.
Accurate measure
ADC sample, filter, second confirmation.
Output & domain interfacing in nano-power systems (avoid back-powering)
Nano-power wake-up chains often span multiple rails: the comparator lives on a storage capacitor or always-on domain,
while the MCU and loads live on a switched domain. The most common failure is back-powering through I/O structures or pull-ups.
A correct interface treats the output as a cross-domain signal with explicit pull-up placement, ESD diode path checks,
and a controlled power-on default state.
Open-drain output: the real nano-power cost to budget
Pull-up current
IPULLUP ≈ VPULLUP / RPULLUP (when OUT is low)
Average cost depends on the low-level duty cycle and leakage. Pull-up placement and logic polarity can decide whether the
interface is truly nano-power at system level.
Back-powering: must-check paths before the first prototype
ESD diode path
Verify whether the input/output pin can source current into an unpowered rail through protection structures.
Pull-up domain
Decide explicitly: pull-up to always-on or to the MCU domain, and confirm OFF-state safety.
Mitigation parts
Reserve options: series-R, diode, or level shifter for robust domain separation.
Confirm output POR state (0/1/Z) at low VDD and during slow ramps.
Allow enabling only after OUT stable and main rail valid are both true.
Use a simple lockout / delay / latch so the enable signal cannot follow short glitches.
Interface audit list (copy into the schematic review)
Where is pull-up?
Always-on / MCU / external.
OFF-state safety
Any rail lifted when MCU is off?
ESD diode path
Pin → VDD / GND conduction exists?
Options reserved
Series-R / diode / level shift.
Energy harvesting & always-on wake-up recipes (copy-paste circuits)
These recipes are designed as copy-paste building blocks for nano-power, sub-1V wake-up systems. Each recipe keeps the same
four fields visible: VTH, VHYS, Domain, and Output. Use the same field set to compare options and to convert each
schematic into a validation plan.
Recipe field set (use the same checklist for every circuit)
Threshold
VTH (or VTH+/VTH−), VHYS.
Divider
R_TOP/R_BOT, R_TH, I_DIV, leakage allowed.
Domains
Always-on rail, MCU rail, load rail.
Output
OD/PP, pull-up rail, POR default, lockout/latch.
Recipe A — Harvester cold-start enable (only turn on DC/DC after VCAP reaches VTH)
Use a nano-power comparator to gate the DC/DC enable so the harvester does not collapse the storage rail during early ramp.
Window width vs ripple, mega-ohm leakage shift, back-power paths.
Recipe C — Load disconnect / ship mode wake (ultra-low static, wake on event)
Keep only the always-on comparator alive and disconnect the main load domain. Wake-up is a one-time event that hands control
to firmware after a clean domain transition.
Validation: how to measure nA currents & leakage without lying to yourself
Nano-power validation often fails because the measurement setup adds leakage, burden voltage, or temperature/humidity coupling.
A reliable plan separates instrument effects from board leakage and converts results into pass/fail thresholds that can be reused
in prototype reviews and production screening.
Six nA measurement traps (symptom → cause → action)
Instrument burden
Reading changes with range → setup adds voltage drop → verify DUT-node voltage and reduce burden.
Probe/fixture leakage
Results change with probes → fixture creates leakage path → use guarded connections and minimize contact area.
Board contamination
Improves after cleaning → residue forms surface conduction → enforce cleaning, keepout, and spacing on high-Z nodes.
Humidity sensitivity
Shifts in humid air → surface leakage rises → add humidity soak to validation and use coating if required.
Missing guard
High-Z node drifts → nearby potentials inject leakage → implement guard ring tied to a low-impedance reference.
Thermal drift
First minutes drift → temperature not settled → define stabilization by a threshold, not by a fixed time.
Stimulus: full temperature sweep → Observe: VTH shift, I_sleep, OUT leakage → Pass: threshold error ≤ budget → Action: reduce R_TH or improve guard/cleanliness.
Humidity soak
Stimulus: high-humidity soak near VTH → Observe: leakage and false triggers → Pass: false wake rate ≤ Y ppm → Action: clean, coat, increase spacing, add guard ring.
Output leakage test
Stimulus: OUT high/low/Z with intended pull-up domain → Observe: pull-up current and leakage → Pass: static current meets target → Action: adjust pull-up, polarity, or output gating.
Domain back-power test
Stimulus: turn MCU domain OFF while AO is ON → Observe: OFF rail lift → Pass: OFF rail stays below safe limit → Action: add series-R/diode/level shift and move pull-up domain.
Pass/fail template (use the same structure in reports and production screens)
Engineering checklist (layout, cleanliness, and bring-up hooks)
Nano-power, mega-ohm dividers, and sub-1V cold-start failures are dominated by leakage, contamination, and domain interactions.
This checklist prioritizes actions that prevent “beautiful bench data” from collapsing on real boards and in humidity.
1) Layout (highest priority)
High-Z node length
Check: Keep the divider sense node and comparator input trace extremely short; avoid routing near pads, vias, and silk.
Pass: High-Z node is isolated and short; no adjacent copper at different potentials.
Action: Move divider next to the pin; remove test pads on the high-Z node; increase keepout.
Guard ring
Check: Surround the high-Z node with a guard tied to a low-impedance reference at a similar potential.
Pass: Guard forms a closed ring around the node; return path is solid and low impedance.
Action: Add guard on both layers when possible; widen spacing; avoid guard segments that float.
Spacing & creepage
Check: Increase spacing around mega-ohm nodes and between rails that can create surface conduction under humidity.
Pass: No narrow “moat” regions that trap residue; spacing scales with expected humidity and voltage.
Action: Increase clearance; remove solder mask openings near high-Z; avoid long parallel traces.
2) Cleanliness & process control
Flux residue & ionic contamination
Check: Cleaning method is defined and repeatable for boards that contain mega-ohm dividers.
Pass: Leakage stays within budget after thermal + humidity soak.
Action: Tighten cleaning + drying steps; add no-clean restrictions for high-Z regions.
Conformal coating strategy
Check: Coating boundary and thickness are controlled near the divider and input pins.
Pass: Coating reduces humidity sensitivity without adding new leakage paths.
Action: Define keepout where coating can wick; validate with soak tests before locking process.
Bring-up environment
Check: Early measurements are not performed in uncontrolled humidity with exposed high-Z nodes.
Pass: Data is repeatable across days and fixtures.
Action: Use a chamber (or at least humidity logging); use guarded probing for nano-amp work.
3) BOM pitfalls (leakage dominates)
High-value resistors
Check: Type and package are selected for surface leakage and voltage coefficient at the intended node voltage.
Pass: Divider behavior stays stable across temperature and humidity.
Action: Reduce R_TH if leakage budget is tight; choose resistor series rated for high resistance stability.
Capacitors near high-Z nodes
Check: Leakage and dielectric absorption are acceptable at the node voltage.
Pass: No slow “rebound” that mimics hysteresis or drift.
Action: Avoid large caps directly on high-Z nodes unless validated; keep RC on a buffered node if needed.
Protection devices
Check: TVS/ESD parts do not add reverse leakage that can overwhelm a mega-ohm divider.
Pass: Threshold does not shift when protection is populated.
Action: Move protection away from the high-Z node; add series resistance; validate leakage at temperature.
4) Bring-up order (do not skip steps)
Leakage first: measure/estimate leakage at the divider node (fixture + board) before tuning thresholds.
Threshold second: verify VTH accuracy at room; then repeat at temperature and humidity stress.
Ramp third: run slow VDD/VCAP ramps; confirm no chatter and no “danger window” mis-triggers.
Domain fourth: validate output pull-up domain and back-power paths with domains powered on/off.
Protection last: add RC/TVS/filters only after the baseline is stable; re-run ramp + humidity tests.
Production hooks (log fields)
VDD(min) (start & output-valid), tSTART, threshold error, chatter toggle count, false wake count, temperature slope, humidity soak outcome.
Applications + IC selection logic
The focus stays on sub-1V / nano-power wake-up behavior: cold-start validity, mega-ohm divider accuracy, slow-ramp chatter,
and safe cross-domain interfacing. The selection flow below converts those risks into a short list and an inquiry template.
A) Applications (only sub-1V / nano-power relevant)
Energy harvesting nodes
AO rail is the storage capacitor. Key risks: VDD(min) vs output-valid, slow ramp danger window, latch/lockout for EN.
Always-on wake for IoT / wearable
AO comparator does coarse detect; firmware does precision only after wake. Key risks: false wake rate and pull-up energy.
Ship-mode / long-storage devices
Static current must include pull-ups and leakage paths. Key risks: back-power through IO and humidity-driven leakage shifts.
Remote threshold alarms (high-Z lines)
Long high-impedance wiring behaves like a leakage source. Key risks: threshold drift and chatter. Add VHYS/RC and validate soak.
B) IC selection logic (fields → risks → inquiry template)
Must-ask fields (in priority order)
VDD(min) (startup and output-valid), Iq (sleep/active/average), tSTART, input bias/leakage vs temperature,
VOS/drift, VHYS (built-in limits), VICR near rails, output type & leakage, power-on output state.
Request test conditions for each key spec:
• Divider impedance (e.g., 10M–100MΩ) and source resistance
• Ramp rate (slow VDD/VCAP ramps)
• Temperature & humidity corners
• Output pull-up domain and duty cycle
Example comparator part numbers (short-list starting points)
The items below are practical starting points for nano-power wake-up designs. Variants and packages differ; always verify
VDD(min), output-valid behavior, and leakage vs temperature/humidity in the datasheet and in board tests.
Sub-1V / harvesting-friendly
• TI TLV3691 (nano-power class; common in always-on wake)
• ST TS881 (low-voltage, ultra-low-power family)
• ST TS880 / TS883 (OD-output options are often used for cross-domain pull-ups)
Window / power-valid building blocks
• ADI/MAXIM MAX9060 / MAX9061 / MAX9062 family (nano-power comparators; some variants include reference options)
• ADI/MAXIM MAX9065 family (window-type options for brown-in/brown-out)
If latency must improve (not nA-class)
• TI TLV7011 / TLV7021 (microamp-class, faster behavior for wake chains where energy permits)
What to demand from the vendor (copy-paste)
Provide leakage and output-valid behavior under these conditions:
• Divider: R_TOP=__ , R_BOT=__ (target R_TH=__), node voltage=__
• Ramp: dV/dt=__ (slow), startup from VCAP=__ to __
• Environment: TA=__ corners; humidity soak=__ ; board cleanliness assumptions=__
• Output: OD/PP, pull-up rail=__, duty cycle=__, back-power paths when other domains are OFF
Short, actionable answers only. Each item includes a repeatable check, a numeric threshold, and a fix path.
Scope is limited to cold-start, mega-ohm dividers, slow ramps, leakage, and cross-domain interfacing.
Why does the datasheet say “sub-1V,” but the output is only stable at a higher voltage?
Symptom: The device starts switching near the advertised VDD(min), but OUT chatters, glitches, or becomes valid only after VDD rises further.
Likely causes (Top 3): (1) “VDD(min)” is a start/operate point, not an output-valid guarantee; (2) internal reference/bias needs extra headroom/time on slow ramps; (3) pull-up/load conditions differ from datasheet test setup.
Quick checks: (1) Ramp VDD slowly and record the first voltage where OUT becomes stable; (2) repeat with a lighter pull-up / different pull-up rail; (3) repeat with a faster ramp to see if the “danger window” shrinks.
Threshold: Define VOUT_VALID as “≤ 1 unintended toggle and OUT remains stable for ≥ 5 s.” Set system enable threshold ≥ VOUT_VALID + 100 mV (or ≥ 10% margin) for harvesting ramps.
Action: Add lockout/delay so the load enable is blocked until VDD crosses VOUT_VALID; move OD pull-up to the always-on domain; require vendor “output-valid vs ramp rate” data when selecting parts.
Avoid: Designing around “typical VDD(min)” without verifying output validity under the actual ramp rate, pull-up, and load.
After using a 10–50 MΩ divider, why does the threshold drift wildly? What are the first three things to check?
Symptom: Threshold error becomes large and inconsistent across boards, days, or humidity.
Likely causes (Top 3): (1) PCB surface leakage / contamination dominates; (2) comparator input leakage/bias current dominates; (3) resistor voltage coefficient / TC and package surface leakage dominate (offset is often not the main driver here).
Quick checks: (1) Clean + dry the board and re-measure; (2) add/verify guard ring + spacing around the high-Z node; (3) temporarily reduce the divider resistance by 10× and see if the drift collapses.
Threshold: Use this start rule: Idiv ≥ 50–100× ILEAK_WORST. If leakage is unknown, treat it as ≥ a few nA under humidity and do not let Idiv drop below that ratio.
Action: First fix cleanliness/guard/spacing; then lower divider resistance (or move to an internal reference solution) until the leakage ratio is satisfied at temperature and humidity corners.
Avoid: Assuming resistor tolerance/TC will dominate at mega-ohm values without quantifying leakage.
On a slow ramp, the output toggles multiple times. What hysteresis (VHYS) should be tried first?
Symptom: Multiple toggles near threshold during slow input or VDD ramps; false wake-ups.
Likely causes (Top 3): (1) Overdrive is tiny during slow ramps; (2) high source impedance + leakage/noise creates effective input jitter; (3) reference/bias is still settling, creating a moving threshold.
Quick checks: (1) Log toggle count during a controlled ramp; (2) measure ripple/noise at the comparator input (use guarded probing); (3) repeat with a faster ramp to confirm “slow-ramp” sensitivity.
Threshold: Start with VHYS ≥ 3× ripple_pp. If ripple is unknown, start with VHYS ≥ max(20 mV, 1–2% of VTH) and iterate.
Action: Use the “three-piece” fix: VHYS + a small RC (on a controlled node) + output lockout/debounce. If external hysteresis requires mega-ohm feedback resistors, treat leakage as a first-order error and lower source impedance.
Avoid: Adding huge feedback resistors without validating leakage over humidity and temperature.
If an open-drain output is pulled up to the main power domain, will it back-power the system? How to check fast?
Symptom: With the main rail OFF, the system still leaks current, partially boots, or the main rail floats upward.
Likely causes (Top 3): (1) ESD diode paths into the “OFF” domain; (2) pull-up injects current through IO protection; (3) level mismatch creates unintended conduction paths.
Quick checks: (1) Power only the always-on domain and keep main rail OFF; measure main-rail voltage; (2) remove the pull-up and compare; (3) insert a large series resistor and see if the symptom disappears.
Threshold: Treat it as a back-power risk if the OFF rail rises above 0.2–0.3 V or if injected current into the OFF rail exceeds 1 µA in ship/sleep conditions.
Action: Pull up OD to the always-on domain and level-shift; or add series-R (typ. 100 kΩ–1 MΩ) / diode / gated interface so the OFF domain cannot be energized through IO.
Avoid: Direct pull-ups into an unpowered domain without a back-power test.
During cold-start the PFET is mistakenly enabled. How can “default output state + delay” prevent it?
Symptom: Load switch turns ON briefly during startup, draining the storage capacitor or causing repeated reset loops.
Likely causes (Top 3): (1) Power-on default output state is not “safe”; (2) reference/bias settles later than the gate control; (3) slow ramp passes through a danger window where OUT is not yet valid.
Quick checks: (1) Log OUT state vs VDD during cold-start; (2) repeat with a faster ramp; (3) temporarily force EN low with a resistor to confirm the failure is in the enable path.
Threshold: Use a delay ≥ tSTART(max) + 2× margin. If tSTART(max) is unknown under harvesting ramps, start with 50–200 ms and validate across temperature and ramp rate.
Action: Choose a “safe-off” default (logic inversion if needed) and gate the PFET enable with a lockout (RC + latch/AND with VDD_OK). Require OUT stability before allowing EN.
Avoid: Driving a PFET gate directly from a comparator without a validity delay on slow ramps.
Why does input protection (TVS/RC/clamps) shift the threshold? How to balance leakage vs protection?
Symptom: Threshold moves after adding protection parts; the shift worsens at high temperature or humidity.
Likely causes (Top 3): (1) Reverse leakage of TVS/ESD clamps; (2) capacitor leakage or dielectric absorption at high-Z nodes; (3) clamp paths create new DC bias currents that a mega-ohm divider cannot swamp.
Quick checks: (1) Compare threshold with/without protection populated; (2) repeat at hot and after humidity soak; (3) move the clamp to a lower-impedance node (temporarily) and check if the shift disappears.
Threshold: Keep total protection leakage ≤ Idiv / 100 as a start rule. If that is not possible, reduce divider resistance or redesign the protection placement.
Action: Add series-R to limit fault current; keep clamps off the high-Z sense node; pick low-leakage parts; validate leakage vs temperature in the same fixture used for production.
Avoid: Treating protection leakage as “negligible” when the divider current is in the nA range.
Iq is very low, but wake-up latency is long. How can a “two-stage wake” fix it?
Symptom: Battery/harvester budget is met, but the system reacts too slowly.
Likely causes (Top 3): (1) Nano-power bias is slow at small overdrive; (2) slow-ramp validity delay dominates; (3) the always-on block is being forced to do “precision” work it cannot do quickly.
Quick checks: (1) Measure latency vs overdrive (slightly move threshold and observe timing); (2) separate “detect latency” from “MCU boot time”; (3) confirm the always-on comparator is only used for coarse wake.
Threshold: Use an energy budget check: E ≈ VDD × Iq(avg) × t. If latency must shrink, allocate energy to a faster second stage after wake.
Action: Stage-1: nano-power comparator does coarse wake (looser threshold, strong debounce). Stage-2: after wake, use MCU ADC or a faster/precision comparator to confirm and act.
Avoid: Demanding fast, accurate, and ultra-low Iq from the same always-on comparator stage.
False triggers happen when humidity rises. What are the three most effective board-level fixes?
Symptom: Threshold shifts and chatter increase dramatically after exposure to humid air or condensation risk.
Likely causes (Top 3): (1) Surface conduction across contamination; (2) insufficient spacing/guarding around high-Z nodes; (3) coating/cleaning process is not controlled or creates new leakage paths.
Quick checks: (1) Compare drift before/after cleaning + bake; (2) compare boards with and without guard/keepout; (3) run a controlled humidity soak and log false wake count.
Threshold: Convert “humidity sensitivity” into a target: during a soak (e.g., high RH, long duration), require false wakes ≤ 10 ppm (or ≤ 1 per day equivalent) under the defined ramp/decision rate.
Action: (1) Lock cleaning + drying steps (and ban flux residue near high-Z); (2) add guard ring and increase spacing/keepout; (3) apply conformal coating with a validated boundary and re-run soak tests.
Avoid: Shipping a mega-ohm design without a humidity soak + false-wake metric.
How can production test measure nA Iq reliably without the instrument “lying”?
Symptom: Iq looks great on bench but shifts with different meters/fixtures; results drift or flip sign.
Likely causes (Top 3): (1) Meter burden voltage changes DUT behavior; (2) cable/fixture leakage is comparable to DUT current; (3) temperature gradients and settling time dominate nA readings.
Quick checks: (1) Measure burden voltage and keep it near zero; (2) short the fixture input to quantify fixture leakage; (3) require a settling window before reading (log current vs time).
Threshold: Target burden < 10 mV and “stable reading” defined as ±5% within a 30 s window after settling.
Action: Use guarded measurement (triax/guard ring fixture), minimize cable length, control temperature, and standardize settling time + range settings across stations.
Avoid: Comparing nA results from different instruments without matching burden, guarding, and settling.
Built-in reference vs external divider: when is a built-in reference required?
Symptom: External mega-ohm divider cannot hit the threshold accuracy target across humidity/temperature or board-to-board spread.
Likely causes (Top 3): (1) Leakage is not bounded tightly enough; (2) divider current is too low to swamp leakage/bias; (3) resistor voltage coefficient and surface leakage dominate long-term stability.
Quick checks: (1) Compute Idiv and compare it to worst-case leakage assumptions; (2) run a humidity soak and measure threshold drift; (3) lower divider resistance temporarily and check if accuracy returns.
Threshold: If Idiv cannot be kept at ≥ 50× ILEAK_WORST (under humidity/temperature corners), prefer a built-in reference/DAC threshold solution.
Action: Use a comparator with an integrated reference/DAC (or add a micropower reference) and keep external nodes at lower impedance; validate reference startup time and drift under the real ramp.
Avoid: Expecting “precision thresholds” from uncontrolled mega-ohm networks in humid environments.
Why does connecting the comparator output to an MCU GPIO still drain power when the MCU is off?
Symptom: Ship-mode current is higher than expected; the MCU “half powers” or the OFF rail is lifted.
Likely causes (Top 3): (1) GPIO ESD diodes conduct into the MCU VDD when the pin is driven/pulled-up; (2) pull-up is tied to the wrong domain; (3) push-pull outputs drive into an unpowered input.
Quick checks: (1) Power OFF the MCU and measure its VDD pin voltage while the comparator is active; (2) remove pull-up / change pull-up domain and compare; (3) insert a series resistor and re-measure.
Threshold: Treat it as a problem if the MCU VDD rises above 0.2 V when “off” or if ship-mode current increases by > 1 µA after connecting the GPIO.
Action: Use OD pulled up to the always-on domain + level shift; add series-R (100 kΩ–1 MΩ) to limit injection; ensure GPIO is high-Z in OFF states; avoid push-pull into unpowered pins.
Avoid: Any direct electrical path from an always-on signal to an off-domain pin without back-power validation.
How should “false wake-up rate” be defined and turned into a measurable verification metric?
Symptom: “False wake” is discussed qualitatively, but there is no test that can prove it meets the product target.
Likely causes (Top 3): (1) No defined “wake opportunity” count (ramps, hours, events); (2) tests do not include humidity/temperature corners; (3) chatter and back-power paths are not tracked as separate failure modes.
Quick checks: (1) Define an opportunity unit: ramps, hours, or monitored events; (2) run N opportunities and count wakes; (3) repeat after humidity soak and temperature sweep.
Threshold: Express a target as ppm (false wakes per 106 opportunities) or per day. Example target: ≤ 10 ppm or ≤ 1/day under the specified ramp/noise/soak conditions.
Action: Log toggle count, wake count, and domain voltages. Tune VHYS/RC/debounce until the metric passes at temperature + humidity corners, then lock the process and fixture.
Avoid: Declaring success based on a single clean bench run without soak and opportunity counting.
