This page shows how comparator ICs with built-in one-shot/timer turn noisy thresholds into clean, timed events—so debounce, blanking, timeout, and delayed shutdown work predictably in real hardware.
It focuses on practical timing modes, error/temperature/measurement traps, and design rules to prevent false trips while meeting real response-time and protection budgets.
What this page solves: clean events, timed pulses, delayed protection
Slow edges and noisy thresholds can make a comparator toggle multiple times (chatter), creating false interrupts, false alarms,
or unintended shutdowns. Narrow fault spikes may be real but too brief for downstream logic to capture. Startup surges and switching
transients can trigger protection when they should be ignored. Some systems cannot afford heavy MCU filtering (latency/power/firmware risk)
and need the analog front end to output a single, deterministic “event.” This page focuses on comparators with built-in one-shot/timer
features that turn messy threshold crossings into clean pulses, blanking windows, and delayed shutdown actions.
Three practical outcomes this page targets
Debounce & clean events
Convert slow/noisy crossings into one stable event (single pulse or single transition), so the system reacts once rather than repeatedly.
Timeout / pulse-stretch
Turn brief spikes into deterministic-width pulses that downstream digital logic and protection pins can reliably detect and log.
Blanking & delayed shutdown
Ignore expected transients (blanking window) and shut down only when a fault persists (delay-off), reducing nuisance trips while keeping safety.
Scope (to avoid content overlap)
This page covers comparators with built-in one-shot/timer/blanking/latch behaviors. It does not attempt to be a general 555/monostable
tutorial or a full comparator theory guide; the focus is practical event shaping for debounce, timeout, and delayed protection actions.
A “comparator with one-shot/timer” is best understood as a short signal-processing chain. The comparator core detects the threshold
crossing, edge/qualifier logic decides what counts as a valid event, blanking gates can ignore expected transients, and a one-shot/timer
generates deterministic pulse width or delayed action. Retrigger/rearm rules decide whether repeated input activity extends the output or
is ignored until the timer completes. Optional latch/reset paths make it suitable for protection systems that must hold a fault state.
Functional chain (what each block changes in the waveform)
Comparator core: converts an analog crossing into a digital transition; its propagation delay depends on overdrive and operating conditions.
Edge / qualifier: determines what counts as a valid event under slow ramps and noise (prevents “multiple crossings” from becoming multiple outputs).
Blanking gate: suppresses events during an expected transient window (startup, inrush, switching edges) without relying on heavy input RC filtering.
One-shot / timer: generates a deterministic pulse width or a deterministic delay before asserting an output action (timeout, pulse-stretch, delay-off).
Retrigger / rearm: decides whether repeated activity extends the output (retriggerable) or is ignored until the timer finishes (non-retriggerable).
Latch / reset + output driver: holds a fault state until reset (latch-off) and exposes it through OD/push-pull output behavior that affects edge shape and effective pulse detection.
Datasheet vocabulary map (term → what it means in the chain)
Term
Look for in datasheet
System meaning
blanking
Timing diagram / “blanking window” spec
Ignores expected transients so the output does not react during startup/inrush/switching edges
rearm
Minimum interval / “rearm time”
Defines how quickly a new event can be accepted after an output pulse or delay sequence
retriggerable
Pulse behavior under repeated input
Repeated activity extends/refreshes the output—useful for persistent faults or noisy bursts
non-retriggerable
Event acceptance during active pulse
Output pulse stays fixed; new events are ignored until completion—useful for “single-shot” capture
latch-off
Truth table / reset conditions
Fault state holds until reset—preferred when safety or compliance requires explicit recovery control
timeout
tPULSE / tTIMEOUT min/max + tolerance
Defines how long the output stays asserted—sets capture margin and protection sequencing
Timing modes you actually use: pulse-stretch, debounce, blanking window, delayed off
One-shot/timer behavior is most useful when treated as a small set of repeatable “timing modes.” Each mode can be selected by matching
the input condition (spike, slow/noisy crossing, startup transient, persistent fault) to the desired output waveform (fixed pulse, single event,
ignore window, or delayed action). The sections below define each mode using the same lens: input condition → output waveform → where it is used → key parameters.
Four modes (what to choose and what to look for)
Pulse-stretch (timeout pulse)
Input condition: a valid event is too narrow to be captured (fault spike, short edge, fast comparator trip).
Output waveform: deterministic-width pulse tPULSE that downstream logic/MCU can always see.
Used for: interrupt capture, event logging, protection pins that require minimum pulse width.
Key params: tPULSE(min/max), retriggerable flag, rearm time, output type (OD pull-up affects edge).
Debounce (single event under chatter)
Input condition: slow ramps or noisy thresholds cross the trip point multiple times.
Output waveform: only one recognized event within a window (tDEB / rearm).
Used for: long cables, switches, slow sensors, power-good transitions that must not double-trigger.
Input condition: startup/inrush/switching edges create predictable transients that should not trip protection.
Output waveform: events are suppressed during tBLANK; normal detection resumes after the window.
Used for: motor start, hot-plug, DC/DC soft-start, gate-driver switching spikes.
Key params: tBLANK(min/max), enable conditions, interaction with rearm and retrigger.
Delayed shutdown (persisting fault → action after delay)
Input condition: fault may be transient; only sustained faults should shut the system down.
Output waveform: trip is declared immediately, but shutdown assertion happens after tDELAY.
Used for: OCP/OVP qualification, nuisance-trip reduction, “fault must persist X ms” rules.
Key params: tDELAY(min/max), latch/retry behavior, downstream chain time (driver/eFuse/MOSFET).
Prop delay vs one-shot delay: how to budget response and effective latency
A protection or event chain is rarely “one delay.” The comparator contributes propagation delay (tPD) that depends on
overdrive and operating conditions. The one-shot/timer adds an intentional pulse width or intentional wait
(tOS, such as tPULSE or tDELAY). Downstream stages (logic, drivers, eFuses, MOSFET turn-off)
add additional latency. Budgeting the full chain with worst-case values prevents nuisance trips, missed faults, and irreproducible bench behavior.
tCHAIN includes controller/logic delay, driver/eFuse response, and MOSFET turn-off behavior. Use max values for safety-critical paths.
False-trigger immunity window
Immunity margin = tBLANK(min) − tNOISE_EVENT(max)
Use tBLANK(min) (shortest blanking) and the worst-case noise/chatter duration. Negative margin predicts nuisance trips.
Datasheet fields that matter for the budget
tPD vs overdrive: use the weakest overdrive case that can happen in the system, then take max delay.
tPULSE / tDELAY min/max: include tolerance (RC, internal current source, temperature).
tBLANK min/max: shortest blanking sets the real immunity guarantee.
retrigger/rearm: repeated activity may extend OUT (retriggerable) or be ignored until rearm.
output type limits: OD pull-up and load affect edge timing and “effective pulse” recognition by logic inputs.
Setting the timer: RC, charge current, thresholds, tolerances, leakage
Timer behavior is only “predictable” when it is budgeted with the same discipline as any other protection parameter.
Across comparator + one-shot/timer parts, timing is typically implemented in one of three ways: an external RC, an external timing capacitor charged
by an internal current source, or a fixed internal timer. The goal is not a textbook derivation; the goal is a usable worst-case method that
produces tMIN and tMAX and explains where timing drift actually comes from.
Common timing implementations (what to identify in the datasheet)
External RC (classic)
Timing is set by R, C, and an internal threshold ratio. Look for CT/RT pins,
timing threshold levels, or a recommended R/C range. High impedance timing nodes are sensitive to leakage and board contamination.
External C + internal charge current
Timing is set by C, ΔV (thresholds), and
I (internal current). Look for ICHARGE/IDISCHARGE specs and VTH(min/max). This approach is predictable
when I and thresholds are budgeted with min/max values.
Fixed internal timer
Timing is internally defined (sometimes with a few selectable options). Use datasheet t(min/max)
directly and size system guardbands around the worst case.
t ≈ R · C · K
→ K is set by the internal threshold ratio and implementation. Use datasheet guidance for K or use t(min/max) curves if provided.
When R is very large, leakage and bias currents can become an additional “hidden” term that shortens or lengthens timing.
Tolerance and drift sources (what moves timing in the real world)
C tolerance / temp drift / DC bias: Cmin can be far below nominal for MLCC under bias; timing can shorten unexpectedly.
R tolerance / tempco: linear impact for RC-based timing; avoid extreme R that makes leakage dominant.
Internal current-source error: Imin/Imax and temperature drift directly scale timing in current-charged schemes.
Threshold dispersion: VTH(min/max) changes ΔV and shifts timing; budget with min/max not typical.
Leakage / bias / board contamination: extra current on high-Z timing nodes skews charge slope; layout cleanliness and lower impedance improve repeatability.
Worst-case workflow (4–6 steps)
Define the required window (minimum acceptable delay/pulse, and maximum allowed delay/pulse).
Identify the implementation type (RC, C+I, or fixed) and list the relevant datasheet min/max fields.
Choose nominal values (R/C or C) to hit the target at nominal conditions.
Compute tMIN and tMAX using min/max of C, thresholds (ΔV), and I (or K).
Evaluate leakage sensitivity (high-Z nodes, bias currents, board cleanliness) and reduce impedance if leakage can dominate.
Apply guardband so the signed-off condition uses worst-case: tMIN ≥ requirement and tMAX ≤ limit.
Glitch immunity without killing speed: blanking, re-trigger rules, and edge qualifiers
Input RC filtering can reduce visible noise, but it also reshapes real fault signatures: it can reduce overdrive, delay threshold crossings,
and even suppress narrow but valid events. In fast protection paths, the most reliable approach is to keep the analog trip path fast, then
enforce immunity in the event domain using blanking windows, edge qualifiers, and one-shot rules
(retrigger vs non-retrigger) so the system ignores what should be ignored without missing what must be caught.
Retrigger rules (system-level behavior)
Retriggerable
What OUT does: repeated input activity refreshes/extends the active pulse.
Best for: sustained faults or bursts that should keep the output asserted.
Risk: noise or chatter can “keep OUT alive” longer than intended unless qualified.
Non-retriggerable
What OUT does: pulse width stays fixed; new events are ignored until completion (rearm).
Best for: event capture and deterministic pulse-stretch without noise-driven extension.
Risk: dense fault trains may be compressed into fewer output pulses if rearm is long.
Selection rules (match fault shape to behavior)
Single narrow spike to be captured: pulse-stretch + non-retriggerable.
Chatter / pulse train from noise: edge qualifier + non-retriggerable (optionally add blanking during known windows).
Sustained fault that must hold alarm: retriggerable or latch-off (system policy decides reset).
Expected transient (startup/inrush): blanking window so valid detection starts after the window.
Over-current protection becomes reliable only when timing policy and power-stage policy are aligned. A comparator with a timer can qualify a fault
by duration (delayed-off), enforce a safe stop until a deliberate reset (latch-off), or implement repeated attempts with controlled cooldown (auto-retry).
The practical design task is to define who is the master (comparator/timer, eFuse, or gate driver),
and which signal closes the loop (EN/SHDN, FAULT, PG).
Three protection strategies (behavior boundaries)
Delayed-off (qualify by duration)
Trigger: OCP crosses threshold → enter timer.
Action: assert shutdown only after tDELAY.
Reset: fault clears → return to normal (or rearm window).
Boundary: tDELAY too long risks SOA; too short causes inrush nuisance trips.
Latch-off (fail-safe stop)
Trigger: OCP → immediate or qualified entry into a latched fault state.
Action: shutdown remains asserted until a deliberate reset.
Reset: reset pin, power cycle, or MCU clear (system policy).
Boundary: safest electrically, but availability can suffer if reset policy is unclear.
Auto-retry (shutdown + cooldown + re-attempt)
Trigger: OCP → qualified shutdown.
Action: wait tRETRY, then re-enable; repeat if fault persists.
Reset: successful restart returns to normal; hard persistent faults keep cycling.
Boundary: retry cadence must respect thermal time constants and EMI/PG stability.
Coordination checklist (master, reset, counting)
Master of timing: comparator/timer vs eFuse vs gate driver (only one should “own” tDELAY/tRETRY).
Shutdown authority: which node is actually forced (EN/SHDN pin, gate pull-down, or upstream supply cut).
Reset path: pin reset, PG-qualified reset, or power cycle (define the only accepted reset).
Foldback alignment: if foldback reduces current first, ensure timer policy does not fight the foldback state.
“Nuisance trip” vs “missed fault” decision cues
Startup inrush: use blanking so detection starts after inrush; delayed-off qualifies only after the blanking window.
Hot-plug / bounce: treat as pulse trains; debounce/qualifiers prevent repeated triggers from acting like a persistent fault.
Motor start / stall risk: align delayed-off with foldback policy; protect SOA while avoiding immediate nuisance shutdown.
Hard short: keep tDELAY bounded by SOA and downstream chain time; latch-off is often the safest policy.
Output interface: open-drain vs push-pull when one-shot is involved
With one-shot timing, the “logical pulse width” is not always the pulse that downstream logic actually recognizes.
In open-drain outputs, the pull-up and total capacitance shape the rising edge, which shifts the time the signal crosses
the receiver threshold. This can shorten the effective pulse width for narrow events.
Push-pull outputs produce cleaner edges and more stable threshold crossings, which is often better for narrow pulses and cascaded timing chains.
Practical implications (when one-shot pulses are used)
Open-drain (OD): pull-up + line capacitance sets rise time; narrow pulses can lose effective width at the receiver threshold.
Push-pull (PP): cleaner edges and earlier threshold crossings; better for narrow pulses and tight timing chains.
Wired-OR / multi-voltage: OD can aggregate multiple events and pull up to another domain; PP needs explicit combining or translation.
Selection rules (fast decision)
Need aggregation or cross-domain pull-up: OD (budget pull-up and capacitance).
Need narrow-pulse fidelity or cascaded timing: PP.
Need both: use one-shot pulse-stretch first, then aggregate with OD, or use a stronger pull-up and smaller bus capacitance.
Measurement traps: why the pulse looks wrong on the bench
When one-shot timing is involved, “the pulse in the datasheet” and “the pulse the bench shows” can differ for reasons that have nothing to do with
the timer itself. The dominant bench errors come from measurement capacitance and ground inductance, supply ripple moving internal thresholds,
output loading reshaping the edge (especially open-drain), and noise repeatedly retriggering a retriggerable timer. The fastest way to fix the bench
is to treat the pulse as a threshold-crossing event at the receiver, not as an ideal logic waveform.
Common traps (symptom → cause → action)
Probe capacitance & ground bounce shift the “threshold event”
Symptom: edge slows, pulse width changes, extra toggles near threshold.
Cause: long ground lead and probe C add RC and loop inductance; reference point moves.
Action: use a ground spring/coax, minimize loop area, and measure at the receiver pin.
Supply ripple moves internal thresholds and timing nodes
Symptom: tPULSE/tDELAY drifts with load switching or power-state changes.
Cause: local VDD/ground noise modulates bias/thresholds; decoupling and return paths are weak.
Action: place decoupling at the IC pins, measure VDD with a short ground, and fix return continuity.
External pull-up / load reshapes OUT edges (effective width changes)
Symptom: logic downstream misses a narrow pulse; the rise looks “late”.
Cause: OD rise time is set by Rpull and total Cin (wiring + inputs + protection).
Action: budget Rpull and Cin, reduce bus capacitance, or use push-pull for narrow pulses.
Retrigger + noise “extends” the pulse
Symptom: OUT stays asserted longer than expected under noisy or bouncing inputs.
Cause: retriggerable behavior refreshes timing on each hit; threshold chatter creates extra hits.
Action: confirm retrigger mode, add qualifiers/blanking, or use non-retriggerable for event capture.
Minimal bench setup (copy/paste)
Probe: 10× with ground spring; keep the loop tiny.
Where to measure: at the receiver pin (not only at the driver output pad).
Trigger: edge trigger with a stable threshold; keep the same measurement threshold for width comparisons.
Power: verify local VDD at the IC pins; decouple at the pins with short returns.
Load model: document Rpull, total Cin, and number of parallel inputs on OUT.
This checklist is designed for fast design reviews and predictable bring-up. It prioritizes the failure modes that most often break comparator + timer
behavior in real systems: timing node leakage, threshold network bias errors, output loading and level compatibility, and supply/ground integrity.
The bring-up section provides repeatable hooks to validate blanking, effective latency, and worst-case timing across corners.
OD rise-time is budgeted (Rpull and total Cin) so effective pulse width meets receiver thresholds.
VIH/VIL compatibility is verified for all voltage domains and all receivers (MCU, logic, driver pins).
Wired-OR aggregation avoids back-power and unintended current paths.
External clamps/ESD do not add excessive capacitance or distort edges.
P0 · Power / ground (decoupling, bounce, isolation boundary)
Decoupling is placed at IC pins with short, direct returns; no high-current sharing on the reference ground.
High di/dt loops are kept away from comparator inputs and timing nodes.
If isolation is present, boundaries and references are explicit; cross-domain signals have controlled return/translation.
Supply ripple does not correlate with timing jitter during worst-case switching activity.
Bring-up tests (bench hooks)
Controlled fault injection: create small, repeatable current or threshold pulses (single event and pulse train).
Blanking validation: inject within blanking (no action) and outside blanking (expected action).
End-to-end latency: measure from threshold crossing to power-stage response; sign off worst-case.
Corner sweep: repeat at cold/room/hot and VDD(min/nom/max) while switching noise sources are active.
Application recipes: debounce, timeout, delayed shutdown, pulse to MCU
Each recipe below uses the same structure so it stays practical and avoids scope creep: Use case → topology → start numbers → failure → fix.
Parts are listed as example BOM seeds to speed up sourcing and bring-up; always confirm IO type (OD/PP), VDD range, and timing method (CT/RC/programmable) against the target board.
Recipe A · Switch / relay debounce (mechanical bounce)
Use case
Slow, noisy edge with bounce must generate a single clean event (no multi-trigger).
FAQs: measurement, thresholds, timing, false trips, and interfaces
Each answer is kept inside this page’s scope (bench behavior, thresholds, timers, false triggering, and output interface) and uses the same
structured format: Symptom / Likely cause / Quick checks / Fix / Threshold.
Why does my one-shot pulse get longer when noise increases?
Short answer: noise creates multiple threshold crossings; a retriggerable timer refreshes its timing on each hit.
Symptom
OUT stays asserted longer than the intended pulse width under noisier input conditions.
Likely cause
Retriggerable mode refreshes timing on every edge/threshold hit.
Threshold chatter from insufficient hysteresis or slow/noisy crossing.
Quick checks
Probe the input at the comparator pin and count extra crossings around the threshold.
Confirm the datasheet timing mode: retriggerable vs non-retriggerable.
Temporarily add hysteresis (or raise qualify time) and see if width stabilizes.
Fix
Use non-retriggerable mode for “capture one event”.
Add/raise hysteresis or add a blanking/qualify rule so noise cannot generate extra hits.
Threshold
Set hysteresis so VHYS ≥ 3–5× the input noise (peak-to-peak near the threshold), or require the input to stay beyond threshold for
tQUAL longer than the noise correlation time.
Retriggerable vs non-retriggerable: which one prevents false shutdown better?
Short answer: use retriggerable to represent a sustained fault; use non-retriggerable to capture a single event without noise “extending” it.
Symptom
False shutdowns happen under noisy edges or pulse trains.
Likely cause
Fault is not clearly “single” or “sustained”; the timing policy does not match the fault shape.
Noise creates extra threshold hits during the timer’s active window.
Quick checks
Classify the input: single spike, burst, or sustained over-threshold.
Check if OUT width depends on noise level (retrigger signature).
Check if the “fault line” returns cleanly below threshold between hits.
Fix
Retriggerable: use for sustained faults so OUT stays asserted while the fault persists.
Non-retriggerable: use for event capture so noise cannot extend the timer.
Threshold
If the fault can appear as a burst where gaps are shorter than the timer width, choose retriggerable. If the goal is “log first hit only,” choose non-retriggerable.
My “10 ms” timeout measures 13 ms on the bench—what dominates the error?
Short answer: passive tolerances and leakage dominate most real timers; measurement threshold definition can add apparent error.
Symptom
Measured delay/pulse width is consistently longer (or shorter) than the nominal setting.
Likely cause
Capacitor tolerance/temperature coefficient (X7R can shift with bias/temp).
Leakage or bias currents stealing/adding charge on the timing node.
Internal threshold/current-source accuracy (if the IC uses internal charge/discharge).
Quick checks
Swap C to C0G/NP0 (or higher-grade film) and re-measure.
Reduce timing impedance (smaller R / larger C) and see if error shrinks (leakage test).
Measure “width” at the receiver’s VIH/VIL crossing, not at an arbitrary scope threshold.
Fix
Use stable timing components (C0G/NP0 where possible) and lower impedance if leakage is suspected.
Add design guardband based on worst-case component spread, not typical values.
Threshold
If timing error changes notably when swapping to C0G/NP0 (or lowering R by 5–10×), the dominant term is C variation or leakage. Treat “10 ms” as min/typ/max rather than a single number.
How do pull-up value and output load change the effective pulse width?
Short answer: with open-drain outputs, the rising edge is RC-limited; the pulse “starts” at the receiver only after VIH is crossed.
Symptom
A narrow pulse is missed or measures shorter at the receiver, especially with OD outputs and long wiring.
Likely cause
OD rise time set by Rpull × Cin (receiver inputs, ESD, wiring, probe).
Pulse width measured at an arbitrary threshold instead of VIH/VIL at the receiver.
Quick checks
Measure at the receiver pin; note the time from 0 to VIH crossing.
Reduce Rpull (stronger pull-up) and see if the “missing” pulse reappears.
Disconnect extra loads (ESD clamp boards, long cable, multiple inputs) to estimate Cin impact.
Fix
Budget RC rise time against the required minimum pulse width at VIH.
For very narrow pulses, use push-pull output (or a buffer) instead of OD.
Threshold
Keep OD rise time small compared to the pulse: a practical start is tR(10–90%) ≤ 20% of tPULSE(min). If not, reduce Rpull or Cin, or switch to push-pull.
Why does blanking work at room temp but fail in cold/heat?
Short answer: timing and thresholds move with temperature (C drift, leakage, internal references); margins that were “just enough” collapse.
Symptom
False trips return at cold/hot even though blanking was verified at room temperature.
Likely cause
Timing capacitor changes with temperature and bias (pulse/blanking shrinks or grows).
Check if noise makes the timer retrigger during startup.
Fix
Set delay just above the benign transient time, then verify thermal/SOA limits at the fault current.
If needed, add a short blanking window during the known startup interval.
Threshold
Enforce a hard cap: tTOTAL(max) must be < the MOSFET safe time at the measured fault current (SOA/thermal). Do not “solve” nuisance trips by extending delay beyond that cap.
Why does the output double-trigger only when probing with a scope?
Short answer: probe capacitance and a long ground lead can create extra crossings (ringing/ground bounce) that look like real triggers.
Symptom
Double trigger appears only when a scope probe is attached; removing the probe restores normal behavior.
Likely cause
Probe capacitance loads a high-impedance node, changing edge shape.
Long ground lead creates inductive bounce and ringing across the threshold.
Quick checks
Switch to a ground spring (or coax tip) and re-test.
Measure at the receiver pin instead of a high-impedance intermediate node.
Compare waveforms with 10× probe vs a high-bandwidth active probe (if available).
Lower node impedance (or buffer it) if probing must be repeatable.
Threshold
If attaching a probe changes the edge timing or level by > 10% (or adds ringing that crosses the threshold), treat the measurement setup as the root cause until proven otherwise.
How to test worst-case delayed shutdown safely on the bench?
Short answer: use controlled, repeatable fault injection and measure end-to-end latency with clear start/stop definitions.
Symptom
Shutdown timing varies run-to-run; stress testing risks damaging the power stage.
Likely cause
Fault injection is uncontrolled (random load/contact bounce).
Start/stop points are inconsistent (scope trigger vs receiver VIH vs MOSFET current collapse).
Quick checks
Inject a known-duration fault pulse (signal generator / controlled switch) instead of “shorting.”
Measure at the receiver (VIH/VIL) and at the power stage (current or VDS change).
Repeat at VDD(min/max) and temperature corners if possible.
Fix
Define latency as: threshold crossing → OUT crosses VIH → driver action → current collapses.
Limit energy during tests (series resistor/current limit/short pulse width) to stay inside SOA.
Threshold
Sign off worst-case with tTOTAL(max) = tPD(max) + tTIMER(max) + tDRIVER + tFET. Use the same measurement points every run.
How to coordinate latch-off/auto-retry with an eFuse or gate driver?
Short answer: assign one “owner” for shutdown policy; everyone else should be a sensor or an actuator—not both.
Symptom
System latches unexpectedly, retries at the wrong cadence, or two devices “fight” each other.
Likely cause
Both the timer comparator and the eFuse/driver implement latch/retry independently.
Reset/enable signaling is ambiguous (who resets whom, when, and under what conditions).
Quick checks
List which block decides: delay, latch, retry period, and clear conditions.
Probe EN/PG/FAULT pins and confirm only one source drives each control line.
Verify reset path is deterministic across power cycles and brownouts.
Fix
Pick the policy owner: either the comparator-timer chain or the eFuse/driver—not both.
Use clear interfaces: comparator provides a clean FAULT event; the owner performs latch/retry and exposes a single reset mechanism.
Threshold
A simple rule: one latch, one retry timer, one reset owner. If two blocks can latch, the system will be corner-case fragile.
Can the timer capacitor leakage dominate at high impedance designs?
Short answer: yes—when leakage current becomes a meaningful fraction of the timing charge/discharge current, timing becomes temperature- and contamination-sensitive.
Symptom
Timing varies wildly with humidity/temperature or from board to board; long delays are especially unstable.
Likely cause
Capacitor dielectric leakage, PCB contamination, or protection paths leak into the timing node.
Timing resistor is so large that bias/leakage current becomes dominant.
Quick checks
Lower timing impedance (reduce R / increase C) and see if timing stabilizes.
Clean the PCB (flux residue) and retest; check humidity sensitivity.
Try a different capacitor technology and repeat.
Fix
Lower timing node impedance and keep the timing node away from dirty/high-voltage nets.
Use stable capacitors and avoid protection elements that create leakage paths into CT/RC nodes.
Threshold
Keep leakage small versus the intended timing current: a practical start is Ileak ≤ 1% of Ichg. If timing changes when R is reduced by 10×, leakage is already significant.
What simple guardband rule avoids over-reject in production?
Short answer: guardband against measurement uncertainty first; avoid setting limits tighter than the test can resolve.
Symptom
Excess rejects despite good field performance; different stations disagree near the limit.
Likely cause
Guardband is smaller than station-to-station uncertainty (timing threshold definition, loading, probe setup).
Limits were set using typical timing, not min/max across corners.
Quick checks
Measure the same unit on multiple stations; extract σ of measured timing/threshold.
Confirm test uses the receiver’s VIH/VIL definition (not a scope default threshold).
Check corner sensitivity (cold/hot, VDD min/max) on a small sample set.
Fix
Set production limits using min/max timing behavior and include station uncertainty explicitly.
Standardize pull-ups, loads, cabling, and measurement thresholds across stations.
Threshold
Simple rule: guardband ≥ 3σ of the production measurement (station-to-station + repeatability). Do not tighten limits below what 3σ can support.
