• False trips / chatter → threshold crossings driven by input noise, ground bounce, or dv/dt-coupled injection near V_TH.
• “Datasheet ns” becomes µs on board → worst-case overdrive is small, pushing propagation delay into the slow region; blanking/deglitch adds additional delay.
• Field-only trips → injection paths (switch node dv/dt, cable EMI, ESD/EFT return) dominate; lab probing or grounding hides the real coupling.
• Missed shutdown → fault pulse too narrow, wrong polarity/levels, or recovery behavior causes the eFuse/driver to ignore or de-assert the fault.

• Protection chain template: Sense → Deglitch/Blank → Compare/Latch → Fault logic → eFuse / Gate driver action.
• Glitch-immunity toolbox: RC, leading-edge blanking, minimum-time deglitch (T_min), one-shot pulse stretch, and latch/hold-off patterns.
• Selection fields: delay vs overdrive, overload recovery, input noise/offset, VICR behavior near rails, output type/drive, and interface compatibility.
• Verification method: timestamp definitions (t0/t1/t2), injection setups, and probing traps for ns–µs claims.

• t0: first threshold crossing at the sense node (current or voltage exceeds the trip level).
• t1: fault valid after deglitch/blank + comparator decision + latch (logic-ready fault).
• t2: power-path action complete (eFuse FET off, driver disables gate, or the controlled switch is forced off).

The end-to-end cutoff time is t2 − t0. Every stage below either reduces risk (immunity) or adds delay—both must be budgeted explicitly.

• Sense delay: front-end RC, source impedance, protection clamps, and parasitic L/C that slow or reshape the event.
• Comparator delay: determined by worst-case overdrive (small OD can stretch delay dramatically vs “typical”).
• Blanking / deglitch: intentional immunity time (T_min)—trades speed for false-trip suppression.
• Output / interface: propagation, level translation/isolation, minimum fault pulse width, and logic polarity compatibility.
• Switch turn-off: eFuse FET discharge, driver disable path, and actual node fall time—often the dominant portion of t2 − t0.

Design rule: budget against worst-case (minimum OD, maximum noise, hottest temperature, lowest VDD), not typical.

Set a system gate that converts protection speed into a requirement: define the maximum event duration t_allow your power path can tolerate at the worst-case peak (I_peak for OCP or V_peak for OVP). The protection chain must guarantee (t2 − t0) ≤ t_allow while keeping false trips below the acceptable rate for the application.

• Hard short (µs-class): prioritize rapid cutoff + robust deglitch/blanking and latch behavior.
• Soft overload (ms-class): typically handled by limit/retry/thermal policies and is outside this page’s deep scope.

• Shunt + Kelvin: speed is limited by loop parasitics (L/C) and any input protection/RC; the dominant error is reference movement from layout (Kelvin integrity, return paths) during hard transients.
• SenseFET / mirror: often fast and compact, but effective behavior is defined by internal filtering/blanking and the external logic interface; verify minimum pulse width and recovery behavior under hard faults.
• Current transformer: strong for fast edges and high dv/dt environments; not a DC sensor; saturation/reset behavior can cause missed events if not bounded.

• Bias×R / leakage×R shifts V_TH: large divider values can translate tiny input bias/leakage currents into meaningful threshold drift.
• Protection networks reshape the event: clamp/TVS capacitance and dynamic resistance can turn spikes into slow ramps (chatter risk) or inject charge into the sense node.
• Front-end RC is a timing decision: deglitch RC improves immunity but delays t0; it must be budgeted against the allowed event duration.

• Sense-node disturbance: dv/dt coupling, ground bounce, cable EMI, clamp charge injection, or slow ramps that create repeated crossings.
• Comparator contribution: input-referred noise, offset, bias current, and recovery behavior when the input is overdriven or forced beyond VICR.
• Threshold source (Ref/DAC): reference noise/TC and filtering choices that modulate the threshold or delay the trip beyond the timing budget.

Treat total threshold uncertainty as two parts: DC error (offset/drift/bias×R/leak×R) and AC jitter (noise/injection/ref noise). Choose a margin that satisfies: Margin ≥ k·σ_total + DC error, where σ_total is the RMS-equivalent disturbance at the comparator input and k is selected to meet the allowed false-trip rate.

The margin decision must remain consistent with the cutoff budget: increasing margin reduces nuisance trips, while excessive filtering or deglitch time can violate the allowed event duration.

• Filter placement must respect timing: filtering that improves threshold stability is useful only if it does not push the trip beyond the allowed cutoff window.
• Control the threshold source impedance: keep Ref/DAC driving impedance low enough that bias/leakage currents cannot move V_TH.
• Prevent threshold modulation: keep reference return paths quiet; avoid routing high dv/dt currents that share impedance with the threshold network.

• Small OD is common in protection: front-end RC/protection networks, source impedance, and injected noise can reduce effective OD right when t0 happens.
• Delay can stretch sharply at low OD: the low-OD region is where “ns-class” becomes “hundreds of ns to µs” under worst-case conditions.
• Always align test conditions: VDD, input common-mode, output load, and temperature must match the system corner used for the timing budget.

• VICR near rails is not always “clean”: near-rail crossover behavior can change delay, noise margin, or even trip polarity under fast transients.
• Transient overvoltage paths matter: input clamps and differential limits can inject currents into the threshold network, creating false trips or delayed decisions.
• Verify the corner that breaks systems: lowest VDD + hottest T + smallest OD + worst CM is the design point, not the “typical” curve.

• Overload recovery time: after a large transient or forced out-of-range input, internal nodes may need time to return to normal—affecting the next event’s delay or even detectability.
• Output-stage saturation recovery: heavy loading or hard rail conditions can distort fault pulses and add latency; recovery behavior is a selection parameter for protection.
• Input differential limits: exceeding limits may engage protection structures that shift the apparent threshold or delay; confirm with the intended clamp network.

• Prop delay vs overdrive curve: read delay at the system’s worst-case OD (not “typ”).
• Overload / saturation recovery: recovery time after large OD, rail forcing, or out-of-range inputs.
• VICR near rails + transient behavior: crossover and clamp behavior under dv/dt environments.
• Input differential limit / overvoltage behavior: what happens when protection clamps conduct.
• Output interface constraints: minimum fault pulse width and logic compatibility (OD vs push-pull details belong to the output-type sibling page).

• When it works: short, high-frequency spikes that should not be interpreted as real faults.
• Cost: RC delays t0 and can turn a fast edge into a slow ramp (chatter risk if margin is small).
• Hook: measure the worst-case glitch pulse width before choosing RC; then check the added delay against the cutoff time budget.

• When it works: repeatable dv/dt-induced spikes aligned with known switching edges.
• Cost: real faults that occur inside the blanking window are delayed; the window must be bounded by worst-case transient duration.
• Hook: validate the upper bound of the transient width across temperature, load, and layout variants.

• What it enforces: the input must remain above threshold continuously for at least T_min.
• Cost: T_min is a hard delay added to the chain; it must fit inside the allowed event duration.
• Hook: choose T_min to suppress threshold-chatter while keeping (t2 − t0) ≤ t_allow.

• When it is needed: eFuses/gate drivers require a minimum fault pulse width or sample the fault synchronously.
• Action: convert a narrow trigger into a guaranteed-width fault pulse so the receiver always sees it.
• Hook: verify the receiver’s minimum pulse width and polarity, then set the one-shot width with margin.

• Slow ramps: when the sense node lingers near V_TH, small noise and injection can create repeated crossings.
• Load-induced bounce: the protection action changes power/current, often causing rebound or ringing at the sense node.
• dv/dt and ground bounce: transient coupling shifts the apparent threshold unless two distinct decision points are enforced.

Use two thresholds (V_TH+ and V_TH−) to convert “noisy hovering” into a single, well-defined transition.

• Purpose: delay re-enable until the sense node, references, and interface logic have returned to a stable decision region.
• Common triggers: energy rebound, supply bounce, comparator recovery, or clamp discharge that can appear as a new fault.
• Rule: hold-off must be long enough to prevent re-trips, but short enough to match the intended system availability profile.

• Slow-ramp sweep near V_TH: confirm a single transition (no multi-toggle) across temperature and supply corners.
• Two-hit test: inject two consecutive faults; the second event should not show delayed or missing detection due to recovery effects.
• Reset robustness: verify that ground bounce and switching noise cannot produce unintended reset or re-enable pulses.

• Logic level compatibility: VIL/VIH and output swing across supply domains (including startup and brown conditions).
• Pulse visibility: fault must meet the receiver’s minimum pulse width / deglitch window (use pulse stretch if needed).
• Ground reference and return: prevent ground bounce from masquerading as EN/RST/FLT pulses.

• Fault pulse not seen: verify receiver min pulse width, sampling method, and any input deglitch.
• Logic mismatch: verify polarity and VIL/VIH margins; add level shifting when crossing domains.
• Spurious reset / enable toggles: verify return paths, pin filtering strategy, and proximity of noisy switching loops.

• Pulse stretch: convert narrow triggers into guaranteed-width FLT/OCP pulses.
• Level shift: ensure clean logic thresholds across supply domains.
• Optional isolation: when domain crossing requires CMTI robustness (keep it as a clear “optional block”).
• Fault taxonomy: expose a minimal fault source ID (OCP vs OVP vs external) to avoid ambiguous shutdowns.

• Capacitive coupling: dv/dt nodes couple through parasitic C into sensitive input/threshold nets.
• Ground bounce: high di/dt return currents shift the local ground reference and appear as a moving threshold.
• Supply disturbance: ripple or transient dips on the comparator/reference supply modulate decision levels.
• Measurement loops: long probe ground leads and large loops can create or hide ringing and crossings.

Debug order: ground reference → capacitive coupling → supply integrity → measurement loop.

• Kelvin sense: route sense taps separately from high-current copper; avoid shared impedance with power paths.
• Symmetric inputs: keep IN+ / IN− length and environment matched to reduce differential injection.
• Shortest sensitive loops: keep threshold network, RC, and clamps close to the input pin with tight return paths.
• Controlled ground tie: ensure the comparator/threshold “quiet reference” is not lifted by switching return currents.
• Keep-away from dv/dt loops: separate sensitive nets from switch node/gate loops using distance, layer, and plane shielding.

• Use short ground: spring ground or coax return near the measurement point.
• Minimize loop area: long ground leads create extra ringing and false crossings.
• Measure the right nodes: comparator input, threshold node, and fault output must be captured together for root-cause clarity.

• t0: first threshold crossing at the effective sense/comparator input.
• t1: fault assertion (comparator output or latched fault becomes valid).
• t2: power-path response (current begins to fall or the switch node reflects turn-off).

The system-relevant metric is (t2 − t0). Report (t1 − t0) separately only as a diagnostic.

• Pulse injection: set amplitude, width, and repetition to test deglitch and immunity margins.
• Step overcurrent: control edge rate and peak to measure true cutoff under worst-case slew.
• Step overvoltage: control dv/dt and source impedance to separate threshold error from coupling artifacts.

• Probe bandwidth and loading: insufficient bandwidth blurs edges and inflates measured delay.
• Grounding method: long ground leads create ringing and false crossings; use a short return.
• Trigger selection: triggering on noisy nodes increases timestamp jitter and misalignment.
• Channel delay mismatch: different probes/channels can skew t0/t1/t2 unless calibrated.

1. Calibrate per-channel delay using a known edge or a shared reference event.
2. Record channel offsets (Δt) and correct t0/t1/t2 consistently.
3. Document probe type, grounding method, bandwidth limits, and correction approach in the same report.

• Unified timestamps: t0 = threshold crossing, t1 = fault assertion, t2 = power-path response. Report (t2 − t0) as the primary metric.
• Repeatable stimulus: use controlled pulse/step-I/step-V fixtures (edge rate and peak must be defined).
• Node coverage: capture comparator input, threshold node, fault output, and power response in the same run.
• Measurement discipline: short ground returns, adequate bandwidth, stable trigger points (avoid noisy nodes as triggers).
• De-embedding: calibrate per-channel delay offsets and document correction methodology in the report.
• Statistics: express cutoff time as min/typ/max or P95/P99 across repeats and corners (VDD, temperature, minimum OD).

These part numbers are provided to speed up evaluation. Selection must follow the checklist above and be validated with the t0/t1/t2 method.