• Primary value: lower cost, lower power, and scalable multi-channel measurement.
• Primary constraint: common-mode rejection depends heavily on external symmetry (source impedance, protection network, and layout).
• Best fit: cost-driven DAQ/process channels where sensor wiring and input networks can be kept consistent.

1. Source impedance is controlled: Rs+ ≈ Rs− and stays stable across temperature, connectors, and cable motion.
2. Input symmetry is enforceable: matching RC/protection components and truly symmetric routing are practical.
3. Common-mode environment is manageable: CM amplitude and spectrum can be reduced with shielding/return paths/filters.

• CMRR collapses on the PCB: datasheet looks great, but real CMRR degrades sharply once wiring and protection are added.
• Cable motion changes the reading: touching/moving the cable shifts output (classic CM→DM conversion symptom).
• Channel-to-channel drift mismatch: identical channels drift differently due to small asymmetries (leakage, protection paths, connector contact).

• Source impedance is unknown or variable (long leads, multiple connectors, changing contact resistance, large bridge imbalance).
• Input protection must be asymmetric due to real-world constraints (different clamp paths, different series resistors, different RC).
• Common-mode disturbance is large and broadband, and wiring symmetry cannot be guaranteed.

• Two paths: each input is amplified through its own loop, then combined through a resistor network.
• Ideal behavior: equal response to common-mode on both paths → subtraction cancels it.
• Real behavior: unequal path impedance or gain → cancellation is incomplete → residual differential output appears.

• Ratio dominates: matching between paired resistors is typically more important than absolute accuracy.
• Higher gain tightens margins: bandwidth, output swing, and recovery become the first limits in single-supply systems.

• Source impedance mismatch: Rs+ ≠ Rs− creates unequal input drops and phase shifts, especially when filters/protection are present.
• Protection asymmetry: different series resistors, clamp leakage, or RC values produce unequal transfer under CM disturbance.
• Routing asymmetry: different parasitic capacitance to aggressors/planes causes frequency-dependent CM→DM conversion.

1. Common-mode enters both inputs: cable pickup, ground bounce, or coupling injects the same disturbance onto Vin+ and Vin−.
2. Inputs do not respond equally: Rs+ ≠ Rs− or asymmetric RC/clamps create different drops and phase shifts on each side.
3. Cancellation becomes incomplete: subtraction/combination inside the INA leaves a residual differential component at Vout.

• Low frequency: behaves like offset/drift; changes with temperature, humidity, contact resistance, and slow cable movement.
• Higher frequency: looks like spikes, jitter, or noise bursts; worsens with coupling, probe placement, and fast common-mode steps.
• Key clue: “CM disturbance in → differential residue out” increases with frequency when parasitic imbalance dominates.

• Reach: input/output can approach a rail without immediate saturation.
• Linearity: distortion and gain error remain small inside a narrower window.
• Recovery: once saturated, the output may take time to return—this is a dynamic limit, not a DC spec.

• Input CM range: the input stage must remain inside its linear window at the intended common-mode level.
• Output swing: amplified differential signal must fit inside the output linear region with margin.
• Gain: higher gain compresses available output headroom and can force saturation during spikes or scan transients.

1. Define extremes: worst-case common-mode and differential peak (including expected transients).
2. Center the trajectory: choose VMID/Vref so the amplified output waveform sits inside the linear swing window.
3. Reserve margin: allocate headroom for drift, RC settling, and ADC kickback (without assuming “rail-to-rail linear”).

• Saturation history matters: a large spike can push the output into saturation, creating a slow “tail”.
• Scan systems amplify the symptom: slow recovery can look like drift or channel memory when channels are multiplexed.
• Separate cause: recovery-limited behavior is time-dependent; CMRR loss is stimulus-dependent and often frequency-shaped.

• Gain accuracy: ratio tolerance is usually the first-order term in gain error.
• CMRR risk: ratio mismatch and asymmetric input networks reduce common-mode cancellation margin.
• Practical implication: matched pairs and symmetric placement often outperform “high-precision single resistors” scattered across the board.

• Small-signal bandwidth: verify flatness and roll-off against sensor dynamics and filter targets.
• Large-signal behavior: verify step settling and overload recovery; “slow tails” often dominate scan systems.
• Single-supply trap: high gain reduces headroom and increases the chance of clipping during spikes and channel switching.

• Better ratio matching: shared substrate processes improve tracking versus discrete parts spread over the PCB.
• Better temp tracking: ratio drift is tighter, so temperature sweeps produce more consistent channel slopes.
• More consistent parasitics: geometry symmetry reduces frequency-shaped CM→DM differences across channels.

• Voltage noise (en): often dominant at low source impedance.
• Current noise (in·Rs): grows with Rs and becomes important as impedance rises.
• Bias/leakage (Ib·Rs): converts directly into offset error and is highly sensitive to asymmetry and contamination at high Rs.

• Offset creation: Ib through source resistance produces a differential-equivalent offset at the input.
• Drift behavior: temperature, humidity, and board contamination change leakage and make the offset look like drift.
• Asymmetry matters: unequal leakage on the two inputs creates large errors even when Ib is “typical small”.

1. Define bandwidth: use the sensor bandwidth or the post-filter effective bandwidth.
2. Estimate short-term RMS: convert wideband density into RMS within the effective bandwidth.
3. Bound long-term stability: use 0.1–10 Hz peak-to-peak as a guardband for slow noise and drift-like behavior.
4. Convert to system units: map input-referred terms through gain into ADC codes or sensor engineering units.

1. Estimate effective Rs: include sensor Rs plus any series resistors and filter components seen by each input.
2. Pick dominant terms: compare en, in·Rs, and Ib/leakage·Rs using the expected operating temperature and humidity.
3. Separate time scales: use wideband terms for short-term RMS and 0.1–10 Hz for long-term stability bounds.
4. Map to system units: convert input-referred noise/offset through gain to ADC codes or engineering units.
5. Route if needed: if the dominant term cannot be reduced without major system changes, choose the architecture that owns that limit.

• Resistive load: mainly affects output current, swing, and distortion; it does not necessarily cause oscillation.
• Capacitive load: adds phase lag and can collapse phase margin; it is the common root of ringing, overshoot, and burst oscillation.
• Real interface: the output sees a mixed load (RC + ADC input behavior), so the whole chain must be verified as a unit.

• What happens: sampling switches connect an input capacitor; charge transfer creates a short, repetitive transient current demand.
• What is observed: output spikes, steps, or bursts synchronized with sampling edges; those can convert into code errors if settling is incomplete.
• Why it worsens in multi-channel: repeated switching plus insufficient recovery time produces a deterministic “memory” pattern from one channel to the next.

• Riso purpose: decouple the INA output from the sampling transient current, reducing direct kickback injection into the output node.
• RC purpose: shape high-frequency content and provide a local charge reservoir, reducing edge-driven disturbances.
• Primary tradeoff: larger R and C slow settling; if the sample window arrives early, deterministic gain/offset errors appear.

1. R-only test: remove C/ADC; confirm the driver is stable with resistive loading.
2. C-only test: add the intended Cfilter without ADC; if ringing appears, the driver is C-load sensitive.
3. ADC test: attach ADC; change sampling rate/window; disturbances that track sampling confirm kickback dominance.

• Geometry: route Vin+ and Vin− as a tight pair with equal length, same layer, and the same reference plane.
• Electrical: mirror series resistors, RC filters, and protection parts so both inputs see the same impedance profile.
• Parasitics: keep both inputs equally distant from noisy copper, planes, and shields to avoid unequal capacitance to aggressors.

• Continuous reference: the differential pair needs a continuous return path under the traces.
• No plane gaps: avoid routing across slots/splits; a detoured return increases loop area and creates unequal coupling.
• Boundary control: define the reference at the connector so common-mode current does not enter the board uncontrolled.

• Connector pinout: place Vin+ and Vin− adjacent; place a solid return reference pin nearby.
• Shield intent: ensure shield connections define a repeatable common-mode return path instead of letting it couple into the signal pair.
• Mechanical stability: strain relief and consistent cable routing reduce motion-driven changes in coupling and impedance.

• High impedance sensitivity: moisture and residues create leakage paths that translate into offset and CMRR loss.
• Guarding: use guard rings and spacing around high-impedance input nodes to intercept leakage currents.
• Symmetry requirement: treat both inputs identically; asymmetric contamination is effectively a built-in mismatch source.

• Vin+ / Vin− routed as a tight pair, same layer, same plane reference.
• No split/slot crossing under the pair; return path remains continuous.
• Series parts (R/RC/protection) are mirrored and placed symmetrically.
• Connector pinout keeps the pair adjacent with a nearby return reference.
• High-impedance nodes use spacing/guarding; both inputs are treated identically.
• Cable move/touch test does not shift the reading beyond the budget.

• Route Vin+ / Vin− as a tight pair, same layer, same plane reference.
• Do not cross splits/slots; keep the return path continuous under the pair.
• Mirror series parts (R/RC/protection) and place them symmetrically.
• Connector pinout keeps the pair adjacent with a nearby return reference pin.
• High-impedance nodes use spacing/guarding; treat both inputs identically.

• Why it fits: channel density and low power matter, while source impedance and wiring can be standardized.
• What decides success: symmetric input networks, controlled return paths, and scan settling verified under real acquisition windows.
• Typical failure sign: a few channels drift or move with cable motion—usually wiring asymmetry or ΔRs variation, not random noise.

• Use when: lead resistance and mismatch are controlled, and cable symmetry is maintained end-to-end.
• Upgrade trigger: uncontrolled cable/connector mismatch or wide ΔRs drift—field CMRR becomes unpredictable.
• Validation hook: common-mode injection plus cable move/touch test confirms whether residual DM stays within budget.

• Critical metric: the output must settle within the acquisition window after each channel switch.
• Primary trap: sampling kickback and RC time constants produce deterministic scan “memory” if recovery is incomplete.
• Practical strategy: stabilize first (no ringing), then tune RC for settling margin, and re-check order dependence.

• Uncontrolled ΔRs / cable variability: move to a topology less sensitive to input mismatch (3-op-amp INA page).
• µV-level DC stability and 0.1–10 Hz dominance: move to zero-drift/chopper INA page.
• Very high source impedance and leakage-driven errors: move to high-Z / electrochemistry INA page.

The part numbers below are practical starting points for datasheet lookup and bench validation. Final selection must follow the gate condition and the verification ladder.