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High-Voltage / Wide-Common-Mode Instrumentation Amplifiers (INA)

High-Voltage / Wide-Common-Mode Instrumentation Amplifiers (INA)

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A high-voltage / wide-common-mode INA lets a tiny differential signal ride on tens to hundreds of volts of common-mode and still appear as a clean low-voltage output—but only when CM range, fault Vdiff, headroom, and recovery are budgeted together. This page shows the practical design rules (input networks, leakage/thermal realities, transient recovery, layout safety, and validation tests) needed to make HV sensing accurate, stable, and production-ready.

What “High-Voltage / Wide-Common-Mode INA” really means

A wide-common-mode instrumentation amplifier (Wide-CM INA) measures a small differential signal riding on a very high common-mode voltage, while keeping the output in a low-voltage domain suitable for ADC/MCU interfaces.

Definition (the only three things that matter)

  • High common-mode (VCM): both inputs can sit at tens/hundreds of volts relative to system ground.
  • Small differential (Vdiff): the useful measurement is the input difference (e.g., shunt drop or sense node delta).
  • Low-voltage output domain: the amplifier output stays within a low-voltage supply so ADC/MCU can read it safely.

What it is NOT (common misreads)

  • Not isolation: there is no galvanic barrier; safety/domain separation is a system-level decision. For reinforced/basic isolation topics, use an isolated front-end page (internal link placeholder).
  • Not “any HV works”: operation is valid only inside the specified common-mode window and transient conditions.
  • Not “high Vdiff allowed”: high common-mode does not imply high differential fault tolerance; Vdiff limits are separate and often tighter.

Rule of thumb: budget VCM, Vdiff, and output headroom as three separate windows. Mixing them is the #1 source of “works on bench, fails in field.”

Typical use cases (scope only)

Bus voltage sensing

Reads an HV rail ripple/level while presenting a low-voltage output to the measurement domain.

High-side sensing (shunt/rail monitor)

Measures a small shunt drop with a common-mode near the bus; the output remains compatible with ADC/MCU.

Battery stack tap / HV sense node

Handles varying tap common-mode levels and switching transients without pulling the output out of range.

Quant hooks (fields to lock before any schematic)

Minimum field set

  • VCM_operating_max / VCM_transient: expected steady and step/ripple common-mode.
  • Vdiff_operating_max / Vdiff_fault_max: measured differential and worst-case fault differential.
  • Vout_swing_headroom: required output margin to rails under load (defines linear region).
  • Rin_effective / input current limit: sets safety energy, leakage sensitivity, and self-heating drift.
  • CMRR vs frequency & mismatch: the real-world CMRR target in the switching-noise band.
HV domain to Wide-CM INA to low-voltage output domain Block diagram showing a high-voltage bus with differential sense lines feeding a wide common-mode instrumentation amplifier that outputs to an ADC and MCU in a low-voltage domain. HV Domain Wide-CM INA LV Domain HV BUS INA CORE + − ADC MCU HV common-mode diff signal low-voltage output
High common-mode does not imply high differential tolerance. Treat VCM, Vdiff, and output headroom as separate windows.

Related: isolation-required designs should use an isolated front-end (internal link placeholder): Isolated INA / Isolated ΣΔ Modulators.

Internal concept: how wide-CM stays safe while output remains low-voltage

Wide-CM performance is easiest to reason about using a macro model. Treat the signal path as four functional blocks; each block owns a different failure mode and a different set of datasheet fields.

The 4-block macro chain (engineering ownership)

  1. Input network: sets fault energy, input current, leakage sensitivity, and self-heating drift.
  2. CM handling / protection: routes common-mode transients and clamps overload; recovery behavior often dominates field “sticking.”
  3. Differential amplifier core: provides the linear gain/noise performance for the differential signal inside the allowed windows.
  4. Output buffer: drives the low-voltage load; stability and swing limitations define the usable measurement range.

Why “high common-mode” does NOT mean “high differential tolerance”

  • Stress follows current paths: clamps and input networks convert voltage into current; Vdiff can push inputs into clamp conduction even when VCM is within range.
  • Transient behavior is its own window: fast VCM steps can saturate CM-handling blocks; recovery time becomes the real spec.
  • Mismatch turns CM into error: any asymmetry in resistors, routing, or parasitics converts VCM ripple into differential error.

Datasheet map: fields that correspond to each macro block

Input network

  • Input impedance / recommended external R range
  • Input bias/leakage vs temperature (if provided)
  • Input current limits under faults

CM handling / protection

  • VCM operating range & absolute maximum ratings
  • Common-mode step response / overload recovery (key)
  • Clamp behavior notes and conditions

Differential core

  • CMRR vs frequency (not only DC)
  • Noise density & low-frequency noise (when relevant)
  • Gain accuracy & drift (mapped later into budgets)

Output buffer

  • Output swing vs load and supply
  • Capacitive load stability guidance
  • Settling time conditions (small vs large signal)

Fast symptom-to-root-cause mapping (macro model)

  • Output “sticks” after a transient: CM handling/clamp recovery dominates; measure recovery time vs CM step.
  • DC shift with humidity/heat: input network leakage + resistor drift; check leakage paths and self-heating.
  • CMRR collapses on board: mismatch in routing/parasitics; treat symmetry as a spec, not a preference.
  • Distortion near rails: output headroom/buffer nonlinearity; confirm swing vs load and reference level.
  • Slow settling: RC placement interacts with overload recovery; separate small-signal settling from recovery tails.
Macro-block chain for a wide common-mode INA Diagram showing four functional blocks: input network, common-mode handling, differential amplifier core, and output buffer, with minimal labels and direction arrows. Macro model: 4 blocks (own the failure modes) Input Network R / RC sets I/P CM Handling Clamp protects Diff Core + – amplifies Output Buffer ADC drives Key checks Iin limit · leakage · self-heating Key checks CM step recovery · clamp tails Key checks CMRR(f) · swing vs load
Use the macro chain to avoid blind spots: most “mysterious” wide-CM issues map to input energy/leakage or CM-step recovery, not to the nominal gain.

Quant hooks (carry these into budgets and tests)

  • R_in_eq / I_in_limit: defines fault energy, clamp current, and leakage sensitivity.
  • t_recovery_CMstep: time to return inside an error band after a specified common-mode step.
  • CMRR(f): target CMRR at the switching ripple band (not just DC).
  • Vout_swing_vs_load: required headroom with the real ADC input network attached.

CM range, differential range, and headroom budgeting (the 3-window rule)

Wide-CM designs fail most often when three independent constraints are mixed into one “voltage rating.” Treat them as three separate windows: VCM (common-mode), Vdiff (differential), and Vout headroom (output linear swing under load).

The 3-window rule (what each window contains)

Window #1 — VCM (common-mode)

  • Operating VCM (steady) + ripple band conditions
  • Transient VCM steps (amplitude + edge rate)
  • Miswire / surge scenarios as explicit test cases

Window #2 — Vdiff (differential)

  • Normal measurement span (full accuracy target)
  • Fault differential (open/short/miswire-driven)
  • Input current limit is the real “fault” spec

Window #3 — Vout headroom (output domain)

  • Linear swing vs rails (near-rail nonlinearity)
  • Load-dependent swing (Rload/Cload effects)
  • Recovery tails after events define usable dynamic range

Build the budget as a table (fields, not guesses)

VCM fields

  • VCM_operating_max (steady)
  • VCM_ripple_pkpk (band + amplitude)
  • VCM_step (ΔVCM + edge rate)
  • VCM_abs_max + duration (survive vs operate)

Vdiff fields

  • Vdiff_operating_max (accuracy span)
  • Vdiff_fault_max (open/short/miswire)
  • I_in_fault_limit (sets R/clamp)

Output headroom fields

  • Vout_min / Vout_max (linear region)
  • Headroom_to_rail ≥ X mV or ≥ Y%FS
  • Load_model (Rload/Cload as fields)

If a “wide-CM” claim is missing conditions (temperature, load, step size, duration), it is not a window. Treat it as a marketing headline.

Single-supply vs dual-supply (how the windows deform)

  • Single-supply: output headroom is the tightest window; near-rail nonlinearity and load-induced compression must be explicitly budgeted.
  • Dual-supply: output window expands, but VCM and input-network energy limits do not; Vdiff faults and clamp currents still dominate survivability.
  • Dynamic requirement: specify an event (VCM step + duration) and a pass band (±X%FS) to define usable recovery, not “it eventually settles.”

Co-design note: ADC drive and anti-alias filtering are handled on the dedicated Co-Design page (internal link placeholder). This section only uses a simple load model (Rload/Cload fields).

Top mistakes (and the fastest checks)

  • Abs max treated as operating: survivability is mistaken for accuracy. Check whether the spec is “operate” or “survive.”
  • VCM checked, Vdiff faults ignored: clamps conduct under fault differentials. Verify input fault current.
  • Output headroom assumed constant: load and supply corners shrink swing. Verify Vout vs load and rails.
  • No VCM-step test: real systems switch. Define a VCM step and measure recovery into an error band.
  • Mismatch not treated as a spec: asymmetry turns CM ripple into differential error. Verify symmetry in both network and routing.
Three-window rule for Wide-CM INA budgeting Diagram with three horizontal bars representing VCM window, Vdiff window, and Vout headroom window, each split into operating, transient, and absolute maximum zones. 3-window rule (budget independently) Operating Transient Abs max Abs max ≠ accurate VCM Vdiff Vout Headroom ≥ X mV or ≥ Y%FS
Budget VCM, Vdiff, and output headroom as separate windows. A design can survive an absolute maximum event yet still fail the accuracy or recovery requirement.

Co-design details (ADC drive / AAF) belong on the dedicated page: INA ↔ ADC Co-Design.

Input attenuation & protection network design (R, clamps, RC) — and the hidden error paths

The input network decides whether a Wide-CM INA is safe, accurate, and recoverable. It must limit fault energy while preventing “hidden” error paths: leakage, self-heating drift, and capacitive coupling that converts common-mode noise into differential error.

What the input network must do (3 hard jobs)

  1. Limit current and energy: define fault input current and keep internal clamps inside safe dissipation.
  2. Preserve measurement integrity: avoid leakage-driven offsets, ratio drift from self-heating, and CM-to-diff conversion.
  3. Recover predictably: clamps and RC networks must not add long recovery tails after a surge or CM step.

Resistors (attenuation / series limiting): tradeoffs to budget

Power & self-heating

Budget resistor dissipation with P = V² / R. Self-heating creates ratio drift when the two input paths do not heat equally.

Noise & bandwidth

Higher R raises thermal noise and strengthens parasitic RC poles. Any mismatch in R or parasitic C converts common-mode ripple into differential error.

Leakage sensitivity

Large source resistance amplifies leakage and bias currents into offset. Use a simple model: V_error ≈ R_source_eq × I_leak_total.

Selection order: set fault current first, then check self-heating, then leakage sensitivity, then bandwidth/parasitics, then matching.

Clamps (TVS/diodes): the three hidden costs

  • Leakage: temperature/humidity can raise leakage and create a DC shift. Verify with high-temp soak and contamination sensitivity checks.
  • Drift vs temperature: clamp I–V changes with temperature; a “safe” clamp can still be a large error source in precision ranges.
  • Recovery tails: after a surge or CM step, clamp recovery can dominate settling time. Specify a recovery-to-error-band requirement.

Standards detail (IEC waveforms and levels) is handled on the Protection page (internal link placeholder). This section focuses on error paths and recovery behavior.

RC placement (why CMRR and dynamics change)

  • RC-to-ground is not “free”: any asymmetry converts common-mode noise into differential error.
  • RC sets transient current paths: combined with clamps, it can increase recovery tails after events.
  • Over-filtering costs settling: treat settling and recovery as separate specs, then verify both.
Typical Wide-CM input attenuation and protection network with hidden error paths Block-level diagram showing series resistors, divider resistors, clamp-to-rails elements, and RC-to-ground, with arrows marking leakage, self-heating, and capacitive coupling error paths. HV Sense Node R-series R-divider Clamp RC to GND INA IN+ IN− leakage self-heating cap-coupling Only block-level elements are shown: R-series · R-divider · Clamp · RC-to-GND
The input network is the dominant error entry point in Wide-CM designs. Budget power (self-heating), leakage-driven offset, and capacitive coupling mismatch explicitly.

Quant hooks (budget placeholders)

  • Resistor dissipation: P = V² / R (compute per element: P_each, not only total).
  • Leakage-driven offset model: V_error ≈ R_source_eq × I_leak_total (I_leak includes clamps and board leakage).
  • Self-heating drift fields: ΔT_gradient + ratio TC (treat symmetry as a requirement).
  • Recovery metric: t_recovery_after_event to return within ±X%FS after a specified VCM step or surge.

Protection standards and IEC test hooks belong on the dedicated page: Protection & Immunity.

Error budgeting for HV sensing (DC accuracy + resistor drift + CMRR reality)

System accuracy is not a single datasheet number. Build a worst-case budget that combines INA intrinsic errors, input-network drift/leakage, and real-world CMRR collapse driven by mismatch and wiring asymmetry.

Error tree (what belongs in the budget)

INA intrinsic (DC accuracy)

  • Offset & offset drift (temperature-defined)
  • Gain error & gain drift (conditions-defined)
  • Input bias/leakage × source resistance (worst-case)

Input network (dominant in HV sensing)

  • R tolerance (ratio vs absolute roles)
  • R tempco & aging (ratio drift matters most)
  • Thermal gradient (self-heating asymmetry)
  • Leakage @ temperature (clamps + board leakage)

CMRR reality (mismatch + frequency)

  • CMRR(f) at ripple/switching bands
  • CM-to-diff conversion from asymmetry (ΔR/ΔC)
  • Wiring realities: return paths and coupling

Budget table fields (fill these before picking parts)

Measurement definition

  • VCM_operating / VCM_ripple_pkpk / VCM_step
  • Vdiff_FS and BW_meas
  • Temp_range and warmup conditions

INA intrinsic

  • Vos_max and Vos_drift (by temp)
  • Gain_error_max and Gain_drift
  • Ib/Ilkg_max (not “typical”)
  • CMRR(f) at relevant bands

Input network

  • R_ratio_tolerance and R_tempco
  • Thermal gradient (ΔT_gradient)
  • Leakage @ temp (clamp + board)
  • Parasitic mismatch: ΔC / ΔR_trace

Any term without a guaranteed corner (temperature, load, frequency) is an unknown risk item. Do not let “typical” silently become the budget.

Why mismatch collapses real CMRR (the engineering view)

High CMRR assumes both input paths are symmetric. Any ΔR, ΔC, leakage difference, or return-path asymmetry converts a common-mode ripple into a differential term that looks like “signal.”

  • Divider/bridge mismatch: ratio drift and thermal gradients produce a CM-to-diff error that grows with VCM ripple.
  • Parasitic C mismatch: unequal capacitance to ground injects different currents and creates a differential component at higher frequency.
  • Wiring/return mismatch: the physical return path defines where common-mode energy flows; imbalance turns it into measurement error.

Fast checks: swap input polarity and observe sign changes; vary VCM ripple amplitude (with Vdiff fixed) and see whether the error tracks VCM.

Calibration boundary (strategy only, algorithms elsewhere)

  • 1-point offset/gain: works when error terms are stable and repeatable across temperature and time.
  • 2-point / multi-point: becomes necessary when ratio drift or thermal gradients change slope across temperature.
  • Avoid forced LUT fixes: leakage and contamination are not repeatable; LUTs can hide root causes and fail in the field.

Verification hooks (turn budget into tests)

  • Temperature sweep: separate intrinsic drift from self-heating ratio drift (ΔT_gradient correlation).
  • High-humidity / contamination sensitivity: check whether zero shifts after cleaning or coating changes.
  • VCM ripple injection: verify error vs ripple band (CMRR(f) reality).
  • Load variation: confirm output headroom does not compress readings under realistic loads.
Error contribution stack for HV sensing with a Wide-CM INA A stacked bar chart with categories for offset/drift, gain/drift, leakage, resistor ratio drift, thermal gradient, and CMRR reality. No numeric values are shown; users fill their own budget. Error budget (stack by category — fill your values) Total system error Offset / Drift Gain / Drift Leakage (temp) R ratio drift Fields R tol R tempco ΔT grad Leak @T CMRR(f) ΔC Categories only — no numbers. Fill values from corners and conditions.
Use a category stack to prevent “typical” assumptions. Treat CMRR as a frequency- and mismatch-dependent error term, not a single headline value.

Calibration details are handled on the dedicated page: Calibration Strategy.

Dynamic behavior that matters: CM steps, overload recovery, settling, and phase lag

Wide-CM issues are often dynamic: common-mode steps and overload events can saturate the output and create long recovery tails. Define event-based requirements using an error band and a recovery time limit.

Event-based view (define the step, then measure recovery)

  • Define a VCM step (ΔVCM + edge rate + duration), not just a “frequency response.”
  • Use an error band (±X%FS) and a time limit (< Y ms) as the acceptance criterion.
  • Validate at worst operating points: near-rail output, high temperature, and realistic load.

CM-step response patterns (what the waveform is telling)

Clean response

No saturation; output returns to the band quickly. This is the target behavior.

Saturation + recovery tail

Output clips then crawls back. Clamp recovery and input-network energy paths are typical drivers.

Ringing / phase lag artifact

Filtering and parasitic mismatch add lag and secondary motion. The result can be time-alignment error or overshoot.

Large-signal recovery ≠ small-signal settling

  • Small-signal settling: step response while staying inside the linear region (often specified with strict conditions).
  • Overload recovery: time to return from saturation/clamp conduction back into the linear region (often the real field limiter).

Test definition fields: ΔVCM, edge rate, operating point (near-rail or not), repetition, load model (R/C), and the error band (±X%FS).

Phase lag (what it breaks — without full control modeling)

  • Phase lag appears as measurement delay: the reported value lags the physical quantity during transients.
  • Filtering and protection can stretch tails and increase transient error even if DC accuracy is excellent.
  • For closed-loop systems, lag reduces margin (details belong on the System Control page).

Pass criteria templates (placeholders)

  • After a defined CM step, output returns within ±X%FS in < Y ms.
  • No sustained saturation: output must re-enter the linear region within the defined time window.
  • Under repeated events, no baseline creep beyond the error band (define repetition and duration).
  • Criteria must hold at worst operating point: near-rail output, high temperature, and realistic load.
CM step, output saturation and recovery with settling band Time-axis diagram showing a common-mode step, an output that saturates and then recovers, and a settling band defined by ±X%FS with a recovery time marker. Event response: CM step → saturate → recover into ±X%FS band time t0 t_recovery +X%FS −X%FS VCM step Vout saturate recover t_recovery < Y ms into ±X%FS band
Define dynamic requirements as an event response: a specified CM step and a recovery time into a defined error band (±X%FS). This separates overload recovery from small-signal settling.

Control-loop modeling belongs on the dedicated page: System Control & Dynamics.

Layout & safety implementation (creepage/clearance, zoning, leakage, thermal gradients)

Long-term stability and manufacturability come from PCB rules: strict HV/LV zoning, controlled leakage paths, and thermal symmetry for resistor networks. Treat creepage/clearance as design fields driven by standards and pollution conditions.

HV/LV zoning (the PCB skeleton)

  • Define an HV zone by nodes that can sit at high common-mode potential (not by “grounded” assumptions).
  • Create a continuous keep-out corridor between HV and LV (no copper, vias, test points, or silkscreen crossings).
  • Prevent return-path detours across slots/cuts that turn common-mode energy into measurement error.

Creepage/clearance fields (do not hardcode numbers)

Design fields

  • Standard family target (system-defined)
  • Working voltage and transient category
  • Pollution degree and material group
  • Clearance target (air gap)
  • Creepage target (surface path)
  • Coating status and boundary
  • Slots/cuts usage and impact

Practical rule

Coating reduces risk but does not replace creepage/clearance targets. Treat coating as an explicit field with inspection hooks.

Leakage path control (guard, cleanliness, coating, humidity)

Leakage sources

  • Clamp/TVS and package surface leakage
  • Board residue and ionic contamination
  • High-impedance copper near silkscreen/test pads

Actions

  • Guard ring around high-Z nodes tied to a stable low-impedance reference node
  • No-silk / no-exposed-copper keepouts near sensitive nets
  • Cleaning treated as a process parameter with inspection hooks
  • Coating boundary defined to avoid uncontrolled parasitics

Budget fields: SIR test field, leakage @ humidity/temp field, and drift-vs-humidity correlation field for root-cause isolation.

Thermal gradients (how divider ratio drift is created)

HV resistor networks dissipate power and can create ΔT across “matched” parts. Ratio drift often comes from thermal asymmetry, not only from datasheet tempco.

  • Place ratio-critical resistors in the same thermal environment (copper symmetry, airflow symmetry, distance from hot parts).
  • Separate heat sources from high-impedance sensitive nodes; avoid uneven copper pours that heat one arm more than the other.

Fields: P per resistor (P=V²/R), ΔT_gradient estimate field, and drift correlation test field (thermal image + measurement).

Manufacturing-ready checklist (layout review items)

  • HV/LV zone boundary is continuous (no accidental crossings of copper/vias/test pads).
  • Keep-out corridor includes silkscreen/mask constraints near high-Z nets.
  • Guard and cleanliness controls exist for high-impedance nodes.
  • Ratio-critical resistors have thermal symmetry (placement and copper).
  • Slots/cuts do not force uncontrolled return paths near sensitive routing.
  • Coating boundary is defined and inspectable (not “optional”).
PCB zoning for Wide-CM HV sensing: HV zone, keep-out barrier, and LV zone Top-view block diagram showing HV zone, a keep-out/barrier corridor with a slot, and LV zone with INA and ADC/MCU. Callouts indicate return-path risk, leakage risk, and thermal gradient risk. PCB zoning (top view): separate HV energy from LV accuracy HV Zone LV Zone Keep-out Barrier slot Connector TVS (entry) Divider Series R INA ADC MCU sensitive fence return path risk thermal gradient leakage risk
Start with zoning and a continuous keep-out corridor. Treat leakage and thermal symmetry as accuracy requirements, not afterthoughts.

Certification workflows and standard details belong on the dedicated Protection page: Protection & Compliance.

EMI/RFI & surge survivability without killing accuracy (staged protection)

Use staged protection to control where energy is dumped and where accuracy is preserved. Keep filtering symmetric to protect CMRR, and treat clamp parasitics and recovery as measurable system behaviors.

Staged protection (three roles)

  • Connector stage: block and dump large energy with short return paths.
  • Mid stage: shape the event (limit current, control waveform) while preserving symmetry.
  • Local stage: protect the INA pins with small, matched components and fast recovery.

Connector stage (dump energy early)

  • Place entry clamps/TVS close to the connector with a controlled, short return path.
  • Avoid dragging large parasitic capacitance into the high-impedance accuracy region.

Mid-stage shaping (filter without collapsing CMRR)

  • Keep components and routing matched on both input paths (ΔR/ΔC creates CM-to-diff conversion).
  • If using RC-to-ground, use a symmetric pair and mirror layout to control parasitics.
  • Validate that filtering does not create long recovery tails after overload events.

Local stage near INA (preserve accuracy)

  • Use small, matched series elements and small local RC where necessary.
  • Treat clamp leakage and recovery as budget items and verify recovery time in transient tests.

Pass criteria templates (placeholders)

  • Under RFI injection, output spur stays below X dBFS (define band and level as fields).
  • After EFT/surge events, reading returns within ±X%FS in < Y ms.
  • No long-tail drift: at Z ms after the event, the output remains inside the error band.
Three-stage protection chain for HV sensing: dump energy early, preserve accuracy near the INA Block diagram showing connector protection, mid-stage shaping, and local protection near the INA. Arrows indicate where energy is dumped and where accuracy is preserved. Staged protection: where energy is dumped vs where accuracy is preserved Connector stage Mid stage Local stage TVS Entry clamp GND R R C C matched small R small C local clamp energy dumped accuracy preserved
Dump large energy at the connector, shape the event in the middle, and preserve accuracy near the INA using small, matched components with fast recovery.

IEC waveforms, levels, and compliance selection belong on the dedicated Protection page: Protection Tests & IEC Hooks.

Application patterns (bus & high-side sensing) — system hooks and pitfalls

This section focuses on system wiring patterns and the pitfalls that turn high common-mode environments into measurement drift, spurs, or slow recovery. Each pattern lists two must-ask fields to lock requirements before schematic/layout work.

Pattern map (what fails first)

Common-mode energy

CM ripple and CM steps (dV/dt) can saturate or slow recovery if the protection network and layout are not staged and symmetric.

Input-network errors

Divider self-heating, leakage, and parasitic mismatch convert CM into differential error and degrade real CMRR.

Sampling and timing

Without sync to the switching phase, readings can alias or wander with load/PWM conditions even when DC specs look fine.

Bus voltage sensing (divider + reference + sync)

Two must-ask fields

  • VCM max (include surge/miswire/startup peaks)
  • Bandwidth target (average only vs ripple/transients)

Top pitfalls

  • Divider self-heating creates ratio drift (thermal asymmetry dominates).
  • Leakage in high-R networks shifts offset with humidity/contamination.
  • Unsynced sampling aliases PWM ripple into DC error.

System hooks: define a sampling sync field (phase-locked sampling), and keep output headroom away from rails during ripple to avoid nonlinearity and slow recovery tails.

High-side shunt current (wide-CM role + transient reality)

Two must-ask fields

  • Transient dV/dt (CM steps, switching edges)
  • VCM max (steady + fault + reverse cases)

Top pitfalls

  • Non-Kelvin sensing and routing asymmetry convert CM into diff error.
  • Protection/RC mismatch collapses high-frequency CMRR.
  • CM steps trigger overload recovery tails that distort waveforms.

System hooks: treat shunt + sense routing as one review object, and define a CM-step recovery criterion template (±X%FS within < Y ms) for validation.

Battery stack tap (common-mode drift + leakage dominance)

Two must-ask fields

  • VCM max (tap location across full stack range)
  • Bandwidth target (slow tracking vs pulse capture)

Top pitfalls

  • Leakage changes look like cell drift (humidity/temp sensitive).
  • Clamp recovery creates “memory” tails mistaken as electrochemical effects.
  • Over-calibration hides non-repeatable contamination/leakage mechanisms.

System hooks: add drift correlation tests (humidity/cleanliness/temperature) and define miswire survivability fields (open/short/fault recovery requirements).

Three application patterns for wide-common-mode INA: bus sense, high-side shunt, and battery tap Three side-by-side mini block diagrams showing HV source, wide-CM INA, and LV ADC/MCU. Each mini block includes two requirement field chips. Application patterns (system blocks, not a parts list) Bus sense High-side shunt Battery tap Bus Divider Wide-CM INA ADC / MCU VCM max BW target HV Shunt Wide-CM INA ADC / MCU dV/dt VCM max Stack Tap Wide-CM INA ADC / MCU VCM max BW target
Three patterns share one rule: lock requirement fields first (VCM max, dV/dt, bandwidth), then implement symmetry, staging, and recovery validation.

Other application domains (4–20 mA, medical, bio-potential) are covered on their dedicated pages: INA Application Index.

Engineering checklist (design review + validation tests + pass/fail criteria)

A reusable review and validation template: define fields, implement staged protection and symmetry, then measure recovery, drift, and survivability with pass/fail criteria placeholders.

Design review checklist (fields and implementation)

Windows & headroom

  • VCM window includes transient and miswire scenarios.
  • Vdiff window includes fault differential cases.
  • Output headroom margin field: ≥ X mV or ≥ Y%FS from rails.

Input network & drift

  • Resistor power/temperature rise fields (P=V²/R) completed.
  • Leakage budget fields (temp/humidity) exist for high-R nodes.
  • Parasitic mismatch (ΔR/ΔC/Δtrace) considered for CMRR(f).

Protection staging & layout

  • Three-stage protection implemented (entry / mid / local).
  • HV/LV zoning and continuous keep-out corridor verified.
  • Guard/cleanliness/coating boundary defined for leakage control.

Validation tests checklist (measure points and outcomes)

CM step / overload recovery

Measure VCM step, output saturation, recovery time to the error band, and tail behavior.

Temp sweep drift

Sweep temperature with controlled power states; record zero and gain vs temperature points.

Humidity / contamination sensitivity

Compare clean vs contaminated conditions; verify repeatability and humidity correlation.

Surge / ESD after-effect

Verify recovery to the error band and check for long-tail drift or memory effects after events.

Pass/fail criteria templates (placeholders)

  • After CM step, error returns within ±X%FS in < Y ms.
  • At Z ms after the event, output remains inside the band (no long tail).
  • Under RFI injection, output spur stays below X dBFS (band/level as fields).
  • Across temperature sweep, drift stays below X under defined power states.
  • After humidity/contamination stress, zero shift stays below X and remains repeatable.

Redesign triggers (stop conditions)

  • If coefficients change with humidity/cleanliness, treat it as leakage/contamination, not as a calibration problem.
  • If readings depend on PWM phase, define sync sampling fields before changing the amplifier.
  • If surge events create slow “memory” tails, rework clamp staging and recovery paths before adding more filtering.

Review deliverables (what to produce)

  • 3-window budget sheet (VCM / Vdiff / Vout headroom fields).
  • Input-network sheet (P=V²/R, temp rise, leakage, mismatch fields).
  • Staged protection block diagram with return-path notes.
  • Validation plan table (event definitions, measure points, criteria).
Engineering workflow checklist: Plan, Build, Measure, Decide Flow diagram showing four steps with icons: requirement fields, staged implementation, measurement, and pass/fail decision with a feedback loop back to planning. Checklist flow: define fields → implement → measure → decide Plan Build Measure Decide VCM max dV/dt BW target Zone Stage Match CM step Temp Humidity ESD PASS FAIL fail → refine fields → rebuild
Treat requirements as fields, implement symmetry and staged protection, then validate recovery/drift/survivability with explicit pass/fail criteria.

Production reporting schemas belong on downstream pages (selection/production). This checklist is focused on design review and validation closure.

IC selection logic: fields → risk mapping → vendor questions

High-voltage / wide-common-mode sensing succeeds only when selection is driven by three realities: (1) real common-mode transients and dV/dt, (2) fault differential events and external network errors, and (3) overload recovery behavior under defined conditions. The checklist below forces complete requirements before any datasheet comparison.

A) Mandatory selection fields (copy/paste-ready requirement form)

Treat every line below as a required input box. If any field is unknown, selection is not ready (wide-CM parts can pass “typical” specs but fail in transient, humidity, or fault conditions).

A1 · HV environment define the outside world first
VCM steady max/min
Include full operating range, stack-tap position drift, and supply reference constraints. Do not assume “nominal bus only”.
Evidence hook: measured steady CM at cold/hot + worst-case tolerance.
VCM transient + dV/dt
Capture surge/startup/inductive kick/connector bounce. Wide-CM failure is often triggered by fast CM steps, not DC CM limits.
Evidence hook: scope CM step amplitude + edge rate (dV/dt) at the connector and at the IC pins.
Fault matrix (must survive & recover)
Enumerate: open/short between sense lines, short to HV bus, short to chassis/earth, reverse wiring, and hot-plug events.
Evidence hook: define pass/fail as “no damage + returns to spec band after event”.
A2 · Differential signal & source avoid “diff is small so it’s safe”
Vdiff nominal + bandwidth target
Define full-scale differential swing, required bandwidth (or latency class), and any sampling/hold behavior in the system.
Evidence hook: target settling band and measurement window (placeholders: ±X%FS within Y ms).
Vdiff fault (worst-case differential)
Include fault differential created by miswiring, line bounce, and clamp conduction. “High CM” does not imply “high diff”.
Evidence hook: compute and test maximum diff at the IC pins during fault cases.
Source impedance + imbalance
Capture line resistance, divider mismatch, shunt lead resistance mismatch, and any series protection resistance. These convert CM into apparent diff when CMRR collapses in real wiring.
Evidence hook: worst-case mismatch model + bench verification with deliberate imbalance.
A3 · LV output domain window output must stay linear
Supply & reference framing (LV)
Define single/dual supply, output reference level, and required output polarity mapping into ADC/MCU domain.
Evidence hook: confirm output common-mode and headroom across temperature and load.
Output swing headroom margin
Set a minimum distance to rails to avoid near-rail nonlinearity and recovery slow-down. Placeholder rule: keep ≥ X mV (or ≥ Y%FS) from both rails under worst-case load.
Evidence hook: sweep output code vs load (R + C) and verify monotonicity and settling.
Load model (Rload + Cload)
Output capacitance can dominate stability and settling. Define expected ADC input network, RC filters, cable capacitance, and ESD structures.
Evidence hook: stability region check + step response with realistic Cload.
A4 · Accuracy budget & CMRR(f) reality build a system error tree (not “typ”)
DC terms: offset/drift + gain error/drift
Translate into input-referred error at the sensor node. Plan what is acceptable at cold/hot, after warmup, and after stress.
Evidence hook: temperature sweep drift + repeatability across units/boards.
Input bias / leakage compatibility
External protection and divider networks introduce leakage and temperature dependence. Use a simple model: Verr ≈ Ileak · Rsource,eq (and include temperature/humidity sensitivity).
Evidence hook: humidity/contamination A/B test and hot leakage measurement.
CMRR vs frequency: CMRR(f)
PWM ripple, switching edges, and RF pickup live in frequency. Require a minimum CMRR at the interference bands of interest (not only DC). Also require test configuration disclosure (source mismatch changes the result).
Evidence hook: inject CM ripple and verify output spur stays below the allowed band (placeholder: < X dBFS).
A5 · Overload recovery (wide-CM’s real trap) “slow return / sticky output” prevention
Overload recovery time (defined conditions)
Require recovery time after CM step and after diff fault. Recovery must be specified with CM amplitude, dV/dt, input network, supply, and load.
Pass criteria template: after CM step, output returns within ±X%FS in < Y ms; no long tail beyond Z ms.
Small-signal vs large-signal settling
Small-signal bandwidth does not guarantee large-signal recovery. Require both: small-step settling and overload recovery.
Evidence hook: step tests at multiple amplitudes and CM conditions.
A6 · Package & manufacturable safety fit must be buildable and stable long-term
Creepage/clearance & keep-out plan
Package choice must match the PCB spacing strategy. Field values depend on the applicable standard and pollution degree; keep them as explicit design inputs.
Evidence hook: PCB rule check and 3D clearance review (connector → protection → IC).
Leakage control plan (clean/coat/guard)
High-value resistor networks and contamination form hidden resistors. Define cleaning, coating, and guard strategy up front.
Evidence hook: humidity soak + contamination sensitivity test (before/after cleaning).
Thermal gradient plan for resistor networks
Divider/self-heating and nearby hot parts create gradients that look like drift. Keep hot resistors away from sensitive ratio networks. Power placeholder: P = V²/R (budget steady and fault power).
Evidence hook: IR/thermocouple map + drift correlation vs hotspot distance.
Wide-CM INA selection decision tree Flowchart from VCM level and transient to accuracy budget, recovery, safety layout fit, and shortlist, with a vendor data box feeding accuracy and recovery nodes. Selection flow (Start → Shortlist) keep text minimal; verify with conditions Start VCM level steady max/min Transient CM step + dV/dt Accuracy CMRR(f) + leakage Speed / recovery overload & settling Safety / layout package & spacing Shortlist verify conditions Vendor data required curves + test conditions CMRR(f), recovery, load No numbers are assumed: define X/Y thresholds from system noise and accuracy budgets, then verify on the real PCB.

B) Risk mapping (missing fields → real failure modes)

Missing: VCM transient / dV/dt
Likely field symptom: output saturates on CM steps, then returns slowly (“sticky” reading) or shows long tail error.
Fast check: step CM on the bench; verify recovery to ±X%FS in < Y ms under the real input network and load.
Missing: Vdiff fault
Likely field symptom: divider/protection overheats, clamp conduction distorts readings, or intermittent damage appears after miswire events.
Fast check: fault injection (open/short/miswire) + power/temperature audit; verify “no damage + returns to spec band”.
Missing: CMRR(f) requirement
Likely field symptom: PWM ripple or RF pickup converts into a false differential signal (spurs, wandering DC, alias-like behavior).
Fast check: inject CM ripple at key bands; verify output spur < X dBFS (or < X µV/√Hz-equivalent) within the measurement bandwidth.
Missing: leakage / humidity plan
Likely field symptom: zero shifts with humidity, cleaning residue, flux, or finger touch; drift looks like “sensor changed”.
Fast check: humidity soak + contamination A/B; verify Verr stays within the budget under worst-case temperature.
Missing: output headroom + load model
Likely field symptom: near-rail nonlinearity, missing codes, slow settling, or stability issues that appear only with real ADC input networks.
Fast check: load sweep (R + C) and headroom sweep; verify monotonic output and settling to the required band.

C) Vendor questions (ask for curves + test conditions, not “typical”)

Each item below should request both the curve and the exact test setup (input network, mismatch, load, supply, temperature). If conditions are missing, the data cannot be used for selection.

  • Provide CMRR vs frequency and disclose the source impedance mismatch used (or provide results for multiple mismatch cases).
  • Provide overload recovery after a defined CM step (amplitude + dV/dt) and after a defined diff fault, including load and supply.
  • Provide output swing vs load (Rload + Cload) and indicate any stability constraints or recommended isolation resistor range.
  • Provide input bias/leakage vs temperature and any notes on how external clamps/dividers affect leakage paths.
  • Provide recommended external network ranges (series R / divider R / RC) and explain tradeoffs: error, bandwidth, recovery, and CMRR impact.
  • Provide survivability evidence (ESD/EFT/surge) focusing on post-event recovery behavior and measurement stability, not only pass/fail.
  • Provide package/PCB guidance: keep-out suggestions, pin-to-pin spacing considerations, and coating/cleanliness notes for leakage control.

D) Reference examples (official links; starting points only)

These part numbers are provided only to speed up datasheet lookup and vendor condition checks. Selection must be driven by the mandatory fields above (VCM transient/dV/dt, CMRR(f), leakage plan, recovery, and package fit). No ranking is implied.

D1 · Wide-CM difference amplifiers (HV common-mode → LV output)
D2 · High-side shunt current-sense amplifiers (wide-CM role in current sensing)
Usage rule: treat every reference part as “a datasheet entry point”. Shortlisting is allowed only after the mandatory fields (A) are filled and vendor curves/conditions (C) confirm recovery and CMRR(f) under the real input network and load.

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FAQs: high-voltage / wide-common-mode INA (field failures & fast fixes)

Each answer is intentionally short and action-driven to keep the page scope tight. Use the same 4-line structure (cause → check → fix → pass) to close long-tail troubleshooting without expanding the main text.

Q1 Why does the output saturate when common-mode steps quickly, even if Vdiff is small?
Likely cause — The CM step drives the input network/clamps or internal level-shift into overload; LV output headroom collapses during recovery.
Quick check — Scope CM at connector vs IC pins; confirm VOUT hits rail and shows a long tail after CM step (note step amplitude + dV/dt).
Fix — Add staged CM energy dumping (connector-side clamp) and keep a guaranteed LV headroom margin; rebalance/relocate RC to reduce CM injection at the pins.
Pass criteria — After a defined CM step (A V, dV/dt B V/µs), VOUT returns within ±X%FS in < Y ms with no tail beyond Z ms.
Q2 How to tell “input clamp recovery” vs “INA overload recovery”?
Likely cause — Clamp recovery is dominated by clamp conduction/storage and external RC; INA recovery is dominated by internal saturation and output stage headroom.
Quick check — Measure clamp current/voltage during the event; temporarily disable or raise clamp threshold and see if the recovery tail follows the clamp change.
Fix — If clamp-limited: reduce clamp charge/storage, add series R to tame peak current, and stage clamps (far + near). If INA-limited: increase LV headroom, reduce CM step at pins, or choose faster overload recovery.
Pass criteria — With clamp path controlled (on/off or swapped), recovery time changes by < X% for INA-limited cases and by > Y% for clamp-limited cases.
Q3 Why does CMRR collapse after adding input RC?
Likely cause — RC mismatch and parasitic capacitance asymmetry convert CM into differential (especially at switching/RF bands), defeating CMRR(f).
Quick check — Inject a small CM sine/ripple at the interference band; compare output spur before/after RC and after swapping capacitors between legs.
Fix — Use tightly matched RC components, symmetric placement, and minimize unequal copper to each pin; prefer differential-first filtering with controlled CM shunting paths.
Pass criteria — For CM ripple at f = F Hz, output spur stays below X dBFS (or below X µV equivalent) across temperature and production tolerances.
Q4 Divider resistors heat up—how much self-heating becomes a real drift problem?
Likely cause — Self-heating changes resistor value (tempco) and creates thermal gradients that distort ratio accuracy, especially with mismatched thermal coupling.
Quick check — Estimate P = V²/R per resistor; measure ΔT with IR/thermocouple and correlate drift vs power step and airflow.
Fix — Increase total divider resistance (within noise/leakage limits), spread voltage across more resistors, use matched network parts, and place ratio-critical elements in a uniform thermal zone.
Pass criteria — With steady HV applied, drift due to self-heating stays within X ppm (or X%FS) after Y minutes and remains stable over airflow changes.
Q5 Why does leakage cause large offsets only at high temperature or humidity?
Likely cause — Surface leakage (flux residue, contamination, moisture film) and device/clamp leakage rise strongly with temperature; high-value networks amplify I·R error.
Quick check — Perform humidity soak or breath test (controlled), then measure bias/leakage-induced shift; compare before/after cleaning and with conformal coating.
Fix — Reduce impedance where possible, implement guard/keep-out around HV nodes, enforce cleaning process, and apply coating in leakage-sensitive zones.
Pass criteria — After humidity exposure, offset shift stays within X µV (or X%FS) at Tmax; repeating clean/contam A/B changes results by < Y%.
Q6 Can a wide-CM INA replace isolation for high-side sensing?
Likely cause — Confusing “measurement CM capability” with “safety isolation”; wide-CM moves signals across CM, but does not provide galvanic isolation.
Quick check — Identify safety requirement: if the LV domain must be galvanically separated (shock/ground fault/medical/drive systems), isolation is mandatory.
Fix — Use an isolated measurement path when required (isolated INA or isolated ΣΔ modulator/ADC). Link target: Isolated INA / Isolated ΣΔ.
Pass criteria — Isolation requirements are met by safety documentation and layout spacing rules; measurement still meets X%FS accuracy under defined CM transient conditions.
Q7 How to choose series resistance for surge/ESD without killing bandwidth?
Likely cause — Series R limits peak current and clamp stress, but forms RC poles with input capacitance/parasitics and can degrade dynamic response and matching.
Quick check — Measure input capacitance (including clamp/TVS parasitics) and estimate pole fp ≈ 1/(2π·R·C); verify step settling and CMRR(f) with injected CM ripple.
Fix — Use staged protection: larger R near connector for energy, smaller matched R near IC for symmetry; keep both legs matched and place RC symmetrically.
Pass criteria — Under surge/ESD stress, no functional damage and post-event reading returns within ±X%FS in < Y ms; bandwidth/settling meets target Z.
Q8 Output looks fine at DC but oscillates when driving an ADC—what to check first?
Likely cause — ADC input sampling or capacitive load pushes the amplifier into an unstable region; DC tests hide phase-margin issues.
Quick check — Measure ringing with a step or with ADC sampling enabled; estimate effective Cload at the output pin (filter caps + ADC input + probe).
Fix — Add/adjust output isolation resistor (Riso), relocate/resize output RC, and ensure the output stays away from rails under dynamic load; validate with real sampling conditions.
Pass criteria — With ADC sampling active, no sustained oscillation; step response settles within ±X%FS in < Y µs/ms with overshoot < Z%.
Q9 Why do two channels mismatch more in the field than on the bench?
Likely cause — Field conditions amplify asymmetry: thermal gradients, humidity/leakage, wiring mismatch, and CM noise coupling differ between channels.
Quick check — Swap sensor inputs between channels; compare mismatch vs temperature/airflow/humidity; check resistor network temperatures and routing symmetry.
Fix — Improve symmetry (routing + RC + grounding), keep ratio-critical networks in a uniform thermal zone, enforce cleaning/coating, and validate under real CM ripple/dV/dt.
Pass criteria — Channel-to-channel mismatch stays within X ppm (or X%FS) across Tmin..Tmax and humidity conditions representative of the target environment.
Q10 How to validate performance under real bus ripple and switching noise?
Likely cause — Real bus ripple combines CM ripple + fast edges; imperfect symmetry turns CM noise into differential error, often visible as spurs or wandering offsets.
Quick check — Reproduce ripple spectrum (or inject CM sine/square at key bands) and record output spectrum/time-domain error; compare at connector vs IC pins.
Fix — Improve CM containment (staged protection + symmetric RC), reduce parasitic asymmetry, and ensure CMRR(f) is adequate at the dominant ripple bands.
Pass criteria — Under defined ripple profile, output spur/error stays below X dBFS (or X%FS) and does not violate the recovery/settling time windows.
Q11 What’s a practical pass criterion for overload recovery in production test?
Likely cause — Production tests often omit realistic CM steps and dV/dt, so parts that “look good” at DC fail in field transients.
Quick check — Define a repeatable CM step stimulus (amplitude + edge rate) and a measurement window; record time to return into the error band.
Fix — Add a controlled CM-step injection path (or fixture coupling) and require vendor-provided recovery behavior under the same load and input network.
Pass criteria — For CM step (A V, dV/dt B), output enters ±X%FS within Y ms and stays within band for the next Z ms (no rebound).
Q12 Why does the reading shift when the probe/measurement instrument is connected?
Likely cause — The instrument adds leakage, capacitance, or a new ground reference path, disturbing high-impedance HV nodes and CM symmetry.
Quick check — Compare readings with a high-impedance differential probe vs single-ended probe; observe whether CM ripple or offset changes when the probe is attached.
Fix — Use differential/isolated measurement where needed, probe at low-impedance nodes, and add a defined bleed/guard strategy to prevent floating/leakage sensitivity.
Pass criteria — Connecting/disconnecting the intended measurement tool changes the reading by < X ppm (or < X%FS) across the specified frequency band and environment.
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