123 Main Street, New York, NY 10001

Submit Your BOM

Shunt-Based Current Measurement for High-Side & Isolated ADCs

Shunt-Based Current Measurement for High-Side & Isolated ADCs

← Back to:Instrumentation Amplifiers (INA)

Shunt-based current measurement is only “accurate” when the full chain—shunt thermal behavior, Kelvin routing, front-end recovery under common-mode transients, and ADC sampling/settling—meets a measurable timing and error budget.

This guide turns field symptoms (PWM edge jumps, saturation tails, random offsets, code glitches) into repeatable checks, layout rules, and pass/fail criteria that keep common-mode energy out of the differential reading.

Definition & scope: what “shunt-based current measurement” really means

Working definition

Shunt-based current measurement converts load current into a small differential voltage across RSH, then conditions it through a front-end (INA/CSA or isolated converter) so an ADC can digitize it with predictable accuracy under real common-mode voltage and common-mode transients.

Scope boundaries (to prevent off-topic expansion)
Covered on this page
  • Deployment choices: low-side, high-side, and in-line shunts.
  • Bidirectional sensing: mid-supply analog zero vs ADC digital zero calibration.
  • End-to-end chain decisions: RSH → front-end / isolation → ADC → digital calibration / filtering.
  • Practical failure modes: CM steps, dV/dt, overload recovery, and wiring-induced CMRR collapse.
Referenced (not expanded here)
  • Full IEC immunity standards and staged protection details (handled in Protection & Immunity pages).
  • Internal INA architecture deep dives (3-op-amp, chopper, PGA, etc.).
  • General ADC driver theory beyond what is needed to budget settling and timing for this chain.
Quick self-check (find the right path fast)
  1. Which deployment fits the measured node? Choose low-side / high-side / in-line before tuning any filters or calibration.
  2. Is bidirectional measurement required? Decide whether “0 A” is set by mid-supply headroom or by ADC digital calibration.
  3. Do common-mode steps or high dV/dt exist? If yes, prioritize overload recovery and CM transient rejection before chasing noise density.
Overview map: deployments + bidirectional zero
Shunt-based current measurement overview A four-panel block diagram showing low-side, high-side, and in-line shunt deployments and two ways to implement bidirectional zero. Deployments (choose one first) Low-side Rsh FE ADC Risk: ground bounce / return path High-side Rsh INA/CSA ADC Risk: high Vcm / CM steps / dV/dt In-line Rsh FE ADC Risk: routing / Kelvin / parasitics Bidirectional sensing: where “0 A” is defined Analog zero @ mid-supply 0 0A @ Vref/2 Digital zero calibration code offset = 0A DSP

Use this map to pick the deployment and the “0 A” definition first. Filtering, gain, and calibration should be designed only after the topology is fixed.

System topologies: low-side vs high-side vs isolated front-end

The core decision

Topology is chosen by where the shunt sits in the power path and by how severe the environment is in common-mode range and common-mode transients. A correct topology makes accuracy scalable; a wrong topology makes every “noise fix” brittle.

Low-side shunt
Best when
  • Highest accuracy is needed and the measurement can share the system ground.
  • Common-mode is near ground, so front-end headroom is easy.
  • Fast dynamic range is needed without large high-side CM steps.
Watch out
  • Ground bounce and return-path coupling can corrupt the sensed differential voltage.
  • “Quiet analog ground” assumptions often fail under pulsed load current.
Must verify
  • Return-path integrity (no plane splits or shared high-current vias near Kelvin sense).
  • Transient error during load steps (scope the shunt Kelvin nodes, not only ADC codes).
High-side shunt
Best when
  • High-side current (battery/bus/high-side switch) must be measured without disturbing ground.
  • Fault detection needs visibility into high-side shorts or high-side load behavior.
  • Bidirectional sensing is required with a known output reference (mid-supply or digital).
Watch out
  • Front-end must tolerate high Vcm while preserving linearity and overload recovery.
  • Switching nodes inject CM steps and high dV/dt that look like false differential voltage.
Must verify
  • CM step rejection and overload recovery time under realistic switching edges.
  • CMRR vs frequency, not only DC CMRR, because PWM harmonics dominate.
Isolated front-end
Best when
  • Measurement domain and control domain do not share a stable ground (multi-board, long cables, noisy power stages).
  • High dV/dt and CM transients are severe (inverters, drives, switching bridges).
  • Safety or functional isolation is required by system constraints.
Watch out
  • Isolation often trades immunity for latency and bandwidth constraints.
  • Synchronization and timestamp alignment may matter for multi-channel control loops.
Must verify
  • Common-mode transient tolerance and recovery under worst-case switching events.
  • End-to-end delay and coherency across channels (if multi-phase / multi-axis).
Topology chooser (fast IF/THEN rules)
  • If the shunt can sit near ground and the return path is controlled, then low-side is simplest for accuracy and bandwidth.
  • If the measured node rides on a bus or high-side switch, then high-side is required and CM step rejection becomes the main risk.
  • If the measurement ground is not stable or CM transients are extreme, then choose an isolated front-end and budget latency coherency.
Topology blocks (A/B/C): what changes and what must be verified
Low-side, high-side, and isolated shunt measurement topologies Three stacked block diagrams compare low-side, high-side, and isolated current measurement chains, highlighting common-mode risks and output forms. A) Low-side + INA/ADC Rsh INA ADC Verify: return path Risk: ground bounce B) High-side + wide-CM front-end Rsh INA/CSA ADC Verify: CM step recovery Risk: high dV/dt C) Shunt + isolated converter / isolated ADC Rsh Isolated Bitstream Verify: latency/coherency Risk: delay

Pick the topology by common-mode range and transient severity first. After that, the remaining design work becomes a bounded chain: shunt parasitics → front-end recovery → ADC settling → calibration strategy.

Shunt selection 1: value, power, and thermal gradient (accuracy starts here)

What must be decided in this section

Choose RSH so the full-scale shunt voltage is large enough for resolution, while power loss and self-heating stay within the system budget. Then control thermal gradients, because gradients create repeatability errors that calibration often cannot remove.

Compute chain (keep it bounded and measurable)
Step 1 — Full-scale shunt voltage
  • VSH,FS = IMAX · RSH
  • Constraint: VSH,FS must stay below the allowed drop in the power path.
  • Constraint: VSH,FS must stay above the minimum usable differential amplitude set by the noise/ADC budget.
Step 2 — Power and self-heating
  • PSH = IRMS2 · RSH (use RMS for pulsed/PWM loads).
  • Self-heating drives resistance change: ΔR ≈ TCR · ΔT · RSH.
  • That resistance change appears as gain error in current: ΔI/I ≈ ΔR/R.
Step 3 — Thermal gradient (often the real limiter)
  • Gradient across pads/copper can create asymmetric errors and drift.
  • Gradient is driven by copper imbalance, nearby hot parts, and airflow direction.
  • Design goal: keep the heat-flow geometry symmetrical around the Kelvin sense points.
Common traps and the fastest fixes
Trap: using ambient temperature only

Self-heating (ΔT) and copper heat spreading dominate the local shunt temperature. Use board-level thermal assumptions, not room air.

Trap: asymmetric copper or airflow

Unequal copper on the two pads forces a gradient across the sensing region. Balance copper, keep hot parts away, and avoid one-sided airflow across the shunt.

Trap: ignoring pulsed current RMS

PWM and pulse loads raise IRMS far above average, increasing PSH and ΔT. Thermal drift may look “random” across use cases if RMS is not budgeted.

Shunt selection field checklist (copy into an engineering log)
Inputs / constraints
  • IMAX (peak) and IRMS (thermal).
  • Allowed shunt drop: VDROP,max across the power path.
  • Allowed dissipation: PSH,max and local temperature limits.
  • Accuracy target: ppm or %FS budget for gain drift and offset.
  • Environment: operating temperature range and airflow conditions.
Derived quantities
  • VSH,FS = IMAX · RSH.
  • PSH = IRMS2 · RSH.
  • ΔT estimate from board copper and airflow (not ambient only).
  • ΔR/R ≈ TCR · ΔT (ppm-level gain drift estimate).
Pass criteria (fill with project budgets)
  • Steady-state shunt temperature rise < X °C at worst-case IRMS.
  • Gain drift from self-heating < X ppm (or < X %FS) over the required time window.
  • Airflow or nearby hot-part perturbation causes < X ppm reading change at constant current.
Thermal gradient map: heat paths and what they corrupt
Shunt thermal gradient and heat flow A block diagram showing a shunt resistor on copper pads, heat flow arrows, airflow direction, a nearby hot component, and a thermal gradient across the shunt that affects accuracy. Copper Copper Rsh Power path Power path I Sense Sense P = I² · R Hot part MOSFET / Ind Airflow ΔT gradient TCR → gain error

Control heat flow symmetry around the Kelvin sense region. Self-heating sets the drift floor; thermal gradients often set the repeatability floor.

Shunt selection 2: Kelvin routing, parasitic L, and pulse current reality

4-wire Kelvin rules (make the differential voltage real)
DO
  • Pick sense nodes on the shunt terminals inboard (inside the high-current pad drop).
  • Route the two sense traces as a tight pair with symmetric coupling to the same reference plane.
  • Keep sense routing away from switching nodes and high di/dt loops.
DO NOT
  • Do not place sense points on the outer copper where high current flows (extra IR drop is measured).
  • Do not split the two sense traces across different planes or across a plane gap (CM → DM conversion).
  • Do not let sense traces run parallel to the power loop for long distance (magnetic pickup grows).
Parasitic L: why PWM edges create “false differential” spikes
The mechanism

Any loop inductance around the shunt and its connections generates VL = L · di/dt. This voltage adds to VSH and can look like real current, especially during fast edges.

Quick proof on the bench
  • Compare the Kelvin nodes “inboard” vs “outboard” during a load step or PWM edge.
  • Change edge rate (gate resistor / slew setting). If the spike scales with di/dt, inductive error dominates.
  • Move the probe ground/loop. Pickup changes indicate routing/loop sensitivity.
Pulse current reality: peaks often break the chain, not averages
What to budget
  • Peak differential input: VIN,peak ≈ VSH,peak + VL,peak.
  • Front-end/ADC headroom: avoid saturation during peaks.
  • Recovery time: if overload recovery > sampling period, codes will “drag” after the event.
Pass criteria (fill with project timing)
  • No saturation during worst-case peak event, or saturation clears within X µs.
  • Settling back to within X% of final code within X samples after the event.
Parasitics checklist (R / L / thermal / coupling)
  • R (pad/copper): outboard sense points measure extra IR drop.
  • L (loop): L·di/dt spikes scale with edge rate and loop area.
  • Thermal: copper imbalance and hot neighbors create gradients across the sense region.
  • Coupling: long parallel runs near switching nodes convert CM noise into DM at the input.
Kelvin routing comparison: correct vs wrong (why waveforms differ)
Correct versus incorrect Kelvin sensing around a shunt Two-panel block diagram: the left shows correct inboard Kelvin sense routing with minimal loop pickup; the right shows incorrect outboard sensing and long routing near a switching node, leading to IR drop and L·di/dt spikes. Correct Kelvin Wrong Kelvin Power loop Rsh Front-end Sense inboard • short pair Power loop Rsh Sense Sense Pickup SW Extra IR drop • L·di/dt • CM pickup Spike

Correct Kelvin places sense nodes inside the high-current pad drop and routes a tight symmetric pair. Wrong Kelvin measures extra copper IR drop and picks up switching-induced errors that scale with di/dt.

Front-end choices: INA vs current-sense amp vs isolated modulator

Inputs that decide the category (fill these first)
  • Vcm range: Vcm_min / Vcm_max including faults and transients.
  • CM transient severity: CM steps, PWM edges, and expected dV/dt near the sense path.
  • Isolation need: safety/functional isolation, ground domains, and ground-loop risk.
  • Bandwidth & latency: pulse capture vs slow energy monitoring; control-loop delay limits.
  • Bidirectional: where “0 A” is defined (mid-supply reference vs digital zero).
  • Output form: analog into ADC vs bitstream/digital across an isolation barrier.
Category mapping rules (use these as a gate)
Choose a CSA when…
  • High-side high Vcm must be tolerated while the output stays in a low-voltage domain.
  • System needs a compact solution with integrated matching and common high-side protections (do not expand here).
  • Primary risk is CM steps + switching edges, so recovery behavior must be verified (see H2-6).
Choose an INA when…
  • Differential signal is small and high CMRR is needed across real-world wiring.
  • Source impedance mismatch is unavoidable (shunt + routing + protection parasitics).
  • Bidirectional sensing needs a clean reference point (mid-supply or digital zero strategy).
Choose an isolated modulator / isolated ADC when…
  • Ground domains differ or ground loops are likely, and CM transients are severe.
  • dV/dt immunity and safe domain separation are top priorities.
  • Latency and sync are acceptable within the system timing budget.
What each category is good at (and what must be verified)
INA
  • Good at: high CMRR with realistic mismatch and long leads.
  • Breaks when: CM steps drive input/output into overload and recovery dominates.
  • Must verify: CMRR vs frequency and overload recovery time (H2-6 test).
CSA
  • Good at: high-side sensing at high Vcm with a low-voltage output domain.
  • Breaks when: PWM edges inject CM energy and the chain recovers slowly.
  • Must verify: CM step response and settling back inside the sample window.
Isolated
  • Good at: domain separation and high CM transient tolerance (CMTI focus).
  • Breaks when: latency/sync budget is missed in multi-channel or control-loop timing.
  • Must verify: CMTI behavior and end-to-end delay/coherency.
Quick mapping (category × constraints)
Constraint
INA
CSA
Isolated
High Vcm
⚠️
✅
✅
Severe dV/dt
⚠️
⚠️
✅
Isolation required
❌
❌
✅
Low latency
✅
✅
⚠️
Mismatch immunity
✅
⚠️
⚠️
Bitstream output
❌
❌
✅
Decision flow: requirements → front-end category
Front-end category decision flow for shunt current measurement A flowchart that maps Vcm, dV/dt, isolation, bandwidth/latency, bidirectional sensing, and output form to one of three front-end categories: INA, CSA, or isolated modulator/ADC. Requirements Vcm high? High-side Isolation? Domains CSA High Vcm Isolated CMTI focus dV/dt severe? CM edges Low latency? Fast pulses Bidirectional? 0A ref Output form? Analog / bitstream INA

Use the flow to select a category first. After category selection, the design focus shifts to common-mode transient behavior and recovery verification.

Common-mode transients: why readings jump, saturate, or recover slowly

What counts as a “common-mode transient” in shunt sensing
  • CM step: a fast change in Vcm that can overload the input/output and force slow recovery.
  • CM ripple / sweep: periodic Vcm content that exposes CMRR vs frequency collapse.
  • High dV/dt edges: switching transitions that couple through parasitic capacitance and create same-polarity spikes.
How CM turns into differential error (the real paths)
  • Parasitic C asymmetry: unequal capacitance from each input node to ground or to a switching node converts CM edges to DM spikes.
  • Clamp / protection conduction: input clamps or protection networks conduct under a CM step and recover slowly, creating tails.
  • Mismatch in source impedance: Kelvin or routing mismatch collapses CMRR under real wiring conditions.
  • Layout coupling: sense traces and return currents couple to switching loops; CM energy becomes DM at the input.
  • Measurement setup: probe loops and ground references can create “spikes” that disappear with proper probing.
Key metrics to verify (because they predict field behavior)
  • CMRR vs frequency: determines how PWM harmonics leak into the measured current.
  • Input overload recovery: determines how long a CM step causes corrupted readings.
  • Output recovery / settling: determines whether the ADC sample window sees a stable value.
  • CMTI (isolated chains): determines whether high dV/dt creates bit errors or dropouts.
Minimum proof actions
  • Apply a controlled CM step and measure time to re-enter a settle band.
  • Inject CM ripple and observe output/error versus frequency.
  • Under switching edges, measure spike peak and whether it scales with edge rate.
Symptom → likely path → fastest proof → fix direction
Symptom
Likely path
Fastest proof
Fix direction
Instant jump
C asym / pickup
Change edge rate
Symmetry / distance
Saturate
Overload
CM step test
Headroom / category
Long tail
Clamp recovery
Probe in/out nodes
Limit energy / relocate
Same-polarity spike
CM→DM via C
Swap probing method
C balance / routing
Pass criteria placeholders (set X by system budget)
  • After a CM step, output returns inside a settle band (±X%) within trec < X.
  • Edge-induced differential spike peak < X mV (or < X LSB at the ADC input).
  • CM ripple/sweep produces error < X ppm (or < X LSB) inside the target bandwidth.
CM step injection test: what to inject and what to measure
Common-mode step injection waveform sketch A three-row waveform sketch showing a common-mode step, a differential spike, and an output recovery tail with placeholders for peak and recovery time thresholds. Vcm step Vdiff spike Vout recovery peak < X ±X% t_rec < X Kelvin Out

A controlled CM step test separates “noise” from recovery-limited behavior. The two key outputs are spike peak and time to re-enter the settle band.

Input network: RC filtering without breaking settling or stability

The real tradeoff

RC filtering can reduce broadband noise and edge-induced spikes, but it also slows settling and can create recovery-limited behavior inside the ADC sample window. “Lower noise but worse readings” is most often a settling / recovery issue rather than a noise-floor issue.

Differential RC vs common-mode RC (what each one actually changes)
Differential RC (DM)
  • Primary impact: settling time, pulse fidelity, and charge recovery.
  • Common failure: C too large → does not settle by Ts; R too large → weak drive and larger errors.
  • Keep in mind: DM filtering must be designed around the sample window budget (Ts and residual target).
Common-mode RC (CM)
  • Primary impact: high-frequency CM energy and CMRR behavior at frequency.
  • Common failure: mismatch between the two sides converts CM into DM (CM→DM spikes).
  • Keep in mind: symmetry is often more important than the absolute value.
What gets worse when R is too large
  • Bias-current error: ΔV ≈ Ibias · Rseries (then maps into current error by gain and Rsh).
  • Leakage stacking: protection leakage plus bias currents can look like drift, especially with temperature.
  • Noise contribution: resistor noise and its interaction with bandwidth can dominate after gain.
  • Drive weakness: larger R increases droop and slows recovery under sampling transients.
Fast proofs
  • Change R by 2× and observe whether the reading jump or droop scales with it.
  • Warm the input network area and check if the “offset-like” error tracks temperature.
  • Temporarily bypass protection elements (if safe) to isolate leakage-driven behavior.
What gets worse when C is too large
  • Settling failure: the input cannot reach the target band within Ts (dynamic error masquerades as “noise”).
  • Stability stress: the front-end sees a heavier capacitive load, increasing ringing or slow recovery.
  • Sampling transient amplification: ADC charge draw creates droop; larger C changes the recovery shape and time.
Fast proofs
  • Reduce C by 2× and check if the problem disappears inside the sample window.
  • Measure step response and see whether the output enters the settle band before Ts.
  • Observe ringing amplitude and decay; persistent ringing indicates margin issues.
Output: RC initial sizing + verification + pass criteria (placeholders)
Initial sizing workflow
  1. Define ε (allowed residual): ±X% of final value or ±X LSB.
  2. Define Ts (available settle window): ADC acquisition or sample window.
  3. Use 1st-order bound: τ ≤ −Ts / ln(ε).
  4. Map to network: τ = Req · Ceq, where Req includes front-end + series R + sampling effects.
  5. Set CM capacitors to be matched and keep routing symmetric to avoid CM→DM conversion.
Verification methods
  • Step/edge test: confirm settling into ±X% within Ts under a representative input change.
  • CM edge test: under switching edges, confirm spike peak < X and recovery < X.
  • Tolerance stress: evaluate worst-case mismatch (C tolerance) and confirm no CMRR collapse symptoms.
Pass criteria (placeholders)
  • Settling: enters ±X% (or ±X LSB) within Ts.
  • Spike: peak differential spike < X mV (or < X LSB).
  • Stability: no sustained ringing; decays below threshold within X time constants.
RC topologies: differential vs common-mode (keep symmetry)
Differential RC vs common-mode RC topology comparison Two-panel block diagram comparing a differential capacitor across inputs versus adding matched common-mode capacitors to a reference node, highlighting settling and CMRR symmetry. A) Differential RC B) DM + matched CM IN+ IN− R R Front-end Cdiff Settling IN+ IN− R R Front-end Cdiff REF Ccm Ccm CMRR Symmetry

Differential filtering is limited by sample-window settling. Common-mode capacitors must be matched and routed symmetrically to prevent CM→DM spikes.

ADC interface & sampling: gain, headroom, anti-alias, and timing budget

Interface targets (set these before tuning RC)
  • ADC input range: usable full-scale (single-ended or differential) including margin.
  • Reference/common-mode point: where the zero-current point is placed for bidirectional sensing.
  • Headroom margin: reserve margin for CM steps, spikes, and recovery without corrupting Ts.
Gain, zero point, and headroom (bidirectional mapping)

The electrical mapping must satisfy worst-case headroom:

  • Vsh = I · Rsh
  • Vadc,in = Gain · Vsh + Vzero
  • Worst-case: |Vadc,in| + spikes + recovery error must stay inside ADC range during Ts.
Two bidirectional strategies
  • Analog zero (mid-supply): 0 A maps near mid-range; simple ADC usage, but reference stability matters.
  • Digital zero (calibrated): 0 A is digitally removed; flexible, but recovery/consistency under CM events becomes critical.
Sampling transient: charge draw, droop, and recovery inside Ts
  • When the ADC sampling switch closes, Cin draws charge from the front-end output.
  • This creates a droop (instant drop) followed by a recovery curve.
  • If recovery does not enter the settle band within Ts, the error looks like “noise” but is actually recovery-limited.
  • Req includes front-end output impedance, series R, and routing; Ceq includes RC capacitors plus Cin.
Budget link (placeholders)
  • Define settle band: ±X% (or ±X LSB).
  • Define Ts: acquisition window / sample window.
  • Require: droop peak < X and trec < X inside Ts.
Anti-alias (bounded to this chain)
  • Signal bandwidth first: set the required measurement bandwidth (BW target).
  • Noise folding control: limit out-of-band noise that would alias into the measurement band.
  • Do not violate Ts: any additional filtering must still satisfy settling within the sample window.
Chain decision order
  1. Set BW target and Ts/ε.
  2. Pick gain and zero point with headroom margin.
  3. Size RC to meet settling first, then reduce alias/noise within remaining margin.
Output: sampling-window budget (fill-in template)
Field
Value (placeholder)
Ts
X
ε (residual target)
±X% or ±X LSB
R_eq
Front-end + series R + routing
C_eq
Input caps + Cin
Droop_peak
X
t_rec
X
Headroom
X%
BW_target
X
AA choice
RC / 2nd order / active / digital
Pass criteria (placeholders)
  • Settling: enters ±X% within Ts.
  • Droop: droop peak < X (mV or LSB).
  • Recovery: trec < X (µs or samples).
Sampling transient: Cin charge draw → droop → recovery inside Ts
ADC sampling charge draw sketch for shunt measurement front-ends A block diagram and waveform showing front-end output driving an ADC sampling switch and input capacitance, producing a droop and recovery curve bounded by a settle band within Ts. Circuit view Front-end Rsource R ADC SW Cin charge Waveform view ±X% Droop < X Ts t_rec < X SW closes

The input network must be sized for droop and recovery inside Ts first; anti-alias and noise benefits only count after the settle band is met.

Error budget & calibration: offset/drift, gain, CMRR, and thermal terms

Error layering (what changes over time and what changes with events)
  • Static: offset and gain terms that appear even in steady conditions.
  • Drift: temperature-dependent movement (offset drift, gain drift, Rsh TCR, reference tempco).
  • CM / wiring reality: CMRR versus frequency plus CM→DM conversion caused by mismatch and layout.
  • Dynamic: overload / recovery / settling inside Ts during CM transients or sampling events.

Calibration is strongest against static and parts of drift. Recovery-limited behavior under CM events must be controlled by headroom, symmetry, and verification.

Budget on a common reference plane (recommended workflow)
Recommended reference plane
  • Convert each term to equivalent shunt voltage (Vsh, µV) or equivalent current error (Ierr).
  • Use a consistent mapping: I → Vsh (I·Rsh) → front-end gain → ADC code.
  • Record where each term is injected: shunt, front-end input, output, ADC sampling, or digital domain.
Practical split (what calibration can and cannot remove)
  • Usually removable: DC offset and DC gain (two-point), if conditions are stable.
  • Partially removable: drift (temperature points), if correlation is stable and gradients are controlled.
  • Not reliably removable: CM event recovery, saturation tail, and Ts settling failures.
Calibration strategy (select by dominant terms)
Two-point (0 + FS)
  • Use when offset and gain dominate and are stable across time and temperature.
  • Define 0 A condition and full-scale condition with traceable stimulus rules.
  • Store coefficients with versioning (board/lot/firmware) for traceability.
Temperature points (drift management)
  • Add temperature points when drift dominates or when gradient sensitivity is unavoidable.
  • Track both the sensor temperature and the shunt/PCB gradient indicator if available.
  • Prefer simple models unless stability is proven; complexity without stability becomes error.
Online vs offline
  • Offline: simplest and safest; best for production calibration and periodic service.
  • Online: only when a reliable 0 A / reference event exists and does not disturb the plant.
  • Any online update must include sanity checks and rollback rules to avoid self-corruption.
Leakage and protection-induced bias (model it explicitly)
Simple leakage model (placeholders)
  • Ieq = Ibias + Ileak(protection) + Isurface(PCB)
  • Verr ≈ Ieq · Rsource
  • Ierr ≈ Verr / (Rsh · Gain)

This term often explains “touch / humidity / temperature” sensitivity because leakage paths and source impedance shift together.

What must be recorded
  • Protection element type and leakage conditions (temperature and voltage).
  • Series resistance and its tradeoffs (protection vs bias/noise vs recovery).
  • Board cleanliness / coating / guard usage for high-impedance nodes.
Output: error-budget field list (copy-ready template)
Signal mapping
  • Rsh, Imax, Vsh_FS, Gain, Vzero, ADC range, headroom margin
Static
  • Offset, gain error, reference error, ADC offset, resistor ratio error
Temperature
  • Rsh TCR, front-end drift, gain drift, reference tempco, gradient risk flag
Common-mode / wiring reality
  • CMRR(f) placeholder, CM step amplitude, expected dV/dt, CM→DM sensitivity (symmetry/layout flag)
Dynamic / sampling
  • Overload recovery, settling within Ts, droop_peak, t_rec, saturation tail behavior
Leakage & protection
  • I_leak@T/V, R_source, humidity sensitivity check, PCB cleaning/coating/guard notes
Calibration control
  • Two-point? temperature points? online/offline? coefficient versioning and rollback rules

Each field should include: measurement condition, source (datasheet vs bench), calibration removability (Yes/Partial/No), and a residual acceptance threshold.

Error tree: I_meas → offset / gain / temp / CM / dynamic
Error tree for shunt-based current measurement A five-branch error tree from measured current to offset, gain, temperature, common-mode, and dynamic terms, with small tags for key contributors. I_meas Offset Gain Temp CM Dynamic Ibias / leak ADC offset Rsh tol Vref / ratio TCR / drift Gradient CMRR(f) CM→DM Settling (Ts) Recovery Droop Calibrate static first; manage drift with temperature points; control CM and dynamic terms with symmetry, headroom, and verification.

Use the tree to decide ownership: which term is removed by calibration and which term must be constrained by design and bench acceptance tests.

Verification: reproduce and diagnose field failures on the bench

Reproduction rules (avoid test-induced artifacts)
  • Probe the shunt correctly: measure across Kelvin sense points; avoid long ground clips that create fake spikes.
  • Record the CM condition: Vcm, dV/dt, cable length/shield, and switching edges must be logged.
  • Include timing: log Ts and trigger alignment; recovery must be judged against the sampling window.
Minimal instrument set (capability-based)
  • Injection source: a controllable step/pulse source for CM or edge stimulation.
  • Current stimulus: a known current step or pulse path (real load, pulse load, or controlled current source).
  • Oscilloscope: with differential measurement capability (or safe isolated method).
  • Optional: temperature stimulus (chamber or heat/cool) and FFT capability for noise mapping.
Three standard test conditions (template)
T1) Common-mode step & recovery
  • Inject: a controlled CM step (amplitude and edge rate recorded).
  • Observe: differential spike peak, saturation tail, and recovery time back into the settle band.
  • Pass: spike_peak < X; t_rec < X; meets ±X% within Ts.
T2) di/dt pulse: L·di/dt false-DM vs real current
  • Inject: a repeatable current pulse with a logged edge rate (di/dt).
  • Differentiate: L·di/dt artifacts are extremely sensitive to Kelvin point placement and loop area.
  • Pass: Kelvin-insensitive result within X; no spike that scales with routing rather than current.
T3) Noise mapping: density / 0.1–10 Hz to resolution
  • Measure: noise density (FFT) and low-frequency variation if applicable.
  • Map: I_rms ≈ V_rms / (Rsh · Gain); record bandwidth used for integration.
  • Pass: resolution meets X in the defined bandwidth; no unexplained 1/f corner inflation.
Probe position rules (the critical part)
  • Probe A: across Kelvin sense points (true Vsh).
  • Probe B: front-end output (pre-ADC) to measure overload and recovery.
  • Probe C: CM node / switching node to correlate edges with measurement artifacts.
  • Prohibited: long ground leads and large probe loops; these can generate “spikes” that do not exist in the circuit.
Bench setup: injection source, shunt, front-end, ADC, and probe locations
Bench setup diagram for shunt measurement verification A test bench block diagram showing injection sources, shunt with Kelvin sense points, front-end, RC network, ADC, and three labeled probe positions A/B/C. CM step Injection Pulse load di/dt Shunt Kelvin Front-end RC ADC Sampling Probe A: Vsh Probe B: Vout Probe C: Vcm Log Vcm and timing; measure Vsh at Kelvin points; correlate edges with output recovery and Ts acceptance. Use the same probe locations for every run to keep results comparable across boards and lots.

Probe placement and loop area control are mandatory; otherwise the bench setup can create artifacts that look like CM or di/dt problems.

Layout & grounding: Kelvin, return paths, and keeping CM out of DM

In shunt-based current measurement, most “mystery errors” come from CM → DM conversion created by routing asymmetry, broken return paths, and probe-loop mistakes. The goal is to keep Kelvin sensing stable under high current, high di/dt, and real wiring conditions.

A) Kelvin sense pair: position first, symmetry second
  • Sense point placement: pick off the shunt voltage from the inner pads (inside the force-current pads), not from the high-current copper.
  • Symmetry target: aim for equal impedance and equal coupling (same layer, same reference plane, same environment), not “equal length”.
  • Keep the pair together: route as a tight pair to reduce loop area and reduce magnetic pickup from the power loop.
  • Reference consistency: keep the Kelvin pair referenced to a continuous plane to prevent return-path detours.
B) Return-path continuity: most CM pickup starts with broken return
  • Do: keep a solid reference plane under the Kelvin pair and the analog front-end input network.
  • Avoid: plane splits, slots, or “moats” under sensitive routing (they force return current to detour and form large loops).
  • Via discipline: if layer changes are unavoidable, ensure the reference transition is controlled (no sudden “floating” segments).
  • CM → DM trigger: any asymmetry (one trace over plane, one over void) converts common-mode fields into differential error.
C) Spatial separation: keep the high-current loop away from the measurement loop
  • Minimize the power loop area (force + return) to reduce emitted magnetic field.
  • Route Kelvin outside the power loop and keep it away from switching nodes (SW), phase nodes, gate-drive loops, and bus bars.
  • Do not parallel-run Kelvin traces with noisy nodes; long parallel segments build capacitive coupling.
  • Place the input RC close to the front-end input pins to reduce the “antenna” length of the sensitive node.
Output: layout checklist (priority order) + prohibited items
P0 — must-pass
  • Kelvin sense points taken from the inner pads (not from high-current copper).
  • Continuous reference plane under Kelvin pair and front-end input network (no splits/slots).
  • High-current loop minimized and kept away from the measurement region.
  • Defined probe points for Vsh (Kelvin) and Vout (pre-ADC) to prevent measurement artifacts.
P1 — strongly recommended
  • Kelvin pair routed together with equal environment (equal coupling) and minimal via count.
  • Sensitive nodes kept short; input RC placed close to the front-end pins.
  • Noisy nodes (SW/phase/gate) routed far and never parallel to Kelvin traces.
  • Shunt placed to simplify both force-current path and Kelvin pickoff geometry.
Prohibited items (red flags)
  • Sense pickoff from outer pads / power copper (force-path IR drop becomes “signal”).
  • Kelvin traces crossing plane splits or running over voids.
  • Long parallel routing next to switching nodes or phase nodes.
  • Large probe loops (long ground leads) used to “verify” spikes.
Top view: good layout vs bad layout (power loop, Kelvin, plane split)
Good vs bad layout for shunt Kelvin sensing A side-by-side top-view diagram showing a good layout with a small high-current loop, tight Kelvin pair over a solid plane, and a bad layout with plane split, parallel run near switching node, and CM to DM coupling. GOOD Solid return plane High-current loop (small) Shunt Kelvin pair (tight) BAD Plane split High-current loop (large) Shunt Kelvin crosses split SW Coupling CM → DM

The goal is equal coupling and continuous return. Plane splits and asymmetric environments convert common-mode fields into differential error.

IC selection logic: what to ask vendors and how to pick parts without regret

Selection should be driven by field constraints (Vcm, dV/dt, bandwidth, recovery, headroom, leakage), not by typical headline numbers. The following flow converts requirements into vendor questions and risk checks.

A) Gate conditions (filter out wrong classes first)
  • Common-mode range: include startup, fault, and reverse energy flow (bidirectional zero placement).
  • dV/dt & ground domains: if CM transients are strong or grounds must be separated, prioritize isolated amplifier or isolated ΣΔ modulator.
  • Signal dynamics: define the bandwidth and the allowed settling within Ts; recovery often dominates pulse accuracy.
  • Output interface: analog-to-ADC vs bitstream/digital isolation; this changes validation and sampling timing.
B) Must-ask specs (ask for curves and conditions, not “typical”)
  • Vcm range over temperature and fault conditions (include negative CM if applicable).
  • CMRR vs frequency (curve) and the test source impedance conditions.
  • Overload recovery: input overdrive amplitude, duration, and recovery-to-error-band definition.
  • Output swing & load stability: capacitive load region, minimum Riso, ADC-driver suitability.
  • Offset/drift and gain error/drift at the intended gain and temperature range.
  • Input bias & leakage vs temperature (critical with series R and protection networks).
  • Noise: 0.1–10 Hz p-p (if DC precision matters) and wideband density for the target bandwidth.
  • Power & thermal: Iq, enable behavior, and thermal derating in the real enclosure.
  • Isolation path (if used): CMTI, isolation rating, delay/bandwidth, and multi-channel sync support.
C) Spec → risk mapping (why each question exists)
  • CMRR@100k–1M → switching ripple becomes “current” (spurs, jittery reading).
  • Recovery time → pulse tail error and wrong peak capture within Ts.
  • Vcm range → clipping or wrong polarity during regeneration / reverse current.
  • Output stability → ADC input capacitance and RC networks trigger ringing or oscillation.
  • Bias/leakage → zero drift that changes with cable touch, humidity, or temperature.
  • Noise metrics → resolution shortfall when bandwidth and filtering do not match the target.
D) Reference part numbers (starting points only)

These examples provide quick anchors for datasheet lookup. Final selection must be driven by the questions and risk checks above.

  • General CSA (analog output): TI INA181 / INA2181 / INA4181; TI INA190; ADI AD8418; ADI LTC6102 / LTC6102HV
  • PWM / inverter environment: TI INA240 (enhanced PWM rejection)
  • Wide / negative common-mode needs: TI INA293 (for systems with reverse conditions and wide CM)
  • Digital monitor (system-level current/power): TI INA226 (I²C/SMBus monitor class)
  • Isolated amplifier path: TI AMC1301; TI AMC3301 (integrated isolated supply variant)
  • Isolated ΣΔ modulator path: TI AMC1306M25; ADI ADuM7701; ADI AD7403
Output: vendor inquiry template (copy/paste)
Subject: Current sensing front-end for shunt (CM transient & recovery critical)
Requirements – Shunt range: ______ mV (bidirectional); Rsh: ______ mΩ; Imax: ______ A – Common-mode range (incl. faults): ______ V to ______ V; expected dV/dt: ______ V/ns – Bandwidth / step behavior: ______ kHz; sampling window Ts: ______ µs; residual target: ±_____% within Ts – Output interface: analog-to-ADC / isolated amplifier / isolated ΣΔ bitstream – Temperature range: ______ °C to ______ °C; supply: ______ V; Iq target: ______ mA Please provide – CMRR vs frequency curve and test conditions (source impedance, gain) – Overload recovery time with conditions (overdrive amplitude/duration; recovery band definition) – Output swing limits and capacitive-load stability region (recommended Riso/RC) – Input bias current and leakage vs temperature (including input clamp behavior) – Offset/drift and gain error/drift across temperature at the intended gain – Noise: 0.1–10 Hz p-p (if available) and wideband noise density – If isolated: CMTI, isolation rating, delay/bandwidth, multi-channel sync method Acceptance criteria (placeholders) – No clipping at worst-case Vcm; recovery t_rec < ______ µs after CM events – Meets ±_____% within Ts under pulse conditions – No instability with ADC input capacitance and planned RC network

Replace placeholders with measured or system-defined values. Any missing “conditions” should be treated as a risk until verified on the bench.

Spec → risk map (selection is a risk-control exercise)
Spec to risk mapping for shunt current sensing IC selection A two-column mapping diagram linking key specs such as CMRR versus frequency and recovery time to field risks like PWM ripple error and pulse tail error. Specs to ask CMRR vs frequency Overload recovery Vcm range Output stability Bias & leakage Noise metrics Field risks controlled PWM ripple error Pulse tail error Clipping / polarity fail Ringing / oscillation Zero drift sensitivity Resolution shortfall

If a spec is missing conditions or curves, treat it as a risk until verified with the bench tests defined earlier (CM step, di/dt pulse, and Ts settling).

Request a Quote

Accepted Formats

pdf, csv, xls, xlsx, zip

Attachment

Drag & drop files here or use the button below.

FAQs: shunt-based current measurement (field symptoms → checks → fixes)

Each answer is intentionally short and actionable. Use placeholders (X, Ts, trec) to match the project’s noise and timing budget.

Why does the current “jump” at switching edges / PWM transitions?
Likely cause: CM step couples into DM (asymmetric routing / broken return / finite CMRR at fsw).
Quick check: Trigger on PWM edge; compare Kelvin Vsh vs output vs ADC code; spike aligns with Vcm edge.
Fix: Restore return continuity; keep Kelvin pair equal-coupling; add symmetric CM filter / move RC to pins.
Pass criteria: Edge-correlated spike < X mV (Kelvin) and spur at fsw < X dBc in code.
Why does adding input RC reduce noise but make pulse current smaller / slower?
Likely cause: RC + front-end + ADC sampling load cannot settle within Ts (droop / phase lag / slew limit).
Quick check: Step/pulse inject; measure time to ±X% at ADC input; compare with Ts and trigger-to-sample delay.
Fix: Reduce R or C; use split R (each leg) + small Cdiff; increase headroom/GBW or move to isolated ΣΔ.
Pass criteria: Settles to ±X% within Ts and pulse amplitude error < X% over the capture window.
Why does high-side sensing saturate at large dV/dt and recover slowly?
Likely cause: Input protection / internal nodes charge during CM transients; recovery limited by overload behavior and output headroom.
Quick check: Apply CM step (or real PWM); record trec to return within ±X% band; correlate with Vcm amplitude.
Fix: Choose CSA/INA with specified recovery; add symmetric CM RC; move to isolated amplifier/isolated ΣΔ if dV/dt is extreme.
Pass criteria: No clipping under worst-case Vcm; trec < X µs after CM events; no long tail in code.
Kelvin routing is done—why is an L·di/dt spike still visible?
Likely cause: The power loop still has inductance; Kelvin pair still forms loop area or sees unequal coupling; probe loop exaggerates spikes.
Quick check: Compare Kelvin-at-pads vs pickoff-from-copper; repeat with short ground spring probe; spike scales with di/dt.
Fix: Shrink force-current loop; keep Kelvin tightly paired over solid plane; avoid parallel run near SW; define proper probe points.
Pass criteria: Kelvin-measured spike < X mV at worst di/dt and does not cause ADC clipping or recovery tail.
Why does the bidirectional zero point drift for a while after power-up?
Likely cause: Thermal settling (shunt self-heating / gradient), reference warm-up, or leakage/bias stabilization shifts the effective offset.
Quick check: Log zero-current code vs time; compare with shunt temperature proxy; verify supply/reference ramp and steady state.
Fix: Use warm-up gating; apply zero calibration after stability; reduce gradients (copper symmetry / airflow control).
Pass criteria: Zero drift slope < X LSB/min after Tsoak; offset within ±X LSB across the specified window.
Why do different lots / boards show very different offsets (seemingly random)?
Likely cause: Leakage + bias interacting with series R, flux/residue moisture, input clamp leakage variation, and board-level thermal gradients.
Quick check: Measure offset at two temperatures and two humidities; inspect for residue; compare with/without input series R and clamp path.
Fix: Tighten cleaning/coat process; reduce input R where possible; add guard/keepout; define per-board zero trim.
Pass criteria: Board-to-board offset spread (3σ) < X LSB after calibration; drift vs humidity < X LSB.
Why does the ADC code show periodic spikes while the INA output looks clean?
Likely cause: Sampling instant interference (digital activity / mux / reference kick), or ADC input charge injection not visible on a slow-probed analog node.
Quick check: Align code spikes with SPI/I²C bursts or PWM timing; probe at ADC pin with low-inductance tip; disable features one by one.
Fix: Move sampling away from digital bursts; add small series R at ADC pin; improve reference decoupling and split analog/digital returns.
Pass criteria: Code glitch rate < X ppm and glitch amplitude < X LSB under worst-case switching and traffic.
How to distinguish “CM-coupled fake differential” from real current change?
Likely cause: Fake DM is edge-locked to Vcm and scales with dV/dt; real current follows the load dynamics and scales with shunt and loop inductance differently.
Quick check: Hold load constant; vary PWM edge speed or Vcm amplitude; if spike changes without load change, it is CM-coupled.
Fix: Improve symmetry/return; increase CM filtering; select higher CMRR(f) / faster recovery; use isolated chain if needed.
Pass criteria: With constant load, edge-locked component < X% of full-scale and < X LSB in code.
Why does using a larger shunt resistor sometimes worsen accuracy?
Likely cause: Higher power and thermal gradient increase R drift; reduced headroom increases clipping/recovery errors; RC/bias terms become more visible.
Quick check: Compute P=I²R and estimate ΔT; measure gain/offset vs temperature; check for clipping at pulse peaks and CM events.
Fix: Reduce Rsh or use higher power/low-TCR shunt; improve heat spreading symmetry; raise gain elsewhere if headroom allows.
Pass criteria: Thermal-induced gain error < X ppm over the duty cycle; no clipping; post-event recovery within trec<X µs.
Why is low-side sensing stable, but high-side sensing tends to chatter / jump?
Likely cause: High-side sees large Vcm swing and stronger coupling; finite CMRR(f) and recovery dominate, while low-side avoids most CM stress.
Quick check: Compare same front-end in both locations; record error vs Vcm amplitude and PWM edge speed; observe recovery tail.
Fix: Use CSA/INA optimized for PWM rejection; add CM filter; improve layout symmetry; switch to isolated chain for harsh CM.
Pass criteria: High-side error under PWM is within ±X% and does not increase with dV/dt beyond the allowed limit.
Will isolated-chain delay destabilize a current control loop (quick screening)?
Likely cause: Added measurement delay reduces phase margin; instability risk rises when delay is a large fraction of the loop time constant.
Quick check: Compare total sensing latency (tdelay) to loop crossover period; observe oscillation or overshoot changes after enabling isolation path.
Fix: Reduce filter latency; increase sampling rate; choose lower-latency isolation; adjust loop bandwidth (keep tdelay margin).
Pass criteria: No new oscillation; step response meets overshoot < X% and settling < X ms with the isolated path enabled.
How to do fast production self-test to guarantee gain/zero consistency?
Likely cause: Without a defined test path, offset/gain spread and assembly leakage appear as “random” field failures.
Quick check: Run two-point test (0 A and Ical); log code histograms; cross-check temperature and soak time control.
Fix: Add calibration injection or known load pulse; store per-unit trim; add leakage screening (humidity/temperature spot check).
Pass criteria: Offset within ±X LSB and gain within ±X ppm after trim; test time < X s; yield > X%.
icnavigator

ICNavigator helps engineers find verified ICs, alternatives, and fast quotes.

Explore
Categories
  • Power Management
  • MCU
  • Automotive ICs
  • Sensors
  • Interface & Transceivers
  • Analog Front-End
Get in Touch
  • Email: hello@icnavigator.com
  • WeChat/WhatsApp: +86-xxxx

© 2025 ICNavigator. All rights reserved.