• Output form: analog across the barrier; typically followed by an ADC in the low-voltage domain.
• System “cost” moves to: analog settling, ADC drive/AA filter interaction, headroom near rails, and recovery from overload/common-mode steps.
• Best fit: systems already built around a specific ADC chain and analog filtering strategy.

• Output form: ΣΔ bitstream (or encoded digital); requires decimation/filtering to produce samples.
• System “cost” moves to: filter/decimation latency, synchronization, windowing around switching events, and integrity checks against glitches.
• Best fit: noisy domains where “digitizing early” simplifies routing and robustness — as long as latency is budgeted.

• Why it forces isolation: “measurement reference” and “system ground” are not guaranteed to be the same node.
• What to verify: output stability while the remote ground shifts; check for offset steps and long-lead coupling sensitivity.

• Why it forces isolation: fast common-mode steps inject charge across parasitic capacitances and can corrupt analog output or bitstream framing.
• What to verify: transient survivability (CMTI), overload recovery time, and “no false codes / no framing loss” during switching edges.

• Why it forces isolation: reinforced/basic isolation requirements constrain the architecture before accuracy tradeoffs are even discussed.
• What to verify: isolation rating class, working voltage constraints, and the “barrier + layout” consistency (creepage/clearance are selection & layout gates).

A robust bitstream / encoded stream across the barrier; samples are produced by a defined decimation filter in the LV domain.

• Latency & sync: decimation group delay defines “when data is trustworthy”.
• Windowing: switching events can require measurement windows and integrity checks.
• Clocking: shared clock strategy affects coherency across channels.

• Control-loop feels delayed (“slow reaction”), or phase margin degrades due to measurement latency.
• Transient-induced glitch bursts in the stream cause sporadic bad samples or framing slips.

• Step stimulus → measure time-to-accuracy (latency breakdown: modulator + filter + transport).
• dv/dt stress sweep → count invalid samples / resync events during switching edges.

An isolated analog representation that is then digitized by an ADC; filter/AA/settling are still analog-domain responsibilities.

• Settling & drive: output swing, load stability, and AA filter interaction define real accuracy under dynamic conditions.
• Recovery: common-mode steps can saturate stages; recovery time becomes the limiting spec.
• Reference ownership: LV-domain ADC reference and ground behavior matter immediately.

• Dynamic errors: “looks accurate at DC” but fails on steps/pulses due to incomplete settling.
• Oscillation or ringing when driving capacitive filters/ADC inputs; measurement shifts with probe loading.

• Separate tests: differential step vs common-mode step → measure settling and recovery independently.
• Drive sweep: vary load/Cfilter → confirm stable region and repeatable settling margin.

Digital samples are created in the HV/noisy domain and cross the barrier as a digital bus/link.

• HV-domain ownership: power integrity, ground bounce, and EMI in the noisy domain directly set the ADC noise floor.
• Thermal & placement: HV-side temperature gradients and coupling become first-order error sources.
• Link robustness: framing/CRC/resync is required when the digital link is stressed.

• Unexpected noise floor elevation that tracks HV power switching activity.
• Digital integrity events (CRC errors / retries / resync) under dv/dt or ESD/EFT stress.

• Inject HV power ripple / ground bounce → measure code noise and spur movement.
• Stress the digital link → log CRC/error counters and confirm deterministic recovery behavior.

• Front-end: input offset, gain error, temp drift, bias/leakage × source impedance.
• Layout: leakage paths (ESD/clamps/PCB contamination) that translate into input-referred offset.
• Power/barrier: low-frequency supply modulation that looks like drift under slow logging.

• Choose 1-point / 2-point / multi-point calibration based on coefficient stability across temperature and time.
• Write a leakage budget: worst-case clamp leakage + PCB surface leakage + source impedance → input-referred offset.
• Separate “true drift” from supply modulation by controlled power ripple injection during characterization.

• Short-input / zero-input runs vs temperature: record offset vs time, then fit drift (avoid mixing with 1/f noise).
• Known differential injection: verify gain error and gain drift across temperature points.
• Clean vs humid/contaminated comparison: confirm whether leakage dominates DC error.

• Front-end: input-referred noise density, 1/f corner, resistor thermal noise, source impedance interaction.
• Decimation: OSR + filter define effective bandwidth and how noise maps into the reported samples.
• Power/layout: low-frequency modulation can masquerade as “extra 0.1–10 Hz noise”.

• Define the measurement window/bandwidth first, then choose OSR and filter (avoid comparing noise with mismatched bandwidth).
• Budget both 0.1–10 Hz (slow wander) and wideband (RMS resolution) using the same end-to-end bandwidth definition.
• Control source impedance and input network values so thermal noise and bias/leakage coupling do not dominate.

• 0.1–10 Hz: long capture → detrend → peak-to-peak in the defined window.
• Wideband: specify bandwidth → compute RMS or spectrum density consistently.
• Power modulation: controlled ripple injection → verify whether the “noise” is actually supply-induced.

• Barrier: parasitic capacitance turns dv/dt into displacement current.
• Layout/return: where that current returns determines whether it becomes measurement error.
• Receiver: thresholds/deglitching decide whether glitches become bad samples or framing loss.

• Place input RC to keep transient energy out of sensitive nodes (position matters more than “RC value”).
• Provide a short, intentional common-mode return path so displacement current avoids the measurement reference.
• Use receiver-side deglitching and framing supervision for digital/bitstream paths.

• dv/dt stress sweep: correlate switching edges with peak error, invalid-sample flags, or error counters.
• Observe minimum nodes: input pins, both-side ground reference, data line, and recovery time after steps.
• Classify outcome: reading step vs bitstream glitch vs CRC/framing error (each has different owners).

• Clock/sync: clock source, sharing strategy, and coherency across channels.
• Decimation: filter group delay defines when data becomes valid.
• System alignment: triggers/time-stamps and channel-to-channel skew control.

• Budget latency as: modulator + transport + decimation, and design to “time-to-accuracy”, not update rate.
• Choose sync strategy (shared clock vs independent clocks) based on channel coherency requirements.
• Use deterministic resync/relock behavior when framing is stressed by dv/dt.

• Step input → measure time to reach the specified error band (true time-to-accuracy).
• Multi-channel event injection → measure channel-to-channel skew and repeatability.
• Under dv/dt stress, verify that any resync is bounded and deterministic.

• dv/dt waveform, edge rate, repetition, polarity, and coupling setup define the result.
• Pass/fail differs by output type: analog outputs care about peak error + recovery time; digital/bitstream care about integrity events.
• Supply and layout are part of the system-level CMTI outcome (device-level numbers do not include board return paths).

• Analog path: transient peak error ≤ target and recovery time ≤ target under the defined dv/dt event.
• Bitstream/digital path: no framing loss, bounded resync, and error counters ≤ target during switching edges.

1. HV switching node dv/dt → barrier parasitics generate displacement current.
2. Current couples into: input wiring, input protection network, receiver ground, or data lines.
3. The return path determines the symptom class and the correct fix.

• Likely cause: analog stage overload or reference disturbance by ground bounce.
• First checks: input pin overdrive, clamp conduction, recovery time after common-mode steps.
• Design levers: RC placement + intentional return path that avoids the measurement reference node.

• Likely cause: receiver threshold hit by short glitches synchronized to dv/dt events.
• First checks: bitstream line pulses, clock alignment with switching edges, invalid-sample flags.
• Design levers: receiver deglitching + sampling windows that avoid the dirtiest edge intervals.

• Likely cause: data-line common-mode disturbance + ground bounce at the receiver.
• First checks: error counters vs switching frequency, supply dips at the isolator/receiver, resync behavior.
• Design levers: shorter return loop, stronger local decoupling, deterministic resync/timeout strategy.

• Clock sets the modulator rate.
• OSR trades bandwidth for noise shaping and stability margin.
• Decimation filter defines the output sample rate and the passband shape.
• Transport/sync adds fixed delay and sometimes delay variation.

• Simple and common, strong notch-like behavior around multiples of the output rate.
• Higher order improves attenuation but increases group delay and transient “tail”.
• Best used with a clear bandwidth window and a known settling requirement.

• Often flatter passband and stronger stopband control.
• Latency is defined by tap length and buffering; verify determinism.
• Prefer when the application needs predictable passband shape and bounded recovery behavior.

• Modulator delay: internal state memory before the stream reflects an input change.
• Filter delay: group delay from decimation, usually the dominant term.
• Transport/sync delay: isolation transfer, framing, and channel alignment.

• Use maximum temperature leakage for clamps/ESD/TVS and any PCB surface leakage paths.
• Map leakage current through source/bias impedance into an equivalent input offset.
• Verify stability: if leakage changes with humidity/contamination, treat it as a layout/process owner.

• Injection points: bus ripple, switching nodes, dv/dt and di/dt ground bounce.
• Risk: measurement reference rides on a noisy domain unless the return path is controlled.
• Use when: HV domain already provides a clean, regulated rail close to the sensing front-end.

• Injection points: isolated DC-DC switching edges and its high-frequency return loop.
• Risk: displacement current across the barrier couples into reference nodes if routing is careless.
• Use when: measurement rails must be controlled and repeatable across platforms and lots.

• Framing: define how a receiver finds boundaries after a disturbance.
• CRC: proves an error happened; a system still needs a response strategy.
• Bounded resync: recovery time must have a known maximum for safe control behavior.

• Settling depends on: output drive stability, AAF placement, and recovery from barrier-coupled transients.
• Verification target: ADC input reaches the error band within the required time window.
• Common failure: a clean-looking analog chain becomes “not clean” due to ground bounce and return paths.

• Effective bandwidth and group delay define “usable data”.
• Verification target: time-to-accuracy for step events under switching and common-mode stress.
• Common failure: correct average value but slow recovery tail makes control and logging wrong during events.

• Reduces HV-domain edge energy before isolation transfer.
• Settling ownership shifts toward: sensor wiring, protection network, and HV reference stability.
• Risk: RC and clamps can dominate step response and cause long recovery tails.

• Better control of ADC-facing settling and anti-alias behavior.
• Settling ownership shifts toward: LV conversion, decimation, and recovery logic.
• Risk: barrier-coupled glitches must be detected and bounded (invalid/hold/resync).

• 0.1–10 Hz: use long capture windows and remove slow trend before peak-to-peak statistics.
• Wideband: define measurement bandwidth and sampling conditions consistently.
• Always state: time window, bandwidth, and any digital filtering applied.

• Protection order is explicit: Connector → Rseries → RC → Clamp → INA/Mod inputs.
• Leakage budget is written as fields (not assumptions): I(leak,max,T) × R(source,max) → V(error).
• High-impedance sources have a defined bias return path (no “floating CM” behavior).
• Clamp path is current-limited so CM transients do not drive the front-end into long saturation.

• Isolated DC-DC hot loops are small, closed, and routed away from input and reference nodes.
• “Measurement reference” and “safety reference” are not unintentionally tied by routing or copper pours.
• Barrier displacement current (Cpar) has a planned return path (treated like a routed signal).
• Probe points are designed in (input node, HV-GND, LV-GND, data/clock nodes).

• Barrier boundary is physically obvious on the PCB (keep-out, split, and label discipline).
• Creepage/clearance constraints are preserved by placement and routing (no last-minute via shortcuts).
• Fast-switching nets stay away from barrier edges; reference nodes stay inside protected regions.
• Failure modes are listed: clamp short/open, DC-DC noise rise, isolator upset, sensor open/short.

• Clock domain strategy is defined (shared vs independent) and startup behavior is deterministic.
• Digital path has bounded recovery: invalid flag → hold last good → resync within a maximum time.
• Multi-channel alignment method is declared (shared clock / sync pin / timestamp boundary).
• Production counters are planned: CRC errors, timeouts, resync count, invalid sample percentage.

• CMTI / dv/dt: record stimulus, HV-GND, LV-GND, and data output in the same capture.
• Overload recovery: differential step + CM step; report peak error and time-to-accuracy.
• Temperature sweep: separate drift from leakage (shorted input vs normal input control runs).
• Bit errors: CRC/timeout/resync statistics under switching frequency and load sweeps.
• Transient windows: verify whether sampling must avoid switching edges (and log the rule).
• Long-term drift: warm-up/soak is defined by a stability threshold, not a fixed time guess.

• Isolation grade: basic / reinforced (vendor term).
• Working voltage and transient envelope (state the intended domain).
• Package creepage/clearance and board-level margin plan.
• Barrier coupling note: Cpar return path is planned (yes/no).

• Output type: analog / bitstream / framed digital.
• Clocking: internal/external, allowed range, startup determinism.
• Sync method: shared clock / sync pin / timestamp boundary.
• Diagnostics: invalid/overrange/CRC/resync visibility.

• Offset / drift; gain error / gain drift (conditions required).
• 0.1–10 Hz noise p-p (window + processing definition required).
• Wideband noise (state bandwidth and any filtering).
• Input bias/leakage impact: worst-case temperature and board leakage assumptions.

• CMTI (must include test waveform and pass/fail criterion).
• CM step behavior: peak error + recovery time; error flags during event.
• Overload recovery: amplitude and “time-to-accuracy” definition.
• Latency: group delay vs update delay; include transport/sync or not (define it).

• Priority: CMTI test conditions, CM step recovery, glitch/CRC/invalid handling, return path discipline.
• Typical symptom: spikes, bitstream glitches, CRC bursts, or short jumps correlated with switching edges.
• Ownership focus: barrier coupling + layout + receiver thresholds + bounded resync behavior.

• Priority: drift, 0.1–10 Hz noise definition, leakage budgeting, input bias return path.
• Typical symptom: slow offset drift after protection changes or humidity/temperature changes.
• Ownership focus: protection leakage + board cleanliness + reference stability + warm-up stability threshold.

• Priority: latency definition, time-to-accuracy under steps, overload recovery, sync determinism.
• Typical symptom: correct steady-state value but wrong behavior during events due to slow recovery tails.
• Ownership focus: decimation/filter delay + transport/sync delay + bounded invalid sample policy.

• TI AMC1301 / AMC1302 / AMC1300 (reinforced isolated amplifiers; current/voltage sensing variants).
• TI AMC1311 (reinforced isolated amplifier family; input-range variants).
• TI AMC3301 / AMC3302 (isolated amplifiers; variants include integrated isolated power options in some families).
• Broadcom ACPL-7970 (isolated amplifier family used in power electronics sensing).
• Silicon Labs Si8920 / Si8921 (isolated amplifier family for current/voltage sensing use cases).

• Analog Devices AD7401A (isolated ΣΔ modulator; 1-bit data stream).
• Analog Devices ADuM7701 / ADuM7702 (isolated ΣΔ modulator family; bitstream output).
• TI AMC1306M05 / AMC1304M25 / AMC1305M25 (isolated modulator families; bitstream + decimation use cases).
• Broadcom ACPL-C79B (isolated modulator family used in motor drives and inverters).

• Analog Devices ADuM7703 (isolated ΣΔ ADC family positioning; check latency and output framing details).