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Input Bias & Input-Referred Noise for INAs

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Stable readings come from designing around two dominant chains: bias/leakage × source impedance (mean drift) and input-referred noise × bandwidth/window (jitter). This page shows how to model, measure, and set pass criteria so high-Rs sensors and real wiring stay accurate in the field.

Definition & Boundary: Input Bias Current vs Input-Referred Noise

Stable INA readings are governed by two separable chains: a bias/leakage (DC & slow) chain that creates offset and drift, and a noise (random) chain that creates RMS jitter and limits resolution. This page stays inside those two chains and treats source impedance (Requiv) and effective bandwidth (BWeff) as the only “multipliers” that turn tiny currents and densities into visible errors.

Minimal vocabulary (only what is needed for engineering decisions)
  • Input bias current (Ib): average input current required by the input stage. Direction matters (into vs out of the pin) because it sets the sign of the error through resistances.
  • Input offset current (Ios): mismatch between the two input bias currents. Even with perfectly matched wiring, Ios behaves like a differential error source.
  • Input-referred noise: modeled as en (V/√Hz) and in (A/√Hz). At high source impedance, in·R becomes dominant; at low source impedance, en dominates.
  • Leakage: unintended current paths from PCB surface films, connectors/cables, input protection parts (ESD/TVS/clamps), and flux residues. In high-R designs, leakage often exceeds “typical Ib”.
  • Requiv (effective source resistance seen by each input): not only the sensor’s Rs. It also includes series protection resistors, input RC networks, and any parallel leakage paths that shift the input node bias.
  • BWeff (effective noise bandwidth): set by the analog front-end + sampling/decimation + any digital averaging window. BWeff is the conversion between density (V/√Hz) and RMS jitter (Vrms).
Two-chain model (use this to decide “what to change first”)
A) Bias / leakage chain (DC & slow)

Bias/leakage currents flowing through Requiv create a differential error voltage: Verr ≈ I × Requiv. This appears as offset, drift, humidity sensitivity, or “touch/move the cable → reading changes”.

B) Noise chain (random)

Input-referred noise densities become RMS output jitter once integrated over BWeff. Source impedance sets which term dominates: en vs in·Requiv. This appears as reading jitter, “averaging does not converge fast enough”, or “resolution is lower than expected”.

Boundary guardrails (to prevent sideways expansion)
  • Noise theory and 0.1–10 Hz interpretation are not derived here (only decision-ready usage).
  • CMRR/PSRR mechanisms are not explained here (only bias/leakage artifacts that can look like “CMRR problems”).
  • System-level EMI hardening and ADC drive/anti-alias details are not expanded here (only how they change Requiv and BWeff).
Bias and noise error paths for an INA front-end Block diagram showing sensor source impedance and leakage paths feeding an instrumentation amplifier, separating bias/leakage chain and noise chain into different observable symptoms. Sensor R equiv Wiring Leakage INA Ib en/in Observable outcomes Offset / Drift RMS Jitter Touch-sensitive
Use the diagram to classify problems first: if errors scale with Requiv and environment (humidity/handling), bias/leakage dominates; if errors scale with BWeff and averaging length, noise dominates.

Why “Tiny” Bias Current Creates Big Real Errors

“pA/nA” looks harmless until it is multiplied by Requiv and distorted by real-world leakage. Many field failures are not caused by the INA core, but by added resistors, protection parts, connectors, and PCB surface films that silently push Requiv higher and introduce temperature/humidity dependence.

The error multipliers (ranked by how often they dominate in practice)
1) High effective impedance (Requiv)

Sensor resistance, series protection resistors, input RC networks, and any “safety” resistors all add into Requiv. Bias/leakage errors scale approximately linearly with Requiv: Verr ∝ Requiv.

2) Leakage that is not in the datasheet

PCB surface films (humidity + residues), connector insulation, cable dielectric absorption, and protection-part leakage can create input currents far above “typical Ib”. Leakage also varies strongly with temperature and humidity, which turns a clean DC error into drift.

3) Input protection parts acting like current sources

ESD diodes, TVS, clamps, and series resistors create voltage-dependent and temperature-dependent leakage. Even when protection is required, the architecture must preserve a predictable DC path and keep leakage away from the measurement node (layout + guarding + part choice).

4) Environmental coupling that looks like “electronics”

“Touch the cable → reading changes” is often a leakage/insulation issue, not a gain or CMRR issue. Motion changes capacitance and surface charge; humidity changes insulation; both modulate leakage and bias currents through Requiv.

Common illusions (what it looks like vs what it usually is)
  • Looks like CMRR collapsed → often a differential leakage path or Ios interacting with unequal Requiv on the two inputs.
  • Looks like “offset drift” → often temperature/humidity dependence of protection leakage or PCB surface films, not the INA’s intrinsic offset drift.
  • Looks like “noise” → often slow bias drift plus an averaging window that is too short to reveal the slow component (the mean moves during the average).
Fast triage (what to change first, without hiding the root cause)
  1. Quantify leakage sensitivity: compare dry/clean vs humid/handled conditions; if the mean shifts, leakage/bias dominates.
  2. Check scaling with Requiv: add or remove a known series R; a proportional change strongly indicates bias/leakage conversion.
  3. Only after DC paths are controlled, tune BWeff and averaging to hit the jitter target; otherwise filtering can mask drift and create false confidence.
Bias current multiplied by effective resistance: decade ruler A decade scale showing how increasing effective source resistance increases sensitivity to bias and leakage, with practical risk zones. Bias/Leakage sensitivity rises by decades with R equiv 10k 100k 1M 100M Mostly OK Bias visible Leakage dominates Key scaling: Verror ≈ I × Requiv
Treat Requiv as a design variable. Input protection and RC filters often increase Requiv and introduce leakage paths, turning “tiny” currents into large and environment-dependent errors.

Error Model: How Ib/Ios Convert into Offset and Drift

A practical INA error model treats the input pins as current-driven nodes (bias + leakage) sitting on top of a real impedance network (sensor Rs, series protection, RC filters, and clamp leakage). The measured error is not “mystical drift”; it is the predictable result of currents flowing through effective resistance and of voltage- and environment-dependent leakage paths.

Step 1 — Build the “node model” (what currents exist at each input)
  • Ib+, Ib−: input bias currents (direction matters; sign sets whether the node is pulled up or down through R paths).
  • Ios: mismatch component (Ios = Ib+ − Ib−), directly creates differential error even with matched wiring.
  • Ileak+, Ileak−: leakage currents from PCB surface, connectors/cables, input clamps/ESD/TVS, and flux residues (often temperature/humidity dependent).
Step 2 — Convert current to voltage through Requiv (where the error actually appears)

Each input node sees an effective impedance made of sensor resistance (Rs), series protection resistors (Rser), and any RC/filter network. Currents at that node create a node-voltage shift: Vnode ≈ Inode × Requiv. The INA measures the difference between the two nodes, so any imbalance between the two sides becomes a differential offset.

A) Rs mismatch turns “common” bias into differential error

When Rs+ and Rs− are not equal, the same bias/leakage current creates different voltage drops on the two inputs. The measured offset then tracks wiring changes that modify the two sides differently (lead resistance, connector contact, contamination).

B) Clamps and protection make leakage voltage-dependent (nonlinearity)

Clamp diodes/TVS/ESD structures often have leakage that changes with input voltage. As the common-mode or differential input moves, leakage changes, and the error becomes range-dependent (worse near certain voltages).

Step 3 — Classify what is being seen: offset vs drift vs nonlinearity
Static offset

Repeatable mean error under stable temperature/humidity and unchanged wiring. Typically dominated by steady Ib/Ios through a fixed Requiv.

Environmental drift

Mean shifts with humidity, contamination, handling, airflow, or temperature ramps. Usually dominated by leakage paths and by temperature-dependent clamp currents.

Range-dependent error (nonlinearity)

Error changes when the input common-mode or differential level is swept. Often indicates voltage-dependent leakage (clamps/ESD/TVS) or a bias path that changes state across a voltage boundary.

Boundary note: this model explains current-to-voltage conversion through external impedances. Frequency-domain CMRR behavior and full accuracy budgeting are handled in their dedicated pages.

Differential node model for bias and leakage error conversion An equivalent differential circuit showing Rs, series protection resistors, leakage to ground, clamp leakage, and input bias currents producing offset, drift, and range-dependent error. Sensor IN+ IN− Rs+ Rs− Rser+ Rser− R leak+ R leak− GND Clamp Ib+ Ib− mismatch → Ios INA What shows up offset drift nonlinear
Model the input pins as nodes: bias/leakage currents flow through Rs + Rser and through leakage paths (Rleak, clamp leakage), producing differential offset, environment-driven drift, and voltage-range-dependent nonlinearity.

Source Impedance Matching: When Rs Dominates Everything

Source impedance determines which term dominates: voltage noise (en), current noise (in·R), or bias/leakage conversion (I·R). The correct first move is different in each Rs regime, so this section uses a zone model that maps dominant term → design focus → quick check. This stays inside the Ib/noise boundary and does not explain frequency-domain CMRR mechanisms.

Zone logic (use Requiv, not just the sensor’s Rs)

Treat Requiv as the actual zone input. Protection resistors and input RC networks can push Requiv far above the sensor’s nominal Rs, and leakage paths can effectively create unequal Requiv on the two inputs.

Low-R (Ω–kΩ)
  • Dominant term: en and bandwidth/settling effects typically dominate; in·R is small.
  • Design focus: avoid unnecessary series R; manage BWeff and any RC that changes settling or noise bandwidth.
  • Quick check: change BW/averaging; RMS jitter should scale with BWeff if noise dominates.
Mid-R (kΩ–100 kΩ)
  • Dominant term: bias/leakage conversion (I·R) becomes visible; in·R may start to rise.
  • Design focus: match Rs on both inputs; place series R and RC symmetrically; control leakage near the input nodes.
  • Quick check: add a known series R equally; mean offset scaling with R strongly indicates bias/leakage conversion.
High-R (>100 kΩ to GΩ)
  • Dominant term: leakage and surface contamination dominate; “typical Ib” is often not the limiting current.
  • Design focus: guarding, cleaning, materials, and protection leakage specifications; minimize exposed high-impedance surfaces.
  • Quick check: humidity/cleanliness A/B test; if mean shifts with environment, leakage dominates.
Rs regime decision bar: dominant term, focus, and quick check A three-zone bar chart for low, mid, and high source impedance showing dominant error term and recommended focus actions: bandwidth control, matching Rs, and guarding/cleaning. Rs / Requiv zones → dominant term → first action Low-R Ω–kΩ Dominant: en/BW Focus: limit BW Check: change BW Mid-R kΩ–100k Dominant: Ib×R Focus: match Rs Check: add Rser High-R >100k–GΩ Dominant: leakage Focus: guard/clean Check: humidity A/B Use: dominant term → first fix → quick validation
Apply the zone model using Requiv (sensor Rs plus series protection and RC). The dominant term determines the fastest safe fix: bandwidth control (low-R), matching and symmetry (mid-R), or guarding/cleanliness and leakage control (high-R).

Leakage Paths in the Real World: PCB, Connectors, Protection Parts

In high-impedance front-ends, leakage is an unintended DC current path from the input node to nearby conductors (planes, rails, shields, chassis). Because the input node typically sits on a large effective resistance, even tiny leakage currents can shift the mean reading and create humidity/handling sensitivity. The fastest way to stabilize measurements is to identify the path, then remove it, move it, or guard it.

What “leakage” means (engineering definition)
  • Surface conduction: contamination + humidity forms a conductive film across solder mask, flux residues, and exposed pads.
  • Component leakage: TVS/ESD/clamps, analog switches/MUXes, and protection networks introduce temperature- and voltage-dependent leakage.
  • Connector/cable insulation: absorption, dirt, and aging reduce insulation resistance; shield and shell provide convenient return nodes.
The three dominant leakage families (and the practical fix direction)
A) PCB surface leakage

High-impedance nodes near exposed solder mask openings and residues are sensitive to moisture. Fix direction: keepout + guard + cleanliness to prevent a surface film from bridging input copper to nearby planes.

B) Protection-part leakage

TVS/ESD/clamps and some MUX/switch inputs can leak in a way that depends on temperature and input voltage. Fix direction: keep the highest-leakage parts away from the measurement node, and keep symmetry between IN+ and IN−.

C) Connector & cable insulation

Cable/connector insulation resistance can drop with humidity and contamination. Shield/shell often becomes a “hidden return”. Fix direction: define shield/shell strategy and isolate the high-Z node with guarded routing and controlled reference.

Practical isolation strategy (ranked by impact)
  1. Reduce leakage sources: clean residues, minimize exposed high-Z copper, avoid hygroscopic materials near the input node.
  2. Move the return: keep planes/rails/chassis away from the input pad neighborhood; keep high-Z traces short and separated.
  3. Guard the node: surround the input node with a guard conductor at similar potential to suppress surface currents.
  4. Make it symmetric: match protection networks and routing on IN+ and IN− to prevent differential conversion from unequal leakage.
Fast diagnostics (short A/B tests)
  • Humidity A/B: dry vs humid conditions; mean shift indicates leakage dominance.
  • Clean/No-clean A/B: cleaning or bake-out changes mean/drift slope; surface film is dominant.
  • Guard A/B: enabling a guard ring reduces touch sensitivity; confirms surface leakage path.

Boundary note: this section focuses on DC/low-frequency leakage paths that move the mean reading; EMI/RFI hardening and IEC surge design are handled elsewhere.

Leakage path heatmap from input pads to planes, rails, and chassis A block heatmap diagram showing leakage routes from the input pad area across PCB surface films to adjacent copper, then to ground, supply rails, and connector shell/shield. Input pads IN+ IN− Surface film Adjacent copper Plane / trace Keepout Return nodes GND Vrail Case Connector & cable Connector Shield Shell / Case Guard
Leakage is a path problem. Trace the route from input pads across surface films to adjacent copper, then to GND/rails/case. Add keepouts and guard conductors around the high-Z node, and define shield/shell strategy to prevent the cable hardware from becoming a hidden return.

Datasheet Traps: Ib vs Common-Mode, Temperature, Input Voltage

Input bias current is not a single number; it is a condition-dependent function. Many “typ looks great, worst-case fails” situations come from missing the test conditions: temperature, input common-mode, differential level, supply headroom, input voltage proximity to rails, and operating mode. Reliable designs use max over temperature plus a condition matrix to map bias current into the system’s Requiv and leakage budget.

A safe reading order (prevents “typ-only” selection)
  1. Start with max specs over the target temperature range (not typical).
  2. Locate test conditions: Vcm, Vdiff, Vsupply, and whether inputs are near rails.
  3. Use curves if available: Ib vs temperature and Ib vs Vcm show regime changes.
  4. Check mode interactions: chopper/auto-zero and protection structures can change effective input current behavior.
Condition dimensions that frequently move Ib/Ios
Temperature

Bias and leakage currents often increase strongly with temperature; worst-case drift must be evaluated at the temperature extremes and during ramps.

Common-mode (Vcm)

Input stage operating points shift with common-mode; Ib magnitude and direction can change across the valid Vcm range.

Input voltage proximity (near rails)

Near-rail conditions and protection structures can introduce voltage-dependent leakage; errors may become range-dependent even if the mid-range looks fine.

Supply headroom

Single-supply vs dual-supply and headroom constraints can move input stage behavior, changing effective bias current and clamp interaction.

Operating mode

Chopper/auto-zero may deliver excellent DC offset performance, but input switching behavior and protection networks can introduce secondary effects that must be validated under system conditions.

Selection logic: match Ib/Ios behavior to Requiv and leakage risk
  • Low Requiv: Ib conversion is often small; prioritize bandwidth/settling and en behavior.
  • Mid Requiv: Ib/Ios conversion becomes visible; check Ib vs Vcm and over temperature, and keep protection symmetry.
  • High Requiv: system leakage typically dominates; enforce guarding and verify with humidity/cleanliness A/B tests.

Boundary note: this section teaches how to read bias-current conditions; detailed architecture noise mechanisms and frequency-domain CMRR are covered in their dedicated pages.

Datasheet condition matrix for input bias current A two-card matrix diagram listing datasheet test-condition dimensions that affect Ib/Ios, mapped to system variables Requiv and leakage risk. Test conditions Temperature (T) Common-mode (Vcm) Differential (Vdiff) Supply (Vs) Mode / Protection Ib / Ios changes Magnitude shifts Direction can flip Range-dependent Map to R equiv + leakage risk Rule: use max + conditions, not typical alone
Treat Ib/Ios as a condition-dependent behavior. Extract the datasheet’s test dimensions (T, Vcm, Vdiff, Vs, mode/protection) and map them to Requiv and leakage risk to avoid “typ-only” selection failures.

Input-Referred Noise Fundamentals (en, in, 1/f, chopper artifacts)

Input-referred noise is best handled as a set of components that are later combined with source impedance and bandwidth. This section defines the practical meaning of en (voltage noise density), in (current noise density), the 1/f region, and chopper artifacts so the next section can map them into a system decision.

Noise dictionary (what each term “means” at the input pins)
  • en (V/√Hz): an input-referred voltage noise density that tends to dominate when the source impedance is low.
  • in (A/√Hz): an input-referred current noise density that turns into voltage noise through source impedance (later treated as in×R).
  • 1/f region: low-frequency rise where “longer averaging” may not produce proportional improvement in stability.
  • Chopper artifacts: switching-related ripple/spurs that can appear as visible ripple or become a mixing/alias risk in sampled systems.
Dominance map (when each component typically matters)
Low source impedance

en and bandwidth are often the first-order limit; in×R is typically small. Noise improves when bandwidth is reduced or averaging is increased (within dynamic requirements).

High source impedance

in×R becomes significant and may dominate. High-impedance inputs also become more sensitive to leakage paths, which can look like drift rather than random noise.

Low-frequency / slow measurements

The 1/f region can limit the stability of long averaging windows. Improvement may saturate if the noise rises toward DC or if the system adds leakage-driven drift.

Chopper/auto-zero behavior

DC offset can be excellent while switching artifacts create visible ripple or sampled-system interaction. Treat these as deterministic components that require filtering and validation.

Practical guardrails (what to verify before optimizing)
  • Noise vs bandwidth: random noise should generally scale with the effective bandwidth and averaging strategy.
  • Noise vs source impedance: if noise increases strongly with added series resistance, in×R is likely involved.
  • Ripple vs noise: a stable periodic pattern indicates artifacts/spurs; it should not be treated as random noise.

Boundary note: this section defines noise components for design decisions; detailed low-frequency 0.1–10 Hz noise budgeting is handled in the dedicated low-frequency noise page.

Noise density components: en platform, 1/f rise, and chopper spur A conceptual noise density plot showing a flat en region, a low-frequency 1/f rise, and a chopper-related spur, with labels and a bandwidth integration hint. Frequency Noise density en 1/f chopper spur Integrate BW en 1/f chopper spur Design uses BW + Rs
Noise density is component-based: a wideband en platform, a low-frequency 1/f rise, and possible deterministic chopper spurs. Total RMS depends on the effective bandwidth and how the density maps through source impedance.

Noise vs Source Impedance: The Rs Crossover You Must Design Around

The key design question is which term dominates at the input node: en or in×R. The crossover depends on the effective source impedance at the INA pins, not just the sensor’s nominal resistance. Once the dominant density is identified, bandwidth and averaging determine the total RMS. This section provides the decision framework without requiring precise numeric curves.

Step 1 — Use Requiv at the INA pins (not “sensor Rs” only)
  • Include sensor resistance, lead resistance, and any series protection resistor.
  • Keep IN+ and IN− symmetry; mismatch turns common behavior into differential error.
  • Remember that adding input RC/protection can push Requiv into a different dominance zone.
Step 2 — Compare en to in×Requiv

Treat in as a current that becomes voltage through the node impedance. If in×Requiv exceeds en, high-impedance sources are penalized and the design should reduce Requiv or use a lower-current-noise input type.

en-dominated region

Lower Requiv pushes the system toward en dominance; bandwidth control and low en selection become the primary levers.

in×R-dominated region

Higher Requiv amplifies current noise; reducing series resistance and managing leakage/guarding can improve both noise and stability.

Step 3 — Bandwidth multiplies the result (choose BWeff intentionally)
  • Once the dominant density is known, total RMS depends on the effective bandwidth and averaging.
  • Analog filtering controls what reaches the ADC; digital filtering controls reported noise and response time.
  • Do not reduce bandwidth below dynamic requirements; validate step response and settling.
Step 4 — Hidden penalty: RC/protection pushes Requiv up
  • Series protection resistors increase Requiv and can move the design into the in×R-dominated region.
  • Higher Requiv also increases sensitivity to bias and leakage conversion, which may look like drift.
  • Use symmetry and guarding so protection does not become the dominant error source.
Decision outputs (fast)
  • in×R dominates: reduce Requiv, choose lower in input, tighten leakage control.
  • en dominates: reduce BWeff or choose lower en, while meeting settling and stability needs.
  • Low-frequency rise dominates: adjust measurement window/averaging strategy and validate stability across time.

Boundary note: this section provides the Rs crossover decision framework; detailed filter design and 0.1–10 Hz noise budgeting are covered in their dedicated pages.

Conceptual crossover: en vs in×Rs and the effect of Rser A trend plot of equivalent input noise versus source impedance, with a flat en line and a rising in×Rs line, showing a crossover point and a note that adding series resistance shifts the effective impedance. Rs / R equiv Eq. input noise en in×Rs Crossover en-dominated in×R-dominated Rser R_equiv increases crossover shifts leakage risk
The crossover is where in×Requiv becomes comparable to en. Adding series protection (Rser) increases Requiv and can shift the design into the current-noise-dominated region, increasing both noise and sensitivity to leakage and bias conversion.

From Noise Density to Real Resolution: Bandwidth, Filtering, Sampling Window

Noise density (V/√Hz or A/√Hz) becomes a real output number only after the system defines an effective bandwidth and a sampling window. In practice, analog filtering, digital filtering/averaging, and the output update window jointly determine how much noise energy is reported as jitter (σ), peak-to-peak variation, and usable resolution.

A) Define BWeff (effective bandwidth)
  • Analog filtering limits what reaches the sampler/ADC and reduces out-of-band energy that can fold into the passband.
  • Sampling window (Twin) and update rate define how much data contributes to each reported output value.
  • Digital filtering/averaging reshapes the passband and trades noise reduction for response time and correlation between outputs.

Practical rule: BWeff is a system property, not a single cutoff frequency number.

B) Use σ and p-p correctly (no theory, only engineering usage)
σ (RMS jitter)

Best for budgeting and comparing settings because it is less sensitive to record length. Use σ to translate noise into repeatability and resolution.

p-p (peak-to-peak)

Matches user experience and alarm threshold concerns, but depends strongly on record length and bandwidth. Always report the time window and filtering used.

Comparison rule: p-p values are only comparable when BWeff and record length are the same.

C) “Stable reading” criteria (template for acceptance)
  • Lock BWeff, update rate, and the sampling window definition.
  • Apply a fixed averaging policy (N samples or Twin window) and compute output σ.
  • Pass when σ reaches the target and the mean does not drift beyond the allowed slope over the specified observation period.

Debug rule: if mean shifts with touch/humidity, leakage dominates and more averaging will not create true stability.

Common failure modes (when numbers look “good” but readings are not stable)
  • Correlated outputs: heavy digital filtering reduces σ but increases lag; adjacent updates are not independent.
  • Low-frequency rise: longer windows saturate improvement when 1/f and drift-like effects dominate.
  • Spurs/ripple: periodic artifacts are not random noise; averaging can reveal patterns rather than remove them.
  • Measurement setup: probes/fixtures can change bandwidth and leakage, making results non-repeatable.

Boundary note: this section maps density to stability via BWeff and windowing; detailed filter topology design and low-frequency noise budgeting are handled in dedicated pages.

Noise chain: analog bandwidth to digital averaging to output jitter with pass criteria A block diagram showing noise density feeding an analog bandwidth block, then a sampling window and digital averaging, producing output jitter metrics sigma and peak-to-peak and a pass criteria placeholder. Noise density en 1/f spur Analog BW BW Window T_win Digital Average Output σ (RMS) p-p Resolution / Stability Pass criteria BW_eff = ___ N / T_win = ___ σ ≤ ___ p-p ≤ ___
A stable reading is defined by a locked BWeff and a fixed window/averaging policy. Analog bandwidth limits what enters the sampling chain, digital filtering shapes the reported noise, and acceptance must be written as explicit pass criteria (BW, window, σ, p-p, record length).

Measurement & Debug Playbook: How to Separate Ib, Leakage, and Noise

Field failures often look similar: drift, touch sensitivity, or “too much noise”. The fastest path to a fix is to separate the problem into three buckets: bias conversion (Ib-related mean error), leakage paths (environment- and layout-dependent mean shift), and random noise (σ that follows bandwidth and window settings). This section provides low-cost A/B experiments and signatures that do not require specialized instruments.

Quick signature table (what moves: mean vs σ vs p-p)
  • Ib-driven: mean shifts with Requiv in a repeatable way; humidity/touch has weak impact when the board is clean and guarded.
  • Leakage-driven: mean/drift changes strongly with humidity, cleaning, touching, or guard enable; symptoms can look like “drift” more than random noise.
  • Noise-driven: σ responds predictably to bandwidth and averaging; mean is comparatively stable across environment changes.
A) Bias (Ib) experiments
  1. R sweep: switch between known effective resistances and measure mean shift. A stable slope indicates bias conversion through Requiv.
  2. Short vs open: short inputs to a defined potential for baseline; open inputs reveal whether the node is floating and susceptible to leakage-dominated behavior.
  3. Rs compare: keep BWeff fixed and compare outputs across different Rs; mean tracking with Rs suggests Ib/leakage involvement.
B) Leakage experiments
  1. Humidity A/B: compare dry vs humid conditions; large mean shift indicates leakage dominance.
  2. Clean / bake A/B: cleaning or bake-out that changes mean/drift strongly implicates surface films and residues.
  3. Guard on/off: enabling guard should reduce touch sensitivity and humidity sensitivity if surface leakage is the driver.
  4. Path change: temporarily isolate suspected regions (keepouts, nearby copper, connector shell) to identify the return node.
C) Noise experiments
  1. Short-input baseline: establish σ floor and look for periodic patterns that indicate spurs/ripple.
  2. Bandwidth sweep: change analog/digital filtering and verify σ follows BWeff and window policy as expected.
  3. Rs sweep: with BW fixed, evaluate σ vs Rs trend to distinguish en dominance from in×R dominance.
Setup warnings
  • Probes/fixtures can add leakage to high-impedance nodes.
  • Cable motion can change shield return paths and create “false leakage” signatures.
  • p-p requires a fixed record length; otherwise it is not comparable across runs.

Boundary note: this playbook separates bias, leakage, and random noise; compliance-level EMI/ESD qualification is handled in the protection pages.

Bench setup for separating bias, leakage, and noise A bench setup block diagram with a DUT, switchable resistors, guard control, environment controls, and a logger capturing mean, sigma, and drift slope, plus a probe leakage warning. DUT INA front-end IN+ IN− Switch Rs R1 R2 R3 Guard on/off Environment Humidity Clean Bake Logger Mean σ Drift slope Probe Leakage risk
A controlled bench setup separates mean error (bias conversion), environment/path sensitivity (leakage), and random jitter (σ). Switch Req, toggle guard, change humidity/clean/bake conditions, and log mean, σ, and drift slope with fixed BW and window definitions.

Engineering Checklist (Design Review + Bench Tests + Pass Criteria)

This checklist turns bias conversion, leakage sensitivity, and noise stability into a reviewable design package and a repeatable bench validation plan. Each item is written as a testable field so production and debugging can converge on the same criteria.

A) Design review (layout + guard + cleanliness + protection)
Input symmetry

Keep IN+ and IN− environments matched (routing, adjacency, copper proximity) so leakage and series resistance do not convert into differential error.

Field
IN+/IN− match notes: ____
Guard strategy

Guard high-impedance nodes and sensitive surfaces to control humidity/touch sensitivity and to keep leakage paths from dominating mean error.

Field
Guarded nodes: ____
Cleanliness control

Define the cleaning and bake-out process as part of the electrical spec, because surface films can create leakage-driven drift and touch sensitivity.

Field
Clean / bake condition: ____
Protection leakage

Treat clamps/TVS/ESD networks as part of the bias/leakage model; their leakage can vary with temperature and node voltage and become an “effective bias” path.

Field
Protection parts list: ____
Series resistor placement

Place and size Rser to avoid pushing Requiv into a worse noise/bias region; keep symmetry so Rser does not create differential conversion.

Field
Rser location + value: ____
B) Bench tests (repeatable A/B experiments)
Rs sweep

Switch Req (R1/R2/R3) with fixed BWeff and window policy; log mean and σ trends to identify bias conversion and in×R effects.

Humidity A/B

Compare dry vs humid conditions; large mean shift or drift slope change indicates leakage dominance.

Short / open

Short inputs to establish a baseline; open inputs reveal floating-node behavior and leakage sensitivity that can look like drift.

Touch sensitivity

Use a repeatable touch/move action on cable/connector; log mean step and recovery time to distinguish leakage paths from random jitter.

Drift slope

Measure drift slope after a defined soak; avoid mixing warm-up transients into drift acceptance.

Mandatory test conditions (fields)
BW_eff setting: ____
Window / averaging: ____
Record length: ____
Environment (dry/humid/clean/bake): ____
C) Pass criteria template (quantified fields)
Noise stability
σ_out ≤ ____ (BW_eff + window fixed)
p-p_out ≤ ____ (record length fixed)
Mean stability / drift
Drift slope ≤ ____ (after soak)
Mean shift (humidity A/B) ≤ ____
Handling sensitivity
Touch-induced step ≤ ____
Recovery time ≤ ____

Acceptance must always include BW_eff, window policy, record length, and environment condition so results remain comparable across benches and production.

Engineering checklist map: design review to bench tests to pass criteria A card-style flow diagram with three rows: design review items, bench test items, and pass criteria fields, connected by arrows for a production-ready validation flow. Design review Bench tests Pass criteria Symmetry Guard Clean Protection Rs sweep Humidity Short/open Touch / drift σ / p-p Drift Touch
A production-ready flow links design decisions (symmetry, guard, cleanliness, protection leakage) to repeatable bench experiments (Rs sweep, humidity, short/open, touch/drift) and ends with quantified acceptance fields for σ, drift slope, and touch sensitivity.

Applications (Bounded): Patterns by Rs & Leakage Sensitivity

These patterns are organized only by source impedance, leakage sensitivity, and noise dominance (en vs in×R). The goal is to identify typical failure signatures and the smallest countermeasure set, without expanding into full application system design.

Pattern 1 — High-Z electrochemistry (pA leakage dominates)
Dominant

Leakage → mean drift

Typical symptom

Humidity and touch create large mean steps and long recovery.

Fast check

Humidity A/B + guard on/off; compare mean shift and drift slope.

Primary countermeasure

Guard + clean/bake + keepout

Pattern 2 — Thermocouple / RTD front-ends (false drift from leakage)
Dominant

Leakage + Ib conversion

Typical symptom

Mean appears temperature-sensitive even when the sensor is stable.

Fast check

Clean/bake A/B; compare drift slope before and after.

Primary countermeasure

Guard + isolate input node

Pattern 3 — Bridge sensors with long cables (connector/cable leakage)
Dominant

Leakage path to shield/ground

Typical symptom

Touching/moving the cable changes the mean and “stability”.

Fast check

Swap cable/connector; compare touch step and recovery time.

Primary countermeasure

Guard at connector + cleanliness

Pattern 4 — Multi-channel MUX (memory effect from charge + leakage)
Dominant

Charge + leakage + R_equiv

Typical symptom

Previous channel influences the next channel mean; settling depends on history.

Fast check

Change channel order; insert a discharge window; compare mean convergence.

Primary countermeasure

Reduce R_equiv + bleed path

Boundary note: patterns are classified only by Rs and leakage/noise dominance; full application system design is handled in dedicated application pages.

Pattern map: application to dominant term to primary countermeasure A 2×3 grid of small cards mapping application patterns to dominant terms like leakage, Ib conversion, and in times R, with countermeasures such as guard, clean, reduce R, and limit bandwidth. High leakage risk ↑ Low Rs → High Rs Electrochem Leakage Guard Clean / keepout Thermocouple / RTD Leakage Ib×R Guard / isolate Bridge + cable Leakage Guard Connector path MUX multi-channel Leakage Charge Reduce R / bleed Remote high-Z Ib×R in×R Reduce R / limit BW Contaminated fixture Leakage Clean Guard / keepout
Application patterns are mapped only by source impedance and leakage/noise dominance. Each card links the dominant term (Leakage, Ib×R, in×R) to a minimal countermeasure set (Guard, Clean, Reduce R, Limit BW, Bleed path).

IC Selection Logic (Bias Current + Input-Referred Noise + Leakage)

This selection flow stays strictly within this page boundary: Ib/Ios/leakage paths that move the mean (offset/drift/nonlinearity) and en/in paths that set jitter and real resolution. The output is a practical shortlist and a vendor inquiry template that forces conditions and worst-case into the decision.

A) Inputs (fill these before comparing parts)

1) Source impedance class (Rs)

Choose one: Low-Rs (Ω–kΩ), Mid-Rs (kΩ–100kΩ), High-Rs (≥100kΩ up to MΩ/GΩ). This determines whether Ib×Rs and in×Rs become dominant.

Field
Rs class: ____
2) Leakage risk (environment + handling)

Classify the board-level risk: Clean & dry, typical production, or high-risk (humidity/contamination/touchable connectors/long cables/high temperature). High-risk pushes selection toward ultra-low-bias inputs and guard-friendly solutions.

Field
Leakage risk level: ____
3) Stability time and bandwidth/window

Define how fast a stable reading must be achieved (settling window) and what bandwidth is actually used (analog filtering + digital averaging + sampling window). This anchors noise comparison to a real output metric (σ / p-p).

Field
BW_eff + window policy: ____
4) Protection/network constraints

State whether clamp/TVS/ESD/series-R/input RC is mandatory. These parts can add leakage and increase R_equiv, shifting both bias and noise outcomes.

Field
Protection required: ____

B) Datasheet fields (only what matters for Ib/noise/leakage decisions)

Compare numbers only when the test conditions match the application (temperature, Vcm range, input voltage, gain, bandwidth, and any input protection state).

Bias / mismatch
  • Ib(max over temp) and the stated conditions (Vcm, Vin, supply, gain).
  • Ios(max) for Rs+ / Rs− mismatch conversion risk.
  • Ib vs Vcm / Vin dependency (avoid “typ looks great, worst-case fails”).
  • Input return-path requirement (high-R sources often need a defined bias return).
Noise
  • en (midband voltage-noise density) for low-Rs and wider BW_eff cases.
  • in (current-noise density) for high-Rs cases (in×Rs becomes dominant).
  • 1/f corner or low-frequency noise metric (used only to flag stability risk).
  • Switching artifacts indicator for auto-zero/chopper families (treat as a risk flag, not a marketing number).
Leakage-relevant structure
  • Input type label: FET/JFET, bipolar, zero-drift (used for initial filtering only).
  • Input protection hints: internal clamps, input mux/switches, and any “input current” notes.
  • Recommended guard guidance or layout notes for high-impedance use.

C) Decision rules (dominant mechanism first)

Rule 1 — Leakage-dominant signature

If humidity or touch/moving a cable changes the mean, leakage and surface paths are dominating. Prioritize ultra-low bias inputs, guard-friendly topology, and a leakage-aware protection network.

Rule 2 — High-Rs vs Low-Rs

High-Rs → bias/leakage and in×Rs can dominate; compare Ib(max), Ib dependencies, and in. Low-Rs → en and usable bandwidth/window dominate; filter first by en and stability time.

Rule 3 — Protection shifts the outcome

Mandatory series-R and clamps can raise R_equiv and add temperature-dependent leakage. Re-run the decision using the effective input network, not the bare sensor Rs.

Output of these rules: input type family + shortlist bucket, then validate with an Rs sweep and humidity A/B bench test before committing to production.

D) Concrete shortlist (by mechanism bucket)

Part numbers are provided as starting points for datasheet comparison. Always compare worst-case with matching conditions (temperature, Vcm range, Vin, gain, BW_eff, and protection state).

Bucket 1 — High-Z / leakage-driven designs (ultra-low bias priority)
TI INA116 ADI AD8220

Use when leakage paths and handling/humidity signatures dominate. Selection must be paired with guard strategy and cleanliness control.

Bucket 2 — Zero-drift / DC stability (mean accuracy over temperature)
TI INA188 TI INA333 ADI AD8230

Use when long-term DC stability and drift control are the main goals, and switching-family artifacts are treated as a verification item.

Bucket 3 — Noise-limited (low-Rs, real resolution set by en + BW_eff)
TI INA849 ADI AD8421 ADI AD8429

Use when the sensor is low impedance and output jitter/resolution is driven by voltage-noise density and the implemented bandwidth/window.

Bucket 4 — General-purpose baseline (production-friendly balance)
TI INA826 TI INA128 TI INA118 ADI AD8221

Use as a stable baseline for mid-Rs systems; then validate bias/leakage/noise with Rs sweep and humidity A/B before locking production.

E) Vendor inquiry template (forces conditions + worst-case + guardband)

Ask for the following in one response. Any number without conditions is not actionable for production sign-off.

Copy-ready fields
• Ib(max) over temperature: ____ (include Vcm, Vin, supply, gain)
• Ios(max): ____ (include measurement setup and source impedance assumption)
• Ib dependency: Ib vs Vcm range ____ and Ib vs Vin ____ (provide curve/table if available)
• en density and condition: ____ (gain, bandwidth, frequency point)
• in density and condition: ____ (gain, bandwidth, frequency point)
• Low-frequency noise metric: ____ (definition + test method)
• Input structure notes: ____ (internal clamps, mux/switching behavior, return-path requirement)
• Recommended guardband for production humidity/contamination: ____
• Suggested validation test: Rs sweep + humidity A/B + short/open signatures (confirm applicability)
INA selection flow for input bias, noise, and leakage A left-to-right flowchart: inputs such as Rs class, leakage risk, bandwidth/window, and protection requirements feed decision nodes for leakage dominance and Rs dominance, leading to four shortlist buckets with example part numbers. Inputs Rs class Leakage risk BW / window Protection Decisions Leakage-dominant? humidity / touch High-Rs? Ib×R / in×R Low-Rs? en + BW_eff Outputs High-Z INA116 AD8220 Zero-drift INA188 INA333 Low-noise INA849 AD8421 Baseline INA826 / AD8221
Selection uses four inputs (Rs class, leakage risk, BW/window, protection constraints) to decide the dominant mechanism and route to a shortlist bucket with example part numbers.

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FAQs (Bias Current, Leakage, and Input-Referred Noise)

Answers use a fixed 4-line structure: Likely cause / Quick check / Fix / Pass criteria. “IR” means input-referred; when measuring Vout, use IR = Vout / Gain.

Why does touching/moving the cable change the reading if CMRR is great on paper?
Likely cause
Cable handling changes leakage/tribocharge and the bias return path, injecting a DC shift that is not limited by datasheet CMRR.
Quick check
Toggle guard/shield on vs off and log Δmean (IR). Repeat after IPA clean + dry bake and compare the step size.
Fix
Add a defined bias return for each input, use guard ring / driven shield around high-Z nodes, and select low-leakage connectors/cables.
Pass criteria
With Rs = R_test and BW_eff = BW_test, touch/cable motion causes |Δmean(IR)| < X µV and humidity step (ΔRH = Y %) causes |Δmean(IR)| < Z µV.
How can picoamp leakage dominate even when INA bias current is “nA typical”?
Likely cause
External leakage (PCB surface, connector insulation, protection parts) adds an effective input current; with high Rs it creates Verror = I_leak × Rs.
Quick check
Do an Rs sweep (e.g., 10k → 100k → 1M) and fit Δmean(IR) vs Rs; a linear slope indicates current-driven error.
Fix
Reduce leakage by clean + bake, increase creepage, use guard, and replace clamps/TVS with low-leakage options or move them out of the high-Z node.
Pass criteria
Extracted leakage current I_leak = slope(Δmean(IR) vs Rs) satisfies |I_leak| < X pA over T = T_min…T_max and RH = RH_min…RH_max.
Why does adding input protection (TVS/diodes) increase drift?
Likely cause
Protection parts add temperature-dependent leakage and create extra nodes where Vcm/Vin changes modulate current, producing drift-like mean shifts.
Quick check
Compare drift slope with/without the clamp network (or with two clamp options). Repeat at two Vcm points used in the system.
Fix
Use low-leakage clamps, keep clamp voltage stress low, place clamps where leakage does not flow through high Rs, and ensure a stable bias return path.
Pass criteria
Across T = T_min…T_max and Vcm = Vcm_min…Vcm_max, protected configuration meets |d(mean(IR))/dT| < X µV/°C and clamp-induced offset shift |Δmean(IR)| < Y µV.
How to tell leakage drift from 1/f noise in a quick bench test?
Likely cause
Leakage drift correlates with humidity/handling/cleanliness; 1/f noise shows random wander without strong correlation to RH or guard state.
Quick check
Run two A/B tests: RH step (or breath box) and guard on/off, then compare Δmean(IR) and drift slope over a fixed window (e.g., 5–10 min).
Fix
If leakage-driven: clean, guard, improve creepage, replace leaky protection. If 1/f-driven: reduce BW_eff and set a stable averaging/window policy.
Pass criteria
Under ΔRH = Y %, leakage signature is absent when |Δmean(IR)| < X µV and change in drift slope < Z µV/min for guard on/off.
At what source impedance does current noise (in) become dominant?
Likely cause
Current noise contributes in×Rs; it dominates when in×Rs ≳ en for the chosen device and operating conditions.
Quick check
Measure σ(IR) with two known source resistances (e.g., Rs1 and Rs2) at the same BW_eff; if σ scales ~Rs, in×Rs is dominating.
Fix
Lower Rs (or effective Rs), select a lower-in input family, and/or reduce BW_eff via analog filtering and digital averaging/windowing.
Pass criteria
Crossover estimate meets design plan when Rs_cross = en/in falls above/below the actual Rs band as intended, and measured σ(IR, BW_eff) < X µV_rms.
Why does a larger input RC reduce noise but worsen stability of the reading?
Likely cause
Larger RC lowers BW_eff (less noise) but increases settling time and can amplify bias/leakage charging and capacitor dielectric effects.
Quick check
Step the input (or switch channels) and log time to settle within ±X(IR). Compare two RC values; instability shows as slow tail or mean shift vs time.
Fix
Use low-absorption capacitors (e.g., C0G/NP0), keep series-R minimal for the needed EMI limit, and add a defined bias/bleed path so nodes do not float.
Pass criteria
After a defined step/switch, output reaches and stays within ±X µV IR in < Y ms (or < Z samples) while maintaining σ(IR, BW_eff) < W µV_rms.
How to measure bias current without an electrometer?
Likely cause
Bias/leakage current can be estimated from how the mean shifts with a known series resistance: ΔV(IR) = I_eff × ΔRs.
Quick check
Insert two known resistors (Rs1, Rs2) and record mean(IR). Compute I_eff = (mean2 − mean1) / (Rs2 − Rs1).
Fix
Add production test jumpers to insert Rs, define a stable Vcm/Vin for the test, and keep clamps disconnected (or controlled) during bias characterization.
Pass criteria
Estimated |I_eff| < X pA at Vcm = Vcm_test, Vin = Vin_test, and T = T_test, with repeatability < Y pA across N = N_runs.
Why is the result different between open-input and short-input tests?
Likely cause
“Open” often removes the bias return and increases coupling/leakage sensitivity; “short” forces a defined potential and suppresses many leakage paths.
Quick check
Replace open with biased-open: add high-value return resistors and repeat. If the mean collapses toward the short result, the issue is bias/leakage, not noise floor.
Fix
Ensure every operating mode has a defined bias return, guard high-Z nodes, and verify leakage in the same cabling/connector configuration used in production.
Pass criteria
At BW_eff = BW_test, the difference between short and biased-open is |Δmean(IR)| < X µV and the touch sensitivity remains |Δmean(IR)| < Y µV.
Why do muxed channels show “memory” or slow settling?
Likely cause
MUX switching moves charge through input capacitances and protection networks; high Rs and leakage create a long RC tail, showing up as “memory”.
Quick check
Alternate two channels with different DC levels and log the transient after each switch. Repeat with a lower Rs or longer settle delay to confirm RC dominance.
Fix
Add precharge/bleed paths, reduce effective Rs, place RC where it does not trap charge, and enforce a channel-switch settle time before sampling.
Pass criteria
After a channel switch, residual carryover satisfies |Δmean(IR)| < X µV within < Y ms (or < Z samples) for the worst-case Rs channel.
Why does narrowing bandwidth/averaging reduce noise but not stop slow wander?
Likely cause
Averaging reduces wideband noise, but slow wander is often driven by leakage/bias dependency (mean shift) rather than random noise density.
Quick check
Keep BW_eff fixed and vary environment (RH/handling). If mean shifts while σ stays similar, the dominant term is bias/leakage, not noise.
Fix
Treat wander as a DC accuracy problem: control leakage paths, define bias return, and avoid protection leakage through high Rs; then average only after the mean is stable.
Pass criteria
Over a stability window of W min, mean drift meets |Δmean(IR)| < X µV while noise meets σ(IR, BW_eff, N_avg) < Y µV_rms.
Why does the reading shift when common-mode changes even if the differential input is constant?
Likely cause
Input bias/leakage often depends on Vcm; changing Vcm changes I_eff through protection structures and surfaces, translating into a differential error via Rs mismatch.
Quick check
Sweep Vcm across the operating range with fixed Rs and log mean(IR). Repeat with guard enabled to see whether the shift is surface-leakage driven.
Fix
Keep Vcm within the characterized region, minimize V stress across clamps, match Rs paths, and select inputs with low Ib variation vs Vcm for high-Rs designs.
Pass criteria
Over Vcm = Vcm_min…Vcm_max, mean shift satisfies |Δmean(IR)| < X µV for Rs = R_test and the production clamp network.
What pass criteria should be used for drift/noise in production?
Likely cause
Production failures usually come from leakage variability, bias dependency, and BW/window mismatch, not from a single “noise density” number.
Quick check
Define three tests: Short (noise baseline), High-Rs (bias/leakage sensitivity), and RH/handling A/B (leakage dominance) under the same BW_eff and averaging policy.
Fix
Lock a production test harness (cables/connectors), enforce cleaning/handling controls, and verify the clamp/RC network used in the field matches the test configuration.
Pass criteria
Report and enforce all four fields at fixed conditions: σ(IR, BW_eff, N_avg) < X µV_rms, p-p(IR, window) < Y µVpp, |d(mean(IR))/dT| < Z µV/°C, |Δmean(IR)| under ΔRH = W % is < V µV.