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Input Clamp & Leakage Budgeting for Instrumentation Amplifiers

Input Clamp & Leakage Budgeting for Instrumentation Amplifiers

← Back to:Instrumentation Amplifiers (INA)

Input clamp networks protect the INA input, but their leakage can become the dominant source of offset, drift, and slow settling in real wiring and humidity. This page shows how to model, design, verify, and production-test leakage so protection stays robust without sacrificing measurement stability.

Scope & boundary: what this page covers (and does not)

Input clamps keep a precision front-end alive, but their leakage creates hidden offsets, drift, and slow settling errors. This page treats leakage as a first-order error source: model it, budget it, then verify it on real boards.

Covered here (deliverables you can reuse)

  • Leakage source map: clamps (ESD cells, diodes, TVS), analog switches/MUX paths, and series R/RC nodes that inject leakage into a differential error.
  • Leakage-to-error model: convert Ileak into input-referred offset, drift with temperature/humidity corners, and settling creep on capacitive nodes.
  • Worst-case leakage budget: a stacking method that closes the system accuracy target without relying on “typical” numbers.
  • Verification & production hooks: practical tests that distinguish true leakage from fixture artifacts, plus signature-style checks suitable for manufacturing.

Not covered here (linked only; not expanded)

IEC 61000-4-x waveforms & compliance levels
Standards are broad; this page focuses on leakage-induced accuracy loss after protection is added. See: ESD / EFT robustness hooks
RFI filter “topology catalog” and EMI theory
RFI filtering is a separate design space; this page only tracks how protection networks create leakage errors. See: RFI/EMI-hardened input
INA architecture derivations and CMRR fundamentals
Architecture affects leakage sensitivity, but the topology theory belongs elsewhere. See: Architectures & types
By the end of this page
  • Any clamp or TVS Ileak,max can be mapped to input-referred offset, drift, and settling creep for the real sensor impedance.
  • A worst-case leakage budget table can be built and checked against the system accuracy target.
  • A verification plan can separate true leakage limits from cable, humidity, and fixture artifacts.
Boundary map: Input Clamp & Leakage Budgeting Center node shows this page; arrows point to related sibling pages that are linked but not expanded here. Input Clamp Leakage Budgeting Model • Budget • Verify RFI/EMI-Hardened Input filtering ESD / EFT Robustness compliance Architectures & Types topology Layout & Grounding routing Linked only Linked only Linked only Linked only
Boundary map: this page stays focused on leakage-induced accuracy loss from clamp/protection networks. Related topics are linked only, not expanded.

Why leakage budgeting is a first-order error in real systems

In precision front-ends, clamp leakage is rarely visible on a datasheet-driven block diagram. It becomes dominant after wiring, humidity, contamination, and input impedance turn tiny currents into measurable differential errors.

Symptom 1: output creeps for minutes after power-up
Most likely leakage path: clamp/TVS leakage charging an input-side capacitance through the real source impedance.
What this implies: the error is a dV/dt problem (settling creep), not just “offset drift”.
Symptom 2: zero shifts with temperature or humidity
Most likely leakage path: Ileak(T,RH) changes in clamps, MUX structures, or PCB surface films and is amplified by sensor/source impedance.
What this implies: accuracy cannot be closed without a worst-case leakage corner and a wiring-realistic impedance model.
Symptom 3: touching/moving the cable changes the “offset”
Most likely leakage path: the leakage return path or node bias shifts with shielding/handling, turning a small mismatch into a differential error.
What this implies: leakage behaves like a system-level error source (sensor + cable + PCB), not a single-component spec.
Practical conclusion

If leakage is not explicitly budgeted, worst-case accuracy cannot be closed—because real wiring (source impedance and capacitance) plus environment (temperature and humidity) amplifies tiny clamp currents into measurable differential error.

Symptom → leakage injection → error mapping Three field symptoms converge to a leakage injection node and map to offset, drift, and settling errors, with key amplification factors shown. Power-up creep minutes-scale Temp / humidity drift corner-driven Cable touch / move step-like shift Leakage injection clamps / MUX / PCB film I_leak mismatch Offset error V_err = I_leak · R Drift error ΔI_leak(T,RH) Settling creep dV/dt = I_leak / C Amplifiers: R_source • C_eq • Temperature • Humidity
Three common field symptoms converge to the same root: leakage injection plus real-world amplification factors (impedance, capacitance, and environment).

Leakage sources: where the current really comes from

Leakage is rarely a single “INA spec”. In real front-ends it is a layered system effect: device structures inject current, PCB films create hidden resistive paths, and cables/sensors provide leakage returns that change with environment and handling.

Device layer (components and silicon structures)
  • Clamps & ESD cells: reverse-biased leakage changes with node bias and temperature; mismatch turns into differential offset.
  • TVS devices: leakage and capacitance can both matter; large Ileak corners often dominate high-impedance sensors.
  • Analog switches / MUX: off-leakage creates channel-dependent offsets; leakage often depends on common-mode and supply rails.
  • Input structure (BJT/FET/CMOS): bias/leakage behavior sets the baseline for high-Z sources and long-term stability.
  • Package surface: surface leakage can rise with humidity and contamination and bypass “ideal schematic” assumptions.
Temp-sensitive Bias-dependent Channel mismatch
Quick signature
Replace or temporarily bypass the external clamp/TVS and compare the offset slope versus temperature. A large change indicates a device-dominated leakage corner.
PCB layer (surface films and geometry)
  • Flux residues & fingerprints: create hidden gigaohm paths that convert tiny currents into measurable errors with high source impedance.
  • Humidity films: change surface resistance with RH; drift may track environment more than silicon temperature.
  • Creepage and keep-out: short leakage paths across solder mask openings and silkscreen edges often dominate.
  • Missing guard: high-impedance input nodes are not shielded to a stable potential, so surface leakage becomes differential mismatch.
Humidity-driven Contamination-sensitive Layout-dominated
Quick signature
Compare offset before/after cleaning, and during a controlled humidity step. Strong correlation with RH indicates a PCB-film leakage path.
System layer (cables, shields, chassis, sensors)
  • Cable insulation resistance: leakage to shield/chassis acts like a parallel path that changes with moisture and bending.
  • Shield and chassis returns: handling or grounding changes the leakage return path and reveals differential mismatch.
  • Sensor leakage: the sensor itself can leak to housing or excitation rails, especially in wet/dirty environments.
Handling-sensitive Wiring-realistic Return-path effects
Quick signature
Swap the cable, change shield termination (single-point vs floating), and observe step-like offset shifts. Large changes indicate a system return-path dominated leakage loop.
Key takeaway

Leakage budgeting starts by identifying the injection nodes and the return paths across device, PCB, and system layers. Once the dominant layer is known, topology choice determines where leakage returns and how it appears as offset, drift, or settling creep.

Leakage path anatomy Diagram of a differential input front-end showing clamp/TVS leakage injection, PCB surface leakage, and cable shield return paths. System: Cable Shield / Chassis Sensor Bridge / High-Z IN+ IN− Shield Protection R R TVS Clamp I_leak I_leak INA Diff front-end PCB surface film R_surface C_film leak path return path
Leakage is a layered effect: device injection (clamps/TVS/MUX), PCB surface films (resistive/capacitive paths), and system returns (shield/chassis and cables).

Clamp & protection topologies (and their leakage signatures)

Topology decides where leakage returns and how it shows up in measurements. The same clamp current can become a repeatable offset, a temperature/humidity drift, or a slow settling creep depending on the leak node and the source impedance.

Topology A: diodes to rails
Protection: simple and fast for common transients.
Leakage signature: strong temperature dependence; mismatch becomes differential offset at the input node.
Best fit: lower source impedance and stable input bias conditions.
Topology B: clamp to Vref / Vcm
Protection: controls the clamp return in the reference/common-mode domain.
Leakage signature: looks like the input is biased toward Vref/Vcm; often repeatable but sensitive to Vref/Vcm stability.
Best fit: single-supply systems with a defined Vcm operating point.
Topology C: TVS + staged series R
Protection: strong survivability for harsh wiring and industrial transients.
Leakage signature: TVS leakage corners and added capacitance can create offset/drift and worsen settling creep on high-Z inputs.
Best fit: long cables and high-risk environments, with leakage budget explicitly sized.
Topology D: series R + internal clamp
Protection: leverages internal clamps while limiting current using external R.
Leakage signature: external leakage is reduced, but input bias times R can become a measurable offset; placement of R defines the leak node.
Best fit: precision-first channels where external TVS leakage is unacceptable.
Topology E: active clamp / current limit
Protection: controllable limiting and biasing for predictable error boundaries.
Leakage signature: depends on the control scheme; can be designed for low leakage but requires careful failure-mode planning.
Best fit: high-value channels that justify complexity to control leakage and survivability.
Next step

Topology choice identifies the leak node and the return domain. The next step is converting that leak node into a quantitative error model and stacking a worst-case budget.

Clamp topology comparison Five small panels compare clamp/protection topologies and mark the leakage injection node. A) to rails R R INA V+ V− leak node B) to Vcm R R INA Vcm leak node C) TVS + R R R INA TVS leak node D) internal clamp R R INA clamp leak node E) active limit / clamp Limiter INA leak node
Five common protection topologies. The leak node marker shows where leakage most directly converts into measurable offset, drift, or settling creep.

Design knobs: how to reduce leakage-induced error without losing protection

Protection is required, but leakage-driven error can be controlled. The key is adjusting a small set of knobs that directly change the leakage injection node, the return domain, and the surface leakage voltage across high-impedance areas.

Knob 1: series-resistor placement (before vs after the leak node)
What it changes: where leakage and clamp currents develop voltage across source impedance and how much of that voltage becomes differential error.
Primary benefit: can isolate external leakage from the INA inputs when R is placed to separate the leak node from the high-impedance measurement node.
Side effects: added thermal noise and reduced bandwidth/settling margin; placement can also increase Ib·R offset sensitivity.
Best fit: when the dominant leakage source is external (TVS/clamps) and the sensor source impedance is high enough for small currents to matter.
Knob 2: clamp/TVS selection using leakage-centric fields
What it changes: the worst-case leakage current corner and its temperature dependence at the operating reverse bias.
Primary benefit: reduces offset/drift created by Ileak,max mismatch and stabilizes behavior across temperature and humidity.
Side effects: lower-leakage parts may trade off surge energy handling or capacitance; capacitance can worsen settling creep for high-Z nodes.
Leakage-centric datasheet fields
  • Leakage vs temperature at the intended reverse bias
  • Max / distribution (avoid “typical-only” selection)
  • Capacitance at operating bias (settling impact)
  • Reverse standoff vs operating common-mode
Knob 3: bias / common-mode planning (keep nodes out of high-leak regions)
What it changes: the reverse bias across clamp junctions and the DC voltage across PCB surface leakage paths.
Primary benefit: reduces both device leakage and surface-film leakage by lowering the voltage that drives unwanted currents.
Side effects: the chosen common-mode must remain inside INA input CM range and preserve headroom for signal swing and transients.
Best fit: single-supply systems using Vcm/Vref where clamp return domain can be controlled.
Knob 4: guard / driven shield (short-circuit surface leakage to a safe potential)
What it changes: reduces the voltage across surface contamination films, preventing surface leakage from creating a differential mismatch.
Primary benefit: suppresses humidity-driven drift for high-impedance inputs by controlling the leakage return potential.
Side effects: added routing complexity and risk of coupling if guard is discontinuous or tied to the wrong potential.
Best fit: GΩ-class sources, electrochemistry, long cables, or any design showing strong humidity correlation.
Knob 5: cleaning / coating decision (treat contamination as an electrical element)
What it changes: the effective surface resistance and ionic paths that bypass the schematic.
Primary benefit: stabilizes drift and unit-to-unit spread when the leakage budget requires gigaohm-to-teraohm cleanliness.
Side effects: coating choices can introduce moisture absorption and repair complexity; verification is required to confirm improvement.
Best fit: harsh environments and high-impedance inputs where leakage corners dominate worst-case accuracy.
Side effects to watch (do not trade one failure mode for another)
  • Series R: noise and settling margin; placement can increase Ib·R sensitivity.
  • Low-leak clamps: check surge energy and capacitance at operating bias.
  • Bias/CM changes: must stay inside INA CM range and preserve headroom during transients.
  • Guard: requires continuity and correct guard potential to avoid coupling and new leakage paths.
  • Cleaning/coating: verify with humidity steps; do not assume improvement without data.
Knob-impact matrix Matrix showing how key knobs affect protection, offset, drift, settling, bandwidth, and complexity using dot intensity. Knob → Impact Protect Offset Drift Settle BW Complex Series R placement Clamp / TVS fields Bias / CM planning Guard / driven shield Cleaning / coating Dot opacity = impact strength
Knob-impact matrix: use it to choose the smallest set of changes that reduce leakage error without sacrificing required protection.

Layout & contamination control: guard rings, creepage, and humidity realism

Leakage budgets only work if the PCB enforces the assumed leakage paths. Guard continuity, keep-out geometry, and contamination control decide whether a board behaves like the paper model under real humidity and handling.

Guard ring rules (when to use and what potential to follow)
  • Use guard when high-impedance inputs and humidity correlation indicate surface-film leakage dominance.
  • Guard potential should minimize voltage across the surface film near IN+/IN− (reduce the leakage-driving field).
  • Continuity matters: broken guard segments create uncontrolled leakage shortcuts across solder mask edges.
  • Keep guard close to high-Z nodes and maintain a clean keep-out boundary around the input pins.
High-impedance “no-go zones” near input nodes
  • Vias in the keep-out: add contamination traps and shorten surface leakage paths.
  • Exposed pads and mask openings: increase humidity film sensitivity; reduce exposed perimeter near IN pins.
  • Silkscreen crossings: avoid ink near high-Z nodes; ink edges can hold moisture and residues.
  • Finger-access regions: keep high-Z routing away from touchable areas and connector “handling zones”.
Cleaning and coating decisions (budget-driven, not cosmetic)
  • Clean when the leakage budget requires gigaohm-to-teraohm behavior around IN nodes.
  • Coat when humidity and contamination are not controllable in the field and drift dominates worst-case accuracy.
  • Verify improvement with humidity steps; do not assume coating always reduces drift.
Creepage and clearance for leakage control (not breakdown)

Breakdown is a survivability event; leakage is a long-term accuracy problem. For leakage control, creepage increases the effective surface path length and reduces the chance that a humidity film becomes a low-resistance shortcut between sensitive nodes and returns.

Common layout mistakes (fast visual checks)

Via in the high-Z keep-out
Shorter surface path → humidity drift increases.
Silkscreen or mask opening near IN pins
Moisture film forms a leakage shortcut.
Broken guard ring
Uncontrolled surface voltage → leakage mismatch becomes differential error.
PCB high-impedance layout: guard, keep-out, and creepage Top-view PCB diagram showing an INA input area with guard ring, keep-out region, via exclusion, and a surface creepage leakage path marked with dashed lines. High-Z keep-out Guard ring INA IN+/IN− pins IN+ IN− Vias outside Silk / opening Creepage path Connector zone contamination Continuous guard
PCB realism: keep high-Z nodes inside a guarded keep-out, push vias/silkscreen away, and design creepage for leakage control under humidity.

Verification: how to measure leakage-driven offset/drift (without fooling yourself)

Leakage is best verified by changing a single variable that should scale the error (source impedance, humidity, or the clamp device), while keeping the measurement chain fixed. Each method below is structured as Setup → Readout → Pass criteria to reduce test artifacts.

Method A: two-source-impedance scaling (Rsource A/B)
Setup
Keep the board, fixture, cables, and shield termination unchanged. Switch only the effective input source impedance between two known values, then let the reading settle after each switch.
Readout
Record the zero offset (and the drift slope over a fixed time window) for both Rsource settings. Compare the ratio of the errors to the ratio of the impedances.
Pass criteria
Leakage-dominant behavior is indicated when the offset/drift scales strongly with Rsource. A weak or inconsistent scaling suggests a different dominant mechanism (reference/grounding/fixture artifacts).
Anti-trap check
Ensure the resistor switch hardware and insulation do not change the surface leakage path when toggling. Handle control and identical cable routing are required.
Method B: temperature / humidity steps (slope + hysteresis fingerprint)
Setup
Apply controlled steps of temperature or humidity while keeping the other variable as stable as possible. Do not touch or move cables during the soak and settle windows.
Readout
Fit the zero offset versus RH and versus temperature to extract slopes. Check for lag/hysteresis between humidifying and drying steps.
Pass criteria
Strong RH slope and hysteresis point to surface-film/contamination leakage. Strong temperature dependence with weak RH sensitivity points to device reverse-bias leakage corners or bias-domain coupling.
Anti-trap check
Verify that chamber feedthroughs, connectors, and cable jackets are not becoming the dominant humidity-sensitive path. Repeat with input shorted at the board edge to separate fixture effects.
Method C: state comparison (short vs open) + protection part swap
Setup
Compare three conditions using the same fixture: (1) IN+ and IN− shorted near the connector/board edge, (2) inputs open with identical routing, (3) replace or bypass one protection element (TVS or clamp network) while keeping all else unchanged.
Readout
Track offset level, drift slope, and any step changes after switching states. Repeat at a fixed RH point to avoid mixing variables.
Pass criteria
If swapping the protection element significantly changes RH or temperature slopes, the clamp device leakage corner is a primary contributor. If open-input behavior is much worse and RH-sensitive, fixture/PCB surface leakage is likely dominant.
Anti-trap check
Open-input tests are extremely sensitive to probe leakage and nearby objects. Use high-insulation fixtures and keep hands/tools away from the high-Z region during measurement.
Common test traps (artifact → what it mimics → one fix)
Probe / meter input leakage
Mimics input leakage; shifts offset during “open” tests.
Fix: use high-insulation probing, keep leads short, and apply guard where possible.
Fixture contamination
Mimics RH drift; creates unpredictable surface paths.
Fix: clean/bake fixtures, enforce handling rules, and repeatability checks.
Cable motion and strain
Mimics intermittent leakage and offset steps.
Fix: strain relief, fixed routing, and “no touch” soak windows.
Shield termination and ground loops
Mimics offset jumps and drift under load changes.
Fix: controlled A/B test of shield connection (single-point vs floating) with identical cabling.
Minimal proof set (fast and robust)
  • Run Method A to confirm impedance scaling.
  • Run Method B to separate RH film effects from device temperature leakage corners.
  • Run Method C to locate the dominant layer (clamp vs PCB/fixture vs system).
Leakage verification fixtures Three-panel diagram: source impedance switching jig, temperature/humidity chamber setup, and a guarded measurement concept. Three practical verification fixtures A) Rsource switch B) T/RH chamber C) Guard concept Selector R1 R2 DUT (INA) Read offset / slope Chamber DUT No touch Fit slope vs T/RH Guard High-Z node Surface film Reduce ΔV across film
A/B/C fixtures: impedance scaling, environmental slope fingerprinting, and guarded measurement concepts for separating leakage from artifacts.

Calibration & firmware hooks: what calibration can (and cannot) remove

Calibration removes repeatable, structured errors. Leakage-driven errors often depend on humidity, contamination state, and cable motion, so the practical solution is a combination of calibration plus monitoring, detection, and field-safe actions.

What calibration can remove (repeatable structure)

  • Static offset and gain under controlled and repeatable conditions.
  • Stable temperature behavior when the same board shows consistent slopes across repeated sweeps.
  • Fixed protection state where clamp bias and return domains do not change across operating modes.

What calibration cannot remove (state-dependent leakage)

  • Humidity-film drift with hysteresis and changing RH sensitivity.
  • Contamination changes after handling, cleaning, or long field exposure.
  • Cable-motion paths that create intermittent leakage and offset steps.

Practical identification strategy (stable vs state-dependent)

  • Repeatability test: if repeated zero measurements under the same conditions disagree beyond the noise budget, treat it as state-dependent.
  • Slope consistency: stable, repeatable slopes support calibration models; changing slopes indicate environmental leakage.
  • Step detection: sudden offset steps typically indicate path changes (motion/handling/contamination).

Firmware hooks (minimal set for production and field)

Online zero tracking
Update offset only during defined “known-zero” windows; reject updates when drift is non-stationary or when step events are detected.
Slope / step monitors
Track offset slope over time and flag step-like discontinuities; treat flagged periods as suspect for leakage path changes.
Periodic self-test hooks
If available, short/loopback the input path for a quick sanity check; compare against stored baselines to detect contamination or clamp leakage shifts.
Event logging
Log temperature, humidity (if present), operating mode, and the detected anomaly type (slope/step/repeatability) to enable field root-cause.

Note on chopper / auto-zero interactions (keep it bounded)

  • Auto-zero ripple and switching artifacts can interact with input clamps and series resistors, shifting the effective settling behavior.
  • If clamp capacitance is large, switching ripple can produce slow recovery tails that look like drift.
  • Verify using the same verification methods from the previous section before attributing the result to “INA drift”.
Error classification for calibration planning Two columns show calibratable structured errors and non-calibratable state-dependent leakage, with a firmware pipeline for monitoring and logging. Calibration boundaries + firmware hooks Calibratable (structured) Offset / Gain Repeatable temp model Stable operating state Not calibratable (state-dependent) RH film / hysteresis Contamination state Cable motion paths Firmware hooks Monitor Detect Flag Log
Calibration boundary: remove repeatable structure; use firmware hooks to detect, flag, and log state-dependent leakage behaviors.

Self-test & production test: catch leakage issues before shipping

Production failures caused by clamp/ESD leakage rarely look like “hard shorts.” They show up as board-to-board offset spread, temperature/humidity sensitivity, and unstable zero signatures. The goal here is to make leakage observable with repeatable, fixture-tolerant signatures—before the product reaches the field.

A) Three production-ready test hooks (each has a measurable signature)

Hook 1 — Input short “zero signature”
Setup: Short IN+ to IN− close to the clamp network (relay/switch), keep REF fixed.
Readout: Vout_zero (or ADC code) after a defined settle window.
Pass criteria: |Vout_zero − golden| ≤ VZ_limit (set by accuracy budget + ADC noise); no slow ramp within the window.
Hook 2 — Dual source-impedance “leakage gain” signature
Setup: Apply the same differential stimulus twice using two known RS levels (e.g., “low-R” then “high-R”), via an on-board resistor path or fixture.
Readout: ΔVout = Vout_highR − Vout_lowR (at the same stimulus).
Pass criteria: ΔVout scales with (RS,high − RS,low) within ratio_limit; outliers flag leakage injection upstream of the INA.
Hook 3 — Temperature spot-check (fast soak + thresholding)
Setup: Run Hook 1 + Hook 2 at one additional temperature point (hot or cold), with a short stabilization rule.
Readout: temp_slope proxies: ΔVout(T) and Vout_zero(T).
Pass criteria: |ΔVout(T) − ΔVout(25°C)| ≤ temp_limit; drift within the window ≤ ramp_limit.

Notes: keep signatures fixture-tolerant. Any test fixture, probe, or cable that adds its own leakage can defeat the purpose—treat the fixture as part of the leakage budget.

B) Failure analysis schema (minimum fields that make leakage debuggable)

Field Meaning How it helps root-cause
board_id / lot / date_code Traceability Separates process drift from random contamination
Vout_zero (Hook 1) Zero signature Catches clamp/PCB leakage that looks like “offset”
ΔVout (Hook 2) Leakage gain proxy Turns “invisible nA/pA” into a measurable delta
settle_time / ramp_metric Time-domain behavior Detects leakage charging caps / slow relaxation
temp_point / RH (if available) Environment Separates device leakage vs contamination sensitivity
protection_BOM_id Clamp/TVS variant Links leakage behavior to specific clamp choices

Reference example part numbers (starting points only; validate leakage over temperature)

  • Low-leak clamp diode (to rails): BAV199 (dual, ultra-low leakage)
  • ESD/TVS for signal lines (watch leakage & capacitance): TPD1E10B06, PESD5V0S2BT, SP3003-02JTG
  • Low-leak switches/MUX for on-board short / RS selection: TMUX1101 (SPST), TMUX1108 (8:1), ADG1209 (4:1 differential), ADG1204 (4:1)
  • Relay option (fixture-tolerant contact isolation): 9007-05-01 (reed relay)
  • Precision stimulus resistors (example thin-film): RG1608P-103-B (10 kΩ, 0603, ±0.1%)

Rule: any part connected to the high-impedance input node must be treated as a leakage contributor (including test switches and ESD devices).

Production BIST for clamp/leakage detection Block diagram showing input clamp network, short switch, dual source resistors, ADC sampling, and bin/field logging for leakage-driven offset and drift. Production BIST: zero + dual-R signatures + temp spot-check INA input node IN+ / IN− (high-Z) Clamp / ESD network diodes / TVS / series R leak node(s) Switch matrix Short / Rsrc-L / Rsrc-H Guard-friendly routing ADC sampling Vout_zero, ΔVout (dual-R) settle + ramp metrics Decision + logging binning: PASS / SUSPECT fields: board_id, BOM_id, T/RH Temp spot-check: repeat zero + dual-R at one extra temperature; flag abnormal slope
Diagram: a production-friendly BIST that converts leakage into measurable signatures (zero + dual-R delta), plus a minimal temperature spot-check to expose temperature-sensitive clamp/contamination leakage.

Applications & IC selection notes (kept within this page boundary)

This section keeps applications narrow and leakage-centric: each use case is mapped to its dominant leakage risk and the minimum hooks needed to keep protection while controlling leakage-induced offset/drift and settling error.

A) Leakage-driven application constraints (5 focused patterns)

1) Electrochem / pH / ion (GΩ sources)
  • Leakage risk: pA-level clamp/PCB leakage becomes mV-level “offset” through gigaohm sources.
  • Must-have hooks: driven guard / keep-out zones / ultra-low leakage protection strategy (often minimal + staged).
  • Reference examples: ADA4530-1 (electrometer buffer with guard) + TMUX1108 (ultra-low leakage MUX).
2) RTD / thermocouple weak signals (µV-level errors)
  • Leakage risk: leakage into input bias paths looks like “fake temp drift,” especially with long leads and humidity.
  • Must-have hooks: explicit bias return paths, low-leak clamps, and a defined settle window for each measurement.
  • Reference examples: INA333 (zero-drift INA) + BAV199 (low-leak clamp diode) + TPD1E10B06 (ESD TVS where needed).
3) Bridge / weighing with long cables (field wiring realism)
  • Leakage risk: cable insulation + shield/fixture paths change with touch/motion and humidity → wandering “CMRR” and zero jumps.
  • Must-have hooks: guard strategy (if high-Z nodes exist), staged protection at connector, and production zero signature (Hook 1).
  • Reference examples: INA125 (bridge-friendly INA with reference) + PESD5V0S2BT (low-leak ESD) + 9007-05-01 (reed relay for true input short).
4) Multiplexed DAQ (leakage stacking + slow settling)
  • Leakage risk: MUX + ESD + clamp leakage adds across channels; the “previous channel” memory shows up as long settling tails.
  • Must-have hooks: per-channel settle budgeting, low-leak MUX selection, and dual-R signature (Hook 2) to detect channel-dependent leakage.
  • Reference examples: TMUX1108 (ultra-low leakage MUX) or ADG1209 (differential MUX) + SP3003-02JTG (ESD array where required).
5) High common-mode measurement (external protection is unavoidable)
  • Leakage risk: protection to rails or references creates additional leakage injection nodes; CM surges can alter leakage states.
  • Must-have hooks: define where leakage must return (rails vs Vref), keep protection physically staged, and log protection BOM as a first-class field.
  • Reference examples: INA149 (high-CM diff amplifier) + staged clamps (e.g., BAV199 + external surge-rated TVS per system needs).

B) Selection checklist (fields that directly affect leakage-induced error)

Must-ask (datasheet / vendor)
  • Input structure & bias behavior vs temperature (Ib, input leakage corner cases).
  • Internal input protection behavior and allowed external series resistance range.
  • Input common-mode range near rails (to avoid “near-rail leakage surprises” and saturation recovery traps).
Must-pair (board-level)
  • Low-leak clamp/ESD parts selected explicitly for leakage (not only clamp voltage).
  • Guard & contamination controls for any node above ~100 MΩ equivalent impedance.
  • Production signature hooks (zero + dual-R) so leakage is measurable, not guessed.
Reference INAs / front-end ICs (examples only)
  • INA333 (zero-drift INA for DC precision)
  • INA125 (bridge-friendly INA with reference/excitation use cases)
  • INA149 (high common-mode diff measurement; protection staged externally)
  • AD8250 (PGA-type INA for multi-range DAQ, settling-aware designs)
  • ADA4530-1 (electrometer buffer + guard for GΩ sources ahead of the INA stage)
Application → leakage risk → required hooks Three-column mapping that keeps the page boundary: five application patterns, their leakage risks, and the minimum hooks to control leakage while keeping protection. Application → Leakage risk → Must-have hooks Applications Leakage risks Required hooks Electrochem / pH pA → mV through GΩ Driven guard Keep-out + clean RTD / Thermocouple fake drift (RH/T) Bias return path Low-leak clamp Bridge / Weighing touch/motion zero jump Staged protection Zero signature MUXed DAQ leakage stacking + tails Low-leak MUX Settle budget High common-mode extra leak nodes Define return node Log protection BOM
Diagram: keep applications inside this page boundary by mapping each use case to leakage risks and the minimum hooks (guard, staged protection, settle budgeting, and production signatures).

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FAQs: Input clamp & leakage budgeting

These FAQs are intentionally narrow: clamp devices, series resistors, leakage paths, and how their leakage turns into offset/drift/settling errors. Each answer is a 4-line, measurable checklist to prevent the main content from expanding sideways.

Why does offset change dramatically with humidity or after cleaning?

Likely cause: PCB surface film/contamination changes the effective leakage resistance around high-Z input nodes and clamp footprints.

Quick check: Repeat the zero signature (input short) at two RH levels; compare offset shift and within-window ramp slope.

Fix: Add/extend guard ring and keep-out around IN pins/clamps, enforce cleaning/handling policy; use a driven-guard buffer for GΩ sources (example: ADA4530-1).

Pass criteria: RH step causes |ΔVzero| ≤ RH_limit and ramp slope ≤ S_limit for the defined window.

Why does adding TVS/diodes “fix ESD” but ruin zero stability?

Likely cause: Clamp devices add temperature-dependent reverse leakage and create new “leak injection nodes” into the high-impedance input network.

Quick check: Compare Vzero(T) with/without the clamp footprint populated; leakage-dominated issues show a large temperature slope change.

Fix: Use staged protection (connector ESD + local clamp) and select low-leak parts; examples: diode clamp BAV199, ESD TVS TPD1E10B06, PESD5V0S2BT, array SP3003-02JTG (validate leakage over T/RH).

Pass criteria: Adding protection changes Vzero by ≤ Clamp_shift_limit and temperature slope by ≤ Temp_slope_limit.

How can a “tiny” leakage current create millivolts of error?

Likely cause: Leakage current across a large impedance creates voltage error (I × R), then gain multiplies it into a larger output offset.

Quick check: Increase source impedance by a known factor and observe whether offset scales proportionally (same wiring, same clamps).

Fix: Reduce effective impedance at the leakage injection node (bias return planning, guard, keep-out) and keep clamp leakage away from the highest-Z node (staging + placement).

Pass criteria: Offset scaling ratio matches impedance ratio within ±X% and stays inside the allocated error budget.

Why does the error grow with source resistance or sensor impedance?

Likely cause: Higher source impedance increases sensitivity to both clamp leakage and surface leakage, turning pA/nA into larger node voltage errors.

Quick check: Run the dual-R signature: measure the same stimulus at RS,low and RS,high; compute ΔVout.

Fix: Use FET/CMOS-input front ends for very high-Z sources and add driven guard; if switching is needed, pick low-leak switches/MUX (examples: TMUX1101, TMUX1108, ADG1204, ADG1209).

Pass criteria: ΔVout follows the expected scaling and remains ≤ ΔV_limit for the chosen RS range.

Why does the reading drift slowly after power-up (minutes)?

Likely cause: Leakage current charging input/filter capacitances or dielectric absorption causes a slow ramp until the node reaches a quasi-steady state.

Quick check: Capture a time trace after power-up under input-short and under open/sensor states; leakage-driven ramps persist even with zero stimulus.

Fix: Reduce leakage at the injection node (clean/guard/stage clamps), minimize unnecessary capacitance at high-Z nodes, and define a warm-up/settle window in the measurement sequence.

Pass criteria: Ramp slope within the measurement window ≤ S_limit and end-of-window shift ≤ V_window_limit.

How do I tell clamp leakage from INA input bias current?

Likely cause: INA input bias is device-intrinsic and relatively predictable vs conditions; clamp/PCB leakage is strongly topology/placement/RH dependent.

Quick check: Replace only the clamp population (or bypass the clamp node) while keeping the same INA; large offset changes implicate external leakage.

Fix: Move leakage away from the highest-Z node (staging + series R placement), or choose a lower-bias input front end for high-Z sensors; examples (application-dependent): INA333 (zero-drift INA), ADA4530-1 (electrometer buffer ahead of INA stage).

Pass criteria: Clamp swap changes offset by ≤ Clamp_swap_limit; remaining offset tracks datasheet bias expectations for the chosen source impedance.

Does placing the series resistor before vs after the clamp matter?

Likely cause: Yes—series R position determines whether clamp leakage injects error directly into the highest-Z node or is “isolated” behind a lower-Z point.

Quick check: A/B build: swap only R placement relative to the clamp node and re-run the dual-R signature and RH step test.

Fix: Place series R to limit surge current while keeping leakage injection at a controllable node; re-validate bandwidth/noise tradeoffs after moving R.

Pass criteria: Layout variant shows lower RH sensitivity and ≤ ΔV_limit offset shift for the same ESD protection level.

Why does touching/moving the cable change the offset?

Likely cause: Cable insulation/shield/fixture paths create variable leakage and capacitive coupling; motion changes the return path and the leakage injection point.

Quick check: Perform a repeatable “touch test” with the input shorted vs connected; changes under short implicate fixture/PCB, changes only with cable implicate wiring paths.

Fix: Improve cable strain relief and shielding termination consistency, stage protection at the connector, and avoid high-Z exposed nodes near user-touch areas; use relay-based hard short for debug (example reed relay: 9007-05-01).

Pass criteria: Touch/motion produces offset step ≤ Step_limit with a defined procedure and cable routing.

How do I measure leakage without being fooled by fixtures and probes?

Likely cause: Probes, adapters, dirty sockets, and long cables often contribute more leakage than the DUT, creating false conclusions.

Quick check: Run the same test with (1) fixture open, (2) fixture short, (3) DUT installed; if fixture signatures shift, the fixture is leaking.

Fix: Use guarded measurements and low-leak switching, keep fixtures clean/dry, and minimize exposed high-Z surfaces; use low-leak switch/MUX examples: TMUX1101, TMUX1108, ADG1209.

Pass criteria: Fixture-only baseline remains stable within ≤ Fixture_limit across the test window and RH range.

Can calibration remove leakage-induced drift reliably?

Likely cause: Calibration removes stable, repeatable offset/gain terms; leakage that changes with RH, contamination, or motion is not stable and will not stay calibrated.

Quick check: Calibrate once, then apply RH/temperature/cable motion perturbations; if the residual offset varies widely, leakage is not calibratable.

Fix: Treat leakage as a physical design problem (guard, cleaning, staging, series R placement) and use calibration only for the remaining stable offset/gain.

Pass criteria: Post-cal residual stays within ±Cal_residual_limit under defined environmental and handling stresses.

What layout features most often dominate leakage in production?

Likely cause: Missing/incorrect guard, exposed solder mask openings, long creepage across contaminated surfaces, and high-Z routing near flux residue zones.

Quick check: Visual + electrical: inspect mask/keep-out around IN pins and clamp parts, then compare RH sensitivity before/after cleaning and conformal coat trial.

Fix: Guard rings tied/driven to the correct potential, strict keep-out around high-Z nodes (no silkscreen, no test pads), and controlled cleaning/handling process.

Pass criteria: RH sensitivity and lot-to-lot offset spread reduce to ≤ Spread_limit in production sampling.

Why do “identical” boards show different offsets across lots?

Likely cause: Lot variation often comes from clamp/leakage contributors (device leakage corners, PCB process/cleanliness, conformal coat variability, fixture drift), not from the INA alone.

Quick check: Log protection BOM IDs and run the same zero + dual-R signatures across lots; clustering by clamp BOM/PCB process strongly suggests leakage contributors.

Fix: Make leakage controllable: lock clamp/ESD part numbers (examples: BAV199, TPD1E10B06, PESD5V0S2BT, SP3003-02JTG), control cleaning/handling, and add production signatures (short + dual-R) as release gates.

Pass criteria: Lot-to-lot offset distribution stays within the allocated Ppk/Cpk target and within ±Lot_limit around the baseline.

Note on part numbers: The listed part numbers are starting points for datasheet lookup. Always validate leakage over temperature, humidity, and applied voltage in the exact topology and placement used on the PCB.

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