Switched-capacitor filters deliver repeatable, clock-set cutoff and well-controlled responses using charge transfer and capacitor ratios.
Real success depends on managing clock quality, spurs/noise folding, and the dynamic input/loading behavior with the right interface and verification steps.
What is a Switched-Capacitor Filter?
A switched-capacitor (SC) filter is a discrete-time analog filter that moves charge through capacitors using
non-overlapping clock phases. Its corner frequency is primarily set by clock frequency, while its coefficients are set by
capacitor ratios (matching-dominated).
Key takeaway: frequency is clock-defined, and shape is ratio-defined — but the system behaves like sampling,
so switching ripple, folding noise, and clock sensitivity must be engineered.
RC filters are set by absolute R and C. SC filters are set by clock and capacitor ratios, but introduce
clock-related ripple/spurs that must be verified.
Practical verification (fast sanity checks)
Clock-defined corner: change fCLK; the measured corner should shift proportionally (per datasheet scaling).
Clock-locked spurs: in FFT, spurs often appear at fCLK and harmonics; their frequency should track the clock.
Sampling behavior: without adequate input attenuation near fCLK/2, out-of-band energy can fold into the passband.
Scope control: response-family selection and order planning are owned by the Cascaded Biquads page; this page focuses on
SC implementation, clocking, and non-idealities.
The Core Mechanism: Charge Transfer & Req = 1/(C·fSW)
SC filters approximate resistors and integrators by moving a known charge packet each switching cycle. With a two-phase, non-overlapping clock
(φ1/φ2), a capacitor samples a voltage difference and then transfers that charge to the next node. The average current created by repeated
charge transfer yields a useful equivalent resistance.
In many ICs, fSW equals fCLK or a fixed divide of it (as documented in the datasheet scaling).
The equivalent resistance model is a sanity-check tool for scaling and interfaces. It assumes charge packets transfer as intended each cycle.
When the Req model holds (and when it breaks)
Non-overlap must be correct: overlap can create short paths (spurs, distortion, abnormal current). Excessive dead-time can reduce effective settling time.
Settling must meet the error target: if internal amplifiers do not settle within each phase, coefficients shift and distortion/noise increase.
Source/load impedance matters: SC inputs look like a time-varying load; high source impedance can turn “simple scaling” into dynamic errors.
Clock purity matters: jitter/phase noise and clock feedthrough can dominate, showing as clock-locked spurs or raised in-band noise.
Quick scaling examples (order-of-magnitude):
• If C = 10 pF and f = 1 MHz, then Req ≈ 1/(10e−12·1e6) ≈ 100 kΩ.
• If target Req ≈ 10 kΩ at f = 2 MHz, then C ≈ 1/(R·f) ≈ 1/(10k·2M) ≈ 50 pF.
Scope control: full z-domain derivations are intentionally excluded. The goal is an implementation-grade model that supports
estimation, interface checks, and debug hypotheses.
The next step is to map this model into SC building blocks (integrators and biquads) and then quantify real-world deviations (charge injection, clock feedthrough,
kT/C noise, folding, and settling error).
Architectures Inside SC Filters: Integrator, Biquad, and Chains (Implementation View)
Most SC filter ICs are built from a small set of reusable blocks: a sampling network driven by non-overlapping phases (φ1/φ2),
one or more charge-based integrators (op-amp or OTA), a summing/feedback network, and often a
common-mode control loop in differential implementations. This view clarifies ownership: which blocks set
magnitude/phase (coefficients) versus which blocks dominate noise and distortion.
Core ownership:C ratios and clock timing set coefficients;
settling, switch non-idealities, and
common-mode behavior set real-world noise/THD/spurs.
Implementation ownership helps debugging: coefficients come from capacitor ratios and timing, while real-world limits come from
settling, switch feedthrough/injection, and common-mode behavior.
Block ownership: what mainly sets magnitude/phase vs noise/THD
Sampling network (φ1/φ2 switches): sets discrete-time behavior; dominates clock-locked spurs when feedthrough/injection is high.
Integrators (op-amp/OTA charge amps): settling accuracy and swing limits set in-band error, noise shaping limits, and THD at higher amplitudes.
Capacitor ratios (C1:C2:C3…): set coefficients and track well over process/temperature; absolute capacitance is less critical than ratios.
Common-mode control (VOCM/CMFB): in differential SC, wrong common-mode causes early clipping and even-order distortion.
Scope control: response-family and order planning belong to the Cascaded Biquads page. This section focuses on
implementation blocks and their ownership of real-world performance.
Clocking Rules: fCLK, Non-Overlap, Duty, Jitter, and Spurs
In SC filters, the clock is both the time base and the energy injection mechanism.
Many devices specify corners by fc = fCLK / N or fc = k · fCLK, where N (or k) is fixed by the internal topology and clocking plan.
Verification should begin by confirming scaling, then separating clock-locked spurs from noise-floor lift.
Fast scaling check: sweep fCLK across two values and verify that fc moves per the published relationship.
If fc does not scale cleanly, suspect incorrect clock divide, phase/duty distortion, or insufficient settling.
Clock quality defines SC outcomes: confirm scaling (fc vs fCLK), then diagnose clock-locked spurs and noise-floor lift
using the nearest test points.
Actionable clocking rules (SC-specific)
Scaling first: verify fc follows fCLK per fc=fCLK/N (or k·fCLK). If not, suspect wrong divide, duty distortion, or settling limits.
Non-overlap tuning: overlap increases short-path current (spurs/EMI/THD). Excessive dead-time reduces settle time and can shift coefficients.
Spur vs jitter symptom: clock-locked lines track fCLK; jitter/phase noise tends to raise or smear the noise floor and widen sidebands.
Clock source pitfalls: MCU GPIO clocks can inject supply/ground bounce; PLLs can add fractional spurs; spread-spectrum may reduce EMI but broaden energy.
Scope control: this page provides SC clocking criteria and debug rules, not a full clock-system design tutorial.
In switched-capacitor filters, amplitude response can look correct while the waveform appears “dirty” due to switching artifacts.
The most common roots are charge injection (glitch/offset), clock feedthrough (clock-locked spurs),
and switching ripple that downstream stages may demodulate, fold, or alias into the passband.
Symptom → likely cause (fast triage):
• Narrow FFT lines at fCLK / 2fCLK → clock feedthrough or clock-coupled return paths.
• Step-like spikes at phase transitions → charge injection / switch injection into a high-impedance node.
• Ripple becomes worse when a wideband or sampling stage is connected → switching ripple being “seen” by the next stage.
A clean magnitude response does not guarantee a clean waveform: injection and feedthrough create time-domain artifacts that often show up as
clock-locked spurs in the spectrum.
Charge injection: why glitches and offsets appear
When a MOS switch turns off, channel charge and gate-related coupling inject a charge packet into surrounding nodes. If that charge lands on a
high-impedance sampling node, the result is a voltage step (glitch). Depending on downstream bandwidth and sampling behavior, the same
artifact can look like a transient, a spur, or a low-frequency offset shift.
Strong dependencies: signal swing, switch sizing, node impedance (source/load), clock edge speed, and phase timing.
Quick check: change input swing or source impedance; injection-driven steps often scale with these changes.
Measurement trap: probing capacitance can magnify or reshape glitches; verify with a low-C probe or differential probing when available.
Clock feedthrough: why fCLK spurs appear
Clock feedthrough is primarily capacitive coupling from clock nodes into signal nodes (parasitics). It often produces
narrow spectral lines at fCLK and harmonics. A defining property is that spur frequency
tracks the clock when fCLK is changed.
Fast discriminator: sweep fCLK → spur frequencies move with fCLK; amplitude may change with edge rate and coupling paths.
Typical paths: gate-to-channel capacitance, substrate coupling, and clock return currents disturbing analog reference/common-mode nodes.
Practical mitigation: differential signaling (reject common-mode), controlled edge buffers, and disciplined return paths near the clock chain.
Switching ripple: why downstream stages “see” it
Ripple can be present as high-frequency components tied to switching phases. A downstream wideband stage or any sampling stage can
transform that ripple into in-band noise, intermodulation, or alias-like artifacts.
This explains why a standalone bench check may look clean, but a full chain (buffer/ADC/rectifier) reveals contamination.
Controlled mitigation: a small post RC can reduce ripple/spurs, but it trades group delay, settling time, and (in some chains) stability margin.
Apply only when passband error and latency budgets allow it.
Scope control: input protection and ESD clamp strategies are handled by the Clamp & ESD Front-End page, not here.
Mitigation toolbox (with trade-offs)
Differential implementation: improves common-mode rejection of clock coupling; requires valid common-mode control and headroom.
Bottom-plate sampling: reduces injection into sensitive nodes; increases timing complexity and clock integrity requirements.
SC noise and drift become manageable when treated as a budget with measurable contributors. Key sources include
kT/C sampling noise, folding of wideband noise into the passband, settling error due to amplifier limits,
and leakage/absorption/temperature effects that create low-frequency error.
Treat noise and drift as a stack with knobs: capacitor size, bandwidth control, phase time/GBW (settling), and temperature/leakage paths.
kT/C sampling noise: the “C buys noise” trade
Every sampling event leaves a thermal noise imprint whose scale decreases as sampling capacitance increases. Larger C tends to reduce the kT/C term,
but it also increases the required charge per cycle, raising drive burden, settling demand, and sometimes
switching-related artifacts.
Budget knob: increasing effective sampling C reduces this contributor.
Quick measurement: with input shorted (or a low-noise reference), measure in-band noise versus configuration that changes effective C (if supported).
Folding: why in-band noise can exceed intuition
Because SC filters are sampled systems, wideband noise from sources, buffers, or internal amplifiers can be mapped into the passband by sampling action.
The result can be an in-band noise floor that looks too high even when the nominal transfer function is correct.
Fast discriminator: reduce out-of-band noise (add or tighten a prefilter, limit source bandwidth) and check whether in-band noise drops.
A strong correlation indicates folding dominance.
Amplifier limits: settling error becomes magnitude/phase error and THD
In SC filters, the critical question is whether internal charge amplifiers settle to the required error within each clock phase.
Insufficient settling (due to limited GBW, slew rate, output swing, or load) creates coefficient error that appears as
corner shift, peaking error, and distortion at larger signal levels.
Quick check: increase fCLK (or reduce phase time) and observe whether passband error or THD worsens disproportionately.
Passband symptom: magnitude/phase deviates before obvious clipping if settle time is the limiting factor.
Leakage, absorption, and temperature drift: when it looks like “drift” vs “noise”
Leakage paths and dielectric absorption can slowly change held charge, producing low-frequency error. Temperature can modulate leakage and device parameters,
creating drift-like behavior that may be repeatable under controlled conditions.
Practical distinction:
• Drift-like: repeatable with temperature/time, shows a trend under soak.
• Noise-like: statistics dominate across repeats, weak dependence on soak direction.
Quick check: hold a constant input and log output over time; repeat with a temperature step and soak to reveal time constants.
Impedance hint: bias or leakage errors often change when input/source impedance or bias paths are altered.
Budget template (what to write down, what to measure)
Contributor
Main knob
How to measure
Mitigation
Pass criteria
kT/C
effective C
input short/quiet source, in-band RMS
increase C / lower BW where allowed
below noise budget target
folding
source BW
tighten prefilter, compare in-band noise
limit out-of-band noise
noise drops as expected
settling error
tφ / GBW / swing
fc/peaking/THD vs fCLK and amplitude
more phase time, lower swing, better drive
within magnitude/THD limits
leakage/drift
Temp / bias paths
time log + temp step/soak
bias control, guarding, recal
drift below system threshold
external ADC quantization
ENOB / range
include as external term
range planning
budget closes
Scope control: ADC quantization derivations are intentionally excluded; quantization is treated as an external budget term only.
Linearity & Dynamic Range: What Sets THD/SFDR in SC Filters?
In switched-capacitor filters, distortion and spurious limits are rarely set by a single block. THD/SFDR typically comes from a combination of
switch path nonlinearity (RON variation, signal-dependent injection), clock-coupled spurs (feedthrough and return coupling),
finite settling within each clock phase, and (in differential implementations) common-mode dynamics plus mismatch that elevates
even-order distortion.
Fast mental model: first identify whether the dominant artifacts are clock-locked (track fCLK) or
signal-locked (track input tone placement). Then confirm whether distortion is driven more by amplitude,
frequency, or common-mode conditions.
Use lock tests and controlled sweeps to separate clock-locked spurs from signal-locked distortion mechanisms.
Switch path nonlinearity and signal-dependent injection
The switch network is a primary distortion engine in SC filters. RON nonlinearity and signal-dependent charge injection
create harmonic content and discrete spur patterns, especially when artifacts land on high-impedance sampling nodes.
Source impedance and clock edge behavior strongly influence how visible these effects become.
Fast checks: (1) fCLK sweep to identify clock-locked lines; (2) amplitude sweep to confirm signal dependence;
(3) small series R or source impedance change to expose injection sensitivity.
Differential SC: advantages and common failure modes
Differential SC filters improve rejection of common-mode clock coupling, but linearity can collapse when VOCM is set incorrectly,
when common-mode dynamics are slow relative to phase switching, or when layout and capacitor ratio mismatches introduce even-order distortion.
A practical signature is an elevated 2nd harmonic (THD2) compared with other harmonics.
Rule of thumb: if THD2 dominates and changes strongly with VOCM or output common-mode conditions, prioritize common-mode integrity and symmetry checks.
Amplitude and frequency dependence: distinguish settling/SR from injection
Looks like settling/SR: THD worsens with higher tone frequency at constant amplitude; corner/peaking may shift subtly; sensitivity increases when phase time is reduced.
Looks like injection/feedthrough: discrete lines and spur patterns are clock-correlated; strong sensitivity to source impedance, edge rate, and clocking conditions.
Production-friendly measurement: single-tone, two-tone, and spur identification
Single-tone tests reveal harmonic structure and SFDR, while two-tone tests separate intermodulation products from clock spurs.
The most reliable spur identification uses controlled sweeps: clock spurs follow fCLK, while IMD products follow the input tone placement.
Practical notes: coherent sampling is preferred for stable SFDR comparisons. When non-coherent sampling is unavoidable, apply a consistent window and keep test conditions fixed to preserve comparability.
Scope control: detailed ADC-driver stability is handled in the FDA and ADC interface pages; this section focuses on SC-originated distortion signatures and test discrimination.
Interfacing: Source/Load Impedance, Anti-Alias Before SC, and Post-Ripple Filtering
SC filter inputs behave like dynamic sampling loads: they draw charge in a clocked pattern rather than presenting a simple static input impedance.
If the source impedance is too high, the input node can droop during charge transfer and recover incompletely, producing magnitude error, distortion,
and increased sensitivity to injection artifacts.
Interface objective: present a low-enough dynamic source impedance at the sampling instant, and limit out-of-band energy that can fold into the passband.
A compact “sandwich” interface reduces dynamic loading, suppresses folding pathways, and controls spur/ripple visibility—validated at three measurement nodes.
Front-end RC or buffer: why it is often required
A small front-end RC or a suitable buffer helps present a stable source during charge transfer, reduces sensitivity to injection artifacts,
and constrains out-of-band energy that would otherwise fold into the passband. The sizing must respect passband error and transient requirements.
Trade-off note: overly large RC can introduce passband attenuation, phase shift, and slow recovery—keep values consistent with the system’s latency and flatness budgets.
Anti-alias before SC: minimum engineering rule
Before the SC stage, the anti-alias objective is to prevent significant energy near sampling-related regions from being mapped into the passband.
A practical minimum rule is to ensure that interference and broadband noise approaching the Nyquist region tied to the SC clocking
are sufficiently suppressed so they cannot fold into in-band noise.
Folding discriminator: tighten the front-end bandwidth (or reduce out-of-band noise) and verify that in-band noise decreases. A strong correlation indicates folding dominance.
Scope control: full anti-alias filter synthesis and stopband design belong to the dedicated Anti-Alias / Reconstruction Interface page.
This section keeps only SC-specific interface constraints.
Post-ripple filtering: spur reduction with phase and settling budgets
A post RC stage can significantly reduce fCLK-related ripple and spur visibility, especially when the next block is wideband or sampled.
The filter must be sized within the allowed group delay and settling window, and it should not create an impractical load for the following stage.
Verify at POST_OUT: confirm spur reduction at fCLK/2fCLK while passband amplitude/phase remains within the system tolerance.
Interface debug playbook (short path)
Source impedance probe: add a small series R or switch to a lower-Z source and compare THD/SFDR.
Node isolation: measure at IN and SC_OUT to determine whether distortion originates from source drive or SC artifacts.
Bandwidth clamp: tighten the front-end bandwidth and check whether in-band noise drops (folding indicator).
Post cleanup: enable or adjust post RC and verify spur reduction at POST_OUT without breaking phase/settling budgets.
Practical Implementation: PCB/Layout, Clock Routing, EMI, and Grounding for SC
Switched-capacitor filters behave like mixed-signal RF blocks on a PCB: fast clock edges generate broadband harmonics, return currents can pollute
analog references, and small asymmetries convert common-mode coupling into in-band distortion and spurs. A robust layout controls
clock coupling, return paths, differential symmetry, and high-impedance leakage
with actions that are easy to review and verify.
Scope control: this section focuses on SC-specific coupling paths and PCB actions, not full product EMC compliance or certification practices.
Treat CLK as a high-harmonic aggressor and protect IN/VOCM/high-Z nodes using distance, symmetry, continuous return paths, and close decoupling.
Clock routing: minimize coupling and keep return paths tight
Do: keep CLK short; avoid stubs; place a continuous reference plane under CLK; route CLK away from IN, VOCM, and high-Z nodes; add ground stitching near CLK corridors when needed.
Verify: sweep fCLK and confirm that any suspicious lines track fCLK/2fCLK; move cabling/probes to expose coupling sensitivity (a strong indicator of layout-driven pickup).
Power and grounding: confine switching currents away from analog references
SC internal switching currents must close locally through low-impedance loops. If return currents flow through shared ground bottlenecks,
clock-related ripple and spurs appear on analog nodes as “mysterious” SFDR limits.
Decoupling tiers: place small high-frequency capacitors tight to the supply pins to catch edge currents; add mid-band bulk nearby to absorb longer transients; keep the return path short and continuous to the local plane.
Differential routing reduces sensitivity to common-mode coupling only when symmetry is preserved. Small asymmetries
(length, reference plane, via transitions, nearby aggressors) convert common-mode pickup into differential error, often elevating THD2 and clock-related spurs.
Do: route DIFF pairs together in the same environment; keep via patterns symmetric; maintain continuous reference; keep VOCM/REF nodes away from CLK corridors.
Signature: THD2 rises disproportionately and changes with VOCM or nearby aggressor placement → prioritize symmetry and common-mode routing hygiene.
High-impedance nodes: leakage, contamination, and guard practices
Leakage and surface contamination can dominate low-frequency accuracy and appear as drift-like behavior. High-impedance sampling and bias nodes
are especially sensitive to flux residues, humidity, and temperature-dependent leakage paths.
Actions: minimize high-Z trace length; keep high-Z nodes away from board edges/connectors/CLK; apply guard where appropriate; enforce cleanliness and stable surface conditions.
Signature: drift/noise changes strongly with temperature or humidity → prioritize leakage-path inspection and guard effectiveness.
SC layout review checklist (board-level, short list)
CLK corridor: short, no stubs, no parallel run with IN/VOCM; continuous reference plane under CLK.
Return continuity: no plane splits under CLK/IN; no shared bottleneck where clock currents cross analog references.
Decoupling: HF caps tight to pins; returns short into local plane; mid-band bulk close to entry.
DIFF symmetry: same layer/environment, symmetric vias, consistent spacing to aggressors.
VOCM/REF hygiene: short routing, protected area, away from CLK and fast IO.
High-Z protection: minimize length, guard where needed, cleanliness controlled, away from edges/connectors.
Measurement points: IN, SC_OUT, POST_OUT accessible without long loops.
Verification & Debug: How to Measure SC Filters Without Fooling Yourself
SC filter measurements can be misleading when probe loading, non-coherent sampling, and clock-source impurities are not controlled.
Reliable verification separates three questions: magnitude/phase, spur/SFDR, and time-domain behavior.
Each objective requires a specific instrument choice, connection practice, and a clear pass/fail discriminator.
Scope control: production data schemas and binning belong to the production reporting page; this section covers measurement methods and decision criteria.
Start with the measurement goal, then enforce coherence, probing hygiene, and node isolation to prevent false SFDR/THD conclusions.
Measuring magnitude and phase: sweep choices and setup hygiene
For amplitude and phase response, sweep-based methods are preferred. Use a connection that preserves the intended source and load conditions,
and avoid introducing hidden poles with long ground leads or excessive probe capacitance. When clock-dependent artifacts are suspected,
test repeatability improves when the stimulus and sampling are synchronized to a stable clock plan.
Check: compare IN vs SC_OUT responses to confirm whether deviations originate from the source/interface or inside the SC stage.
Spur identification: clock-locked lines, sampling images, and supply sidebands
Clock-locked: sweep fCLK and verify spur tracking at fCLK/2fCLK. Tracking indicates feedthrough, injection, return coupling, or CLK routing pickup.
Sampling-related images: tighten the front-end bandwidth or reduce out-of-band noise and confirm that in-band noise/spurs reduce. A strong correlation indicates folding/alias pathways.
Supply sidebands: change supply impedance (decoupling placement/value) and watch spur sidebands move or shrink. Sensitivity implies power/ground return dominance.
Time-domain observation: glitch, settling, and saturation recovery
Use time-domain views to confirm glitch magnitude near clock phase boundaries, settling inside the expected time window, and recovery behavior
after saturation events. Probe loading can change the observed waveform significantly; short-ground probing and controlled bandwidth settings
improve repeatability.
Trap: long ground leads and high probe capacitance can create or amplify apparent ringing and spur-like structures that are not present in the real node behavior.
Debug flow (trusted order)
Lock the clock: sweep fCLK and classify clock-locked lines vs signal-locked distortion.
Check interface impedance: compare IN and SC_OUT; adjust source impedance/RC/buffer to expose dynamic-load sensitivity.
Check injection and common-mode: run amplitude sweeps and VOCM sweeps; use THD2 dominance as a symmetry/common-mode indicator.
Return to layout coupling: apply the H2-9 checklist to verify CLK corridor, return continuity, decoupling proximity, and high-Z leakage controls.
Engineering Checklist: Design Review + Bring-Up + Production Hooks
This checklist section turns SC-filter guidance into a repeatable workflow. Each item maps to a measurable action:
review what can break (clock, interface, headroom, symmetry, decoupling), bring up in a trusted sequence, and embed production hooks
so failures can be isolated and configurations can be traced by version.
Scope control: production database schemas and bin definitions are intentionally excluded here; this section focuses on review steps, bring-up order, and test hooks.
A compact, copyable checklist: review risk items early, bring up in a trusted order, and embed hooks to isolate failures and trace configuration versions.
Design review (SC-specific, measurable items)
A) Clock quality & distribution
• Clock source type and spur risk (PLL/dividers/spread-spectrum).
• Buffer path and isolation from analog nodes; continuous return plane under CLK routing.
• Non-overlap/duty constraints satisfied by the selected clock mode (device-specific).
• fCLK range margin: minimum, maximum, and profile switching plan.
B) Interface window (RC / buffer / measurement nodes)
• Source impedance and RC range defined as a tunable window (footprints reserved).
• Anti-alias expectation at ~fCLK/2: ensure out-of-band energy is bounded to prevent folding.
• Measurement access reserved at IN, SC_OUT, POST_OUT with short loops.
C) Amplitude headroom & common-mode integrity
• Input/output swing limits checked across supply and temperature corners.
• VOCM/REF routing protected and kept away from CLK corridors and fast IO.
• Differential symmetry plan (routing, vias, reference plane continuity) to prevent THD2 elevation.
D) Decoupling and return confinement
• HF caps placed tight to pins with short returns to the local plane; mid-band bulk placed near supply entry.
• No plane splits under CLK/IN; no shared ground bottlenecks where switching return currents cross analog references.
Step 1 — Baseline spur scan (light load, short loops)
• Set a stable fCLK and run a spectrum scan to classify clock-locked lines.
• Sweep fCLK and confirm tracking at fCLK/2fCLK to isolate clock/return coupling early.
Step 2 — Add nominal load and verify magnitude/phase
• Compare responses at IN, SC_OUT, POST_OUT to separate interface vs SC-core effects.
• Confirm that post-ripple filtering (if used) does not create unexpected phase/latency penalties.
Step 3 — Stress temperature and supply disturbances
• Run temperature sweeps and observe drift/noise changes to expose leakage and reference sensitivity.
• Inject controlled supply ripple or change decoupling impedance to test return-path robustness.
Step 4 — Limits: extreme fCLK and input amplitude
• Verify max/min fCLK profiles and switching transitions (spurs, settling, and stability).
• Sweep input amplitude/frequency to identify headroom limits, injection dominance, and THD2 signatures from asymmetry.
Production hooks (design-for-test and traceability)
Loopback path: provide a known-good internal/external routing to isolate SC core versus downstream blocks.
Known injection point: add an accessible node for stimulus injection without long flying leads or unstable ground loops.
Clock check: reserve a test point or a readback method to validate fCLK presence/profile state during test.
EEPROM configuration version: store profile ID, calibration revision, and build metadata as a compact version field for field traceability.
Applications (Placed Late): Where SC Filters Win
SC filters win when frequency and matching must be repeatable across channels and production lots, and when bandwidth can be defined
by a shared clock profile. The examples below focus on deployment patterns and design hooks,
not full end-to-end application chain design.
Three common deployment patterns: audio consistency and phase control, sensor AFE multi-channel repeatability with calibration hooks, and multi-standard bandwidth switching via clock profiles.
Audio codec / acoustics
SC filters fit audio chains when channel-to-channel consistency and production repeatability matter. On-chip ratios set repeatable response
shapes with low calibration burden. The primary system risk is clock-related spur visibility and phase/group-delay expectations.
Design hooks: keep clock spurs out of audible bands; protect phase/group delay consistency across channels; validate spur sensitivity to fCLK and supply impedance early.
Multi-channel sensor platforms benefit from shared clock definitions and stable ratio-based responses. SC profiles can be validated quickly and
maintained across lots when production hooks exist for loopback and known injection.
Design hooks: enforce minimum anti-aliasing near fCLK/2; define an interface RC window; reserve IN/SC_OUT/POST_OUT access; store a compact configuration version field.
Common failure mode: high source impedance plus out-of-band noise leads to folding, elevating in-band noise despite a “correct” amplitude response.
Multi-standard front ends (bandwidth switching via clock profiles)
When a front end must support multiple bandwidths, SC clock profiles provide a clean control axis for fc and response placement.
The tradeoff is spur/EMI management and ensuring that interface assumptions remain valid across profiles.
Design hooks: verify spur tracking across profile changes; manage transients during profile switching; re-validate interface RC/buffer behavior for each profile; keep clock routing and return confinement consistent.
Selection note (fast fit check)
Prioritize SC when:
• Multi-channel matching and repeatability matter more than absolute RC tolerance.
• Bandwidth must be switched via a shared clock profile.
• Integration and production consistency are primary constraints.
Be cautious when:
• Clock spurs are unacceptable and clock quality cannot be controlled.
• Source impedance is high and buffering/RC windows cannot be added.
• EMI constraints require aggressive clock edge shaping without degrading SC performance.
H2-13. IC Selection Logic (Switched-Capacitor Filter ICs)
This section turns datasheet browsing into a structured scorecard: Ask Vendor (evidence to request) and Verify (bench checks to run). The goal is to avoid “it works on paper” failures caused by clock spurs, dynamic input loading, and common-mode limits that are specific to switched-capacitor filters.
A) How to use this scorecard
Start with Clock and Spur/Noise rows; SC filters are clock-defined and clock-contaminated.
Treat the Input model row as mandatory; a switched-capacitor input is a periodic charge load, not a simple resistor.
Run the Verify checks on 3 nodes whenever possible: IN → SC_OUT → POST_OUT.
Lock down a baseline clock source + layout + configuration version before chasing THD/SFDR.
B) Selection scorecard (Ask Vendor / Verify)
Use the middle column as the vendor request email/template, and the right column as the bring-up checklist. Keep each cell short; details live in the cards below.
Tip: keep vendor replies attached to the project revision. For each row, save the datasheet page reference and the bench result (plot or screenshot).
C) What to ask vendors (copy-paste templates)
1) Topology / coefficients / profiles
“Which coefficient method is used (capacitor ratio only, factory trim, runtime digital calibration)? Provide accuracy over temperature.”
“Are multiple response profiles supported? Provide magnitude/phase and group delay curves for each profile with test conditions.”
“Does profile switching create transients or memory effects? Provide recommended sequencing (mute/settle time).”
Probing changes behavior: scope probe capacitance alters charge paths; validate with low-C probes or buffered measurement points.
F) Reference part numbers (official links; starting points only)
The following material numbers are listed to speed up datasheet lookup and bench comparison. Final selection must be driven by the scorecard above (conditions, guardbands, and system verification).
Universal / building-block SC filters (programmable by clock + resistors)
TI:MF10-N — dual 2nd-order state-variable SC filter building block.
Analog Devices (Linear Tech):LTC1060 — dual universal filter building block.
Analog Devices (Linear Tech):LTC1064 — quad SC filter building blocks (higher order by cascading).
Analog Devices (Linear Tech):LTC1067 / LTC1067-50 — rail-to-rail dual universal building blocks.
Analog Devices (Linear Tech):LTC1068 — quad 2nd-order clock-tunable building blocks.
Analog Devices / Maxim:MAX7490 / MAX7491 — dual universal SC building blocks (rail-to-rail style family).
Pick 2–3 candidates that match the architecture need (building block vs fixed lowpass), then run the same clock, source impedance, and FFT measurement recipe. Only keep parts that remain stable under the intended clock source, layout constraints, and common-mode/swing margins.
Short, actionable troubleshooting for switched-capacitor filters. Each answer follows a fixed 4-line structure to keep scope tight and verification-driven.
Why does the noise floor rise when I increase fCLK even if fc stays the same?
Likely cause: Higher clock-related folding/alias energy and/or clock phase noise is being translated into the in-band region.
Quick check: Run FFT at SC_OUT and POST_OUT while sweeping fCLK (small steps). Check whether broadband noise tracks fCLK or changes with the clock source.
Fix: Improve clock quality (lower jitter/cleaner buffer supply), add/strengthen anti-aliasing ahead of SC, and use a post-filter if clock ripple dominates.
Pass criteria: In-band noise at POST_OUT remains within the system noise budget across the intended fCLK range (no unexpected noise lift vs baseline clock).
Why do I see a strong spur at fCLK (or 2·fCLK) at the output?
Quick check: Sweep fCLK: a feedthrough spur shifts exactly with fCLK. Compare IN → SC_OUT → POST_OUT FFT to locate where the spur enters.
Fix: Improve clock routing/return, isolate clock buffer supply, reduce coupling to sensitive nodes, and add a post-filter tuned to suppress fCLK tones (verify stability).
Pass criteria: Clock-locked spurs at POST_OUT are below the system SFDR/spur budget across fCLK corners and load conditions.
Why does THD get worse mainly at large amplitude but not at small signals?
Likely cause: Large-signal settling limits, headroom/common-mode constraints, or signal-dependent charge injection becoming dominant near higher swing.
Quick check: Run amplitude sweep at fixed in-band frequency. Watch for a “knee” where THD slope changes; sweep VOCM (if differential) to see if even-order products rise.
Fix: Reduce swing, adjust VOCM/headroom, lower source impedance or add a buffer, and avoid operating near output/input swing limits.
Pass criteria: THD/SFDR remains monotonic and within budget over the required amplitude range (no abrupt knee within the operating window).
Why does the response change when I probe with an oscilloscope?
Likely cause: Probe capacitance/ground lead inductance alters the switched-capacitor charge path, loading, or creates extra coupling at clock-related frequencies.
Quick check: Compare 10× passive vs low-C active probe; shorten ground connection. Check if changes occur mainly at SC_OUT and near fCLK tones.
Fix: Add a dedicated buffer/test point, use low-capacitance probing, and keep measurement return paths short and controlled.
Pass criteria: Measured response is invariant (within tolerance) across approved probing methods; spur/noise does not change materially with probe swap.
Why does adding a simple RC at the input “fix it” but reduce bandwidth more than expected?
Likely cause: The SC input behaves like a dynamic charge load (effective Cin + sampling draw), so Rsource·Ceq is larger than the intended RC alone.
Quick check: Sweep R and C separately; observe how fc and passband ripple move. Compare with a buffered source (low Rsource) to isolate loading effects.
Fix: Use a buffer (or lower Rsource), choose RC within the vendor’s recommended window, and treat the SC input as part of the filter network.
Pass criteria: Response meets bandwidth/phase targets with a practical front-end RC (and remains stable across source impedance tolerance).
Why does a shared MCU clock create random-looking sidebands?
Quick check: Repeat FFT with MCU activity reduced (idle mode) and with an external clean clock. If sidebands collapse, the shared clock path is the driver.
Fix: Use a dedicated clock source/buffer for the SC filter, isolate supplies/returns, and avoid sharing noisy digital clock nets directly.
Pass criteria: Sidebands/spurs remain stable and within budget across normal MCU activity profiles (no “mode-dependent” spectral surprises).
Why do two channels mismatch in phase even with the same clock?
Likely cause: Channel-to-channel coefficient mismatch, unequal source/load impedance, or clock distribution skew causing different effective sampling/settling behavior.
Quick check: Swap channel inputs/loads; if phase error follows the external network, it is board/interface driven. Check clock routing symmetry and return paths.
Fix: Match front-end RC/buffers and routing, ensure symmetric clock distribution, and use differential routing/common-mode control consistently.
Pass criteria: Phase mismatch stays within the system phase budget across frequency band and temperature, with stable (repeatable) channel alignment.
Why does the filter clip earlier than expected even though rails look sufficient?
Likely cause: Internal headroom limits (VOCM window, internal amplifier swing, charge transfer nodes) and dynamic loading peaks that are not obvious from DC rails.
Quick check: Sweep amplitude while monitoring THD and time-domain waveform at SC_OUT; vary VOCM (if applicable) and load to see if the clip point moves.
Fix: Re-center VOCM, reduce swing, increase headroom (supply choice), and avoid heavy loading or use a post buffer.
Pass criteria: Clip point and distortion remain outside the required signal range with guardband across supply/temperature corners.
Why does temperature change move the corner even though SC should be ratio-accurate?
Likely cause: Clock frequency drift, temperature-dependent switch/on-resistance effects, internal amplifier settling changes, or profile/calibration drift with temperature.
Quick check: Measure fCLK at the device pin over temperature; compare fc drift with and without a low-impedance source/buffer; repeat in a stable profile.
Fix: Stabilize/compensate the clock, add guardband for settling across temperature, and use vendor-recommended calibration/profile sequencing if available.
Pass criteria: Corner frequency remains inside the system tolerance band across the required temperature range (with documented clock stability).
How do I quickly tell clock feedthrough from power-supply coupling?
Likely cause: Feedthrough is primarily capacitive coupling of clock edges; supply coupling is modulation through supply/ground impedance and buffer rails.
Quick check: Sweep fCLK: feedthrough tones move with fCLK. Inject/alter supply ripple: supply-coupled sidebands change with supply conditions and decoupling.
Fix: For feedthrough: improve clock routing/spacing/return and add post-filter. For supply coupling: isolate buffer supply, fix return paths, and reinforce decoupling.
Pass criteria: Identified spur family responds only to its dominant knob (clock sweep vs supply perturbation) and remains below budget after targeted fixes.
When is a post-filter mandatory, and how do I keep it stable?
Likely cause: Clock ripple/spurs at SC_OUT exceed the next-stage spur/EMI budget, or the load is sensitive to clock-locked energy.
Quick check: Compare FFT at SC_OUT vs POST_OUT (temporary RC). If spur reduction is required to meet SFDR/EMI limits, a designed post-filter is mandatory.
Fix: Use a simple RC (or a well-damped active stage) with a defined load; include isolation resistance if driving capacitive loads; validate phase margin/stability.
Pass criteria: fCLK-related spurs at POST_OUT meet the system budget without inducing ringing/oscillation or unacceptable group delay.
What is the fastest production test to catch bad clocking/alias folding?
Likely cause: Excess jitter/clock integrity issues or insufficient pre-SC anti-aliasing causing folded energy and clock-locked spur families.
Quick check: Run a short FFT test with a known injected tone plus a “quiet” input condition; look for clock-locked spurs and unexpected in-band noise lift.
Fix: Gate out failing units via spur/noise metrics, then trace upstream: clock source/buffer, clock routing/return, and front-end RC/AA network.
Pass criteria: Production FFT metrics (clock-locked spur bins + in-band noise bins) stay inside pre-defined limits with margin for fixture variation.
