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SC / Gm-C Caveats: Clock Feedthrough, Folding, Drift & Linearity

SC / Gm-C Caveats: Clock Feedthrough, Folding, Drift & Linearity

← Back to: Active Filters & Signal Conditioning

SC and Gm-C filters most often fail in practice not because of the equations, but because clocks and switching couple into high-impedance nodes, creating spurs, folded images, pedestal steps, and drift from gm/PVT and tuning loops. Use minimal discriminator tests (change fs, amplitude/common-mode, clock edge rate, or freeze tuning updates) to identify the dominant mechanism, then fix the actual path (isolation/returns, injection control, noise–settling tradeoffs, and production markers with traceable logs).

H2-1 · Page Positioning & Quick Mental Model

SC and Gm-C filters are powerful because they “move signal behavior” into clocks and biasing. The caveat is that clocks and biasing then become signal paths—showing up as spurs, images, drift, or sudden distortion.

Switched-Capacitor (SC): clock-driven charge transfer. Any parasitic coupling or edge activity can leak clock energy into high-impedance sampling nodes, creating fixed spurs, sidebands, and step errors that look like “mysterious tones.”

Gm-C: poles/zeros set by transconductance. gm is not constant—it shifts with PVT, common-mode, bias, and swing. That shift moves fc/Q and can trigger compression/IMD once OTA linear range or CMFB headroom is reached.

  • Noise floor rises
  • Fixed spurs (fs/2fs)
  • In-band images
  • THD suddenly collapses
  • fc/Q drifts with temperature
Diagnostic mindset: treat every symptom as a mapping from observable signature → dominant mechanism → one fast experiment (clock edge, fs ratio, amplitude sweep, temperature sweep).

Five high-frequency pitfalls that repeatedly dominate real systems

  1. Clock spur at fs/2fs: usually clock feedthrough or supply/ground coupling. Fast check: move the clock divider—spur moves → see H2-4/H2-10.
  2. In-band “mirror” tones: folding/aliasing or clock-modulated images. Fast check: add temporary pre-limit RC—mirror reduces → see H2-5.
  3. Step/pedestal error after switching: charge injection and switch timing. Fast check: slow down edge or adjust non-overlap—step changes → see H2-6.
  4. fc/Q shifts with temperature: gm drift and tuning-loop quantization/injection. Fast check: temperature sweep + fc/Q tracking → see H2-8.
  5. THD “cliff” at a certain amplitude: gm compression, CMFB headroom, or Ron nonlinearity. Fast check: THD vs amplitude knee analysis → see H2-9.

Risk profile: what tends to bite first (SC vs Gm-C)

Risk axis SC tends to be sensitive to… Gm-C tends to be sensitive to…
Spurs edge coupling, feedthrough paths, digital/clock routing tuning activity, bias coupling, LO-like modulation in OTA stages
Folding / images insufficient pre-limit bandwidth, fs too low, strong out-of-band interferers large out-of-band blockers driving nonlinearity into IMD components
Drift clock duty/phase variation, capacitor tempco mismatch, reference sensitivity gm PVT drift, bias tempco, tuning-loop granularity
Linearity Ron nonlinearity + driver settling under large steps gm compression, swing limits, CMFB headroom
Noise kT/C + jitter-to-noise in sampled nodes OTA noise shaping vs bandwidth, bias noise translating to output
EMI coupling clock edges acting as antennas near high-Z nodes bias rails and tuning nodes acting as demod points
Figure F0 — SC vs Gm-C risk profile (quick mental model)
Risk profile: where SC vs Gm-C typically fails first SC Gm-C Spurs Spurs fs, 2fs, sidebands tuning/bias coupling Folding Folding images into band blocker-driven IMD Drift Drift caps/ref sensitivity gm PVT drift Linearity Linearity R_on + settling compression/CMFB Noise Noise kT/C + jitter OTA/bias noise EMI EMI edge radiation bias demod Tip: treat “clock and bias” as signal paths; design them like signal nets.
Use this as a fast orientation tool: the darker the dots, the earlier that axis tends to dominate real failures.

H2-2 · When SC vs Gm-C Fails in the Field

Real failures are usually “triggered,” not random. The trigger is a system condition that amplifies a specific non-ideality until it becomes visible in spectrum, drift plots, or distortion sweeps.

The fastest workflow is to classify the platform into a risk pattern: clock-edge & routing (spurs), fs ratio & pre-limit (folding), amplitude headroom (linearity), and temperature/PVT (drift).

SC: common triggers, what they look like, and the one fast check

  1. Strong interferers near clock harmonics: coupling turns edge energy into a tone at fs/2fs or sidebands.
    Fast check: change divider / PLL fractional mode; spurs move with clock → route to H2-4/H2-10.
  2. ADC front-end too wideband (weak pre-limit): out-of-band energy is sampled and folded into the passband.
    Fast check: insert a temporary 1st-order RC or narrow prefilter; if images drop sharply → H2-5.
  3. fs too low / margin to Nyquist too small: the “folding window” is too close; small changes create large in-band artifacts.
    Fast check: increase fs or change decimation; if image location moves predictably with fs → H2-5.
  4. Clock edges too sharp near high-Z sampling nodes: larger dV/dt creates larger capacitive injection and ground bounce.
    Fast check: slow clock edge (series R / drive strength); spur amplitude changes strongly → H2-10/H2-11.
Practical rule: if a tone follows the clock plan (divider, PLL mode, routing), assume a clock-related mechanism before chasing “analog magic.”

Gm-C: common triggers, what they look like, and the one fast check

  1. Large temperature span: gm drift moves fc/Q and can change loop stability/settling behavior.
    Fast check: temperature sweep with fc/Q tracking; monotonic shift points to gm/bias → H2-8.
  2. Supply/bias perturbations: bias coupling modulates gm or CMFB headroom, creating spurs or gain drift.
    Fast check: inject a small supply ripple (controlled) and observe spur/gain sensitivity → H2-10/H2-8.
  3. Large PVT dispersion across units: “same register setting” produces different fc/Q across boards.
    Fast check: compare unit-to-unit fc/Q histograms; wide spread implies tuning/trim necessity → H2-8/H2-12.
  4. Strict THD/SFDR targets: OTA linear range becomes the limiting factor; distortion shows a knee with amplitude.
    Fast check: THD vs amplitude sweep; knee behavior indicates compression/headroom → H2-9.
  5. Near-boundary input swing or common-mode: CMFB and output headroom saturate early; distortion “cliffs.”
    Fast check: repeat THD sweep at different common-mode/supply; strong dependence indicates CMFB/headroom → H2-9.
Practical rule: if fc/Q moves with temperature or supply, treat gm and bias rails as “frequency-setting components,” not just housekeeping.

Failure signature map (use this before deep debugging)

The matrix below maps what is visible in the spectrum (spur/image/noise floor) to what is visible in time/slow variables (step behavior, amplitude knee, temperature drift). Each cell points to the most likely mechanism chapter later in this page.

Figure F1 — Failure signature map (frequency features × time/slow-variable features)
Signature map: observe → classify → jump to mechanism Frequency-domain feature (what the spectrum shows) Time/slow-variable feature (what sweeps show) Fixed spurs Images Noise floor Step / settling tail Amplitude knee Temp / time drift H2-4 feedthrough + injection (H2-6) H2-5 folding images + switching tail H2-7 kT/C + settling budget H2-9 R_on nonlin + driver limits H2-9 IMD / compression H2-10 jitter-to-noise + EMI coupling H2-8 gm/bias drift → fc/Q shift H2-5 fs plan images move H2-7 noise vs temp bias/ref Use: identify the strongest signature first; do one fast experiment; then deep-dive the mapped mechanism.
The goal is speed: classify the failure with one observable + one sweep (clock/fs/amplitude/temperature), then jump to the mechanism chapter.

H2-3 · Non-Ideality Taxonomy Map

Non-ideal behavior becomes manageable when every symptom is routed into a small set of mechanism “buckets.” The taxonomy below is designed for fast field triage: identify the dominant signature, run one quick check, then apply the most effective fix lever.

  • Clock-related
  • Switch-related
  • Sampling-related
  • OTA-related
  • Noise-related
Workflow: Signature → Bucket → Quick check → Fix lever. Avoid “shotgun fixes” until the signature moves predictably with one controllable variable (clock/fs/amplitude/temperature).

Quick bucket summaries (scan first)

Clock-related: feedthrough, jitter, spurs, EMI coupling. Signature: tones follow clock plan (divider/PLL mode) or edge strength.

Switch-related: charge injection, Ron nonlinearity, body effect, overlap timing. Signature: steps/settling tails and amplitude-dependent THD knees.

Sampling-related: aliasing/folding, images, weak band-limiting. Signature: image locations move with fs and drop with temporary pre-limit filtering.

OTA-related: gm drift, compression, swing limits, CMFB constraints. Signature: fc/Q drifts with temperature/supply; THD cliffs near headroom limits.

Noise-related: kT/C, reference/bias noise, quantization/folded noise. Signature: noise floor shifts with sampling C, jitter, or reference/bias conditions.

Mechanism Observable signature Front-line check Common fix levers
Clock feedthrough Spurs at fs/2fs, sidebands; strong edge sensitivity Change divider / slow edge; spur moves or drops Non-overlap, edge control, keepout, shield, symmetry
Clock jitter → noise Noise floor rises on fast-slope signals; skirt-like noise Swap clock source/jitter; floor changes Lower jitter, re-time, limit input slew, narrow BW
EMI coupling Spurs change with layout/load; near-field probe finds clock Move cable/grounding; spur changes Return-path control, shielding, split domains, decouple
Charge injection Step/pedestal error; settling tail after switching Adjust non-overlap; step changes Bottom-plate sampling, dummy switches, timing balance
Ron nonlinearity THD/IMD grows with amplitude; knee appears Amplitude sweep; knee shape is consistent Bootstrapped switch, reduce swing, increase headroom
Overlap timing Extra tones, leakage, unexpected gain errors Change overlap window; tones change Non-overlap clocking, timing guardband, slower edges
Folding / aliasing In-band images; image location tracks fs Change fs or add temporary RC; images move/drop Stronger pre-limit, re-plan fs, reduce OOB energy
Insufficient band-limiting Noise/tones appear only in system (not bench) Add simple RC; artifacts reduce sharply Front-end limit, keep OOB blockers out, impedance control
gm drift (PVT) fc/Q shifts with temperature/supply; unit-to-unit spread Temp sweep + histogram; drift/spread visible Tuning loop, trim, bias stabilization, reference integrity
gm compression THD cliff at a specific amplitude; IMD rises fast THD vs amplitude at multiple CM/supply Reduce swing, increase headroom, linearize OTA, bias adjust
CMFB / swing limit Distortion + common-mode anomalies near rails Shift common-mode; cliff moves More headroom, CMFB redesign, output stage capability
kT/C noise Noise floor improves with larger sampling C Change sampling C; floor scales Increase C, adjust BW, optimize sampling network
Reference/bias noise Broadband floor or spurs correlate with ref/bias Isolate ref/bias; observe floor/spur change Cleaner reference, better decoupling, partition domains
Folded downstream noise Noise appears after decimation/mode changes Change mode/decimation; floor changes Anti-alias on control paths, stage BW planning, filtering
Figure F2 — Taxonomy map: physical paths → frequency/time signatures
Taxonomy: trace signatures back to physical paths Physical path buckets Clock-related feedthrough · jitter · EMI Switch-related injection · R_on · overlap Sampling-related folding · images · BW limit OTA-related gm drift · compression · CMFB Noise-related kT/C · ref/bias · folding Trace couple inject sample compress drift What becomes visible Fixed spurs fs · 2fs · sidebands Images / folding moves with fs Noise floor kT/C · jitter · ref THD knee IMD / compression Drift fc/Q vs T, time Use: start from the visible signature (right), then trace back to the physical bucket (left).
This map prevents scope creep: it classifies mechanisms without teaching full topologies, and routes each issue to the correct deep-dive chapter.

H2-4 · Clock Feedthrough

Clock feedthrough is not a single effect; it is a set of coupling paths that move clock edges into signal-referenced nodes. The most efficient fix comes from identifying which path dominates: direct parasitic coupling, reference/virtual-ground modulation, or supply/ground bounce.

Typical field signature: spurs around fs, 2fs, or fs ± fin, with strong dependence on layout, load conditions, and clock edge strength.

Fast discriminator: change a controllable clock attribute (divider, edge rate, routing) and observe whether the spur moves or scales predictably. Predictable movement indicates clock dominance.

Coupling path classes (what to look for)

Path A — Gate/parasitic C into sampling node: high-Z nodes convert tiny coupled charge into visible spur + step behavior.

Path B — Virtual ground / reference / common-mode modulation: “non-signal” nodes become the carrier; spurs can appear at fs ± fin.

Path C — Supply/ground bounce: return-path impedance turns clock edge current into ΔV that rides on the signal chain.

Mitigation levers (ordered by typical effectiveness)

  1. Symmetry & differential routing
  2. Non-overlap clocking
  3. Edge-rate control
  4. Shield/keepout near high-Z nodes
  5. Return-path & ground-bounce control
  6. Clock nets away from sampling plates

Practical ordering guidance: start with clock edge-rate and routing keepout (fast to change), then lock down return paths, and finally enforce symmetry/differential for the sensitive nodes.

Figure F3 — Clock feedthrough coupling paths (A/B/C) and sensitive nodes
Clock feedthrough: three dominant coupling paths CLK Gen Divider / PLL CLK Net Edge strength / routing Path A Parasitic C → CLK Switch High-Z sampling node Cpar Signature fs / 2fs spur step + tail Path B Modulate ref/CM CLK Ref / CM coupling Virtual GND / CM node Signature fs ± f_in tone varies w/ load Path C Supply/ground bounce CLK PDN Return path ΔV Signature spur scales w/ load layout dependent Most sensitive nodes: high-Z sampling plates, virtual grounds, reference/common-mode nodes, and PDN return paths.
Use the path that best matches the signature: A (edge/step sensitive), B (fs ± f_in modulation), C (load/layout dependent).

H2-5 · Folding / Aliasing & Images

Folding (aliasing) is a frequency-translation problem: sampling replicates the spectrum around multiples of fs, so out-of-band energy can be transported into the passband as images. In switched-capacitor (SC) systems, internal switching can also behave like modulation, creating structured sidebands.

What causes in-band artifacts (without a full AA tutorial)

Path A — Spectrum replication (images): any blocker above the desired band is mirrored into baseband after sampling. The image location moves predictably with fs.

Path B — Switching as modulation: clocked switching can mix interferers and clock tones, creating sidebands near fs ± f and other clock-related offsets.

Two fastest discriminators: (1) change fs (images move) and (2) add a temporary pre-limit RC (images drop if folding dominates).

Engineering takeaways

  • OOB spectrum drives risk
  • Images track fs
  • Sidebands track clock plan
  • Pre-limit is leverage

“Higher fs” is not automatically safer. It can relocate replicas and clock-related artifacts into harder-to-filter regions, or place them closer to sensitive in-band areas. A usable fs plan is built around the interference inventory.

Minimum executable fs planning rule

  1. List dominant interferers: DC/DC switching (and harmonics), system clocks, MCU activity bands, RF/LO leakage, cable pickup.
  2. Mark sensitive zones: target passband + a guard region where images/spurs are unacceptable.
  3. Choose fs so the strongest replicas/sidebands land outside sensitive zones and leave room for practical pre-limiting.
Symptom Most likely cause Fast check
In-band “mirror” appears Folding of an out-of-band blocker Change fs → image shifts; add RC pre-limit → image drops
Tones at fs ± f offsets Switching modulation / mixing path Change clock plan or edge strength → sidebands move/scale
Artifact appears only in-system Coupled interferer not present on bench Near-field scan / cable move / grounding change → artifact changes
Figure F4 — Spectrum folding: blocker → in-band image, plus clock spur
Folding / images: sampling transports OOB energy into the band Magnitude Frequency Signal band Blocker Image Signal fs spur sample fold Signal / Image Out-of-band blocker Quick check: change fs (image moves) + add temporary RC pre-limit (image drops).
The “image” is transported OOB energy. If it moves with fs and drops with pre-limiting, folding dominates.

H2-6 · Switch Injection & Charge Dump

Charge injection (charge dump) differs from clock feedthrough: it is the release of switch channel charge and parasitic charge into a hold/sampling node at switching transitions. The result is typically a time-domain pedestal (step) and a longer settling tail that degrades THD/SFDR.

Key impacts (how they show up)

Pedestal error: a step on the held value after a switch event. Often scales with switch sizing, timing, and node impedance.

Settling tail: post-switch residue that takes time to decay; appears as dynamic error and reduces SFDR/THD in wideband cases.

Ron nonlinearity: amplitude-dependent distortion (THD knee) and IMD growth, especially when swing approaches switch linear limits.

Fast discriminator vs clock feedthrough: injection is dominated by time-domain steps + tails; feedthrough is dominated by fs/2fs spurs and edge-coupling tones.

Symptom → root cause → quick experiment

Symptom: held level jumps after switching.

Root cause: charge dump into a high-impedance node (hold cap top plate).

Quick experiment: change non-overlap or drive strength; pedestal amplitude changes predictably.

Symptom: SFDR/THD collapses only at larger amplitude.

Root cause: switch Ron nonlinearity or compression near swing limits.

Quick experiment: sweep amplitude; THD knee position is consistent and shifts with headroom.

Symptom: distortion worsens with faster edges/tighter timing.

Root cause: insufficient timing guardband; more charge dumped during overlap-like intervals.

Quick experiment: widen non-overlap; tail shortens and tones reduce.

Mitigation levers (practical set)

  • Bottom-plate sampling
  • Dummy switch
  • Complementary switches
  • Timing alignment
  • Reduce node impedance
  • Edge control
  • Right-size switch

Selection guidance: prioritize levers that reduce sensitivity at the victim node (impedance and plate selection), then cancel charge (dummy/complementary), and finally optimize timing and edge rate to reduce the energy dumped per transition.

Figure F5 — Time-domain pedestal + settling tail and the charge path
Injection: a step (pedestal) plus a tail that hurts dynamic performance Time domain Level Time Ideal hold pedestal tail switch edge Charge path CLK Switch Hold C sampling node Next stage Cpar charge dump Knobs: non-overlap · edge rate · drive strength
If pedestal/tail changes predictably with timing and drive strength, switch injection is a primary contributor.

H2-7 · kT/C Noise + Settling Budget

kT/C noise is a sampling-capacitor floor: smaller C raises the thermal noise on the sampled node, which can become an in-band noise floor. Increasing C lowers kT/C, but makes settling and drive burden harder—often converting “looks fine in magnitude” into real dynamic error (THD/SFDR loss).

Three budgets that must agree

  • Noise floor
  • Settling
  • Dynamic range

Noise budget: C ↓ → kT/C ↑ → in-band floor rises (SNR/ENOB drops).

Settling budget: C ↑ → node time constant / required drive increases; residual error becomes distortion-like.

Dynamic range: large signals stress headroom and linearity; insufficient settling shows up as amplitude-dependent error.

A common trap: magnitude response can look correct while time-domain settling is not. Residual settle error turns into THD/SFDR degradation in sampled systems.

Minimum executable sizing workflow

  1. Set an acceptable in-band floor: decide what “noise headroom” must be preserved versus signal level and required SNR.
  2. Choose a C lower bound: avoid kT/C dominating the band floor (especially when source impedance is high).
  3. Verify settling margin: check large-step settling and SFDR/THD versus amplitude; if the error scales with amplitude or edge timing, settling is limiting.
Observed behavior Likely limiter Fast confirmation
Flat floor rises with smaller C kT/C noise dominates Increase C or reduce bandwidth → floor drops
THD collapses mainly at larger amplitude Settling / dynamic error Sweep amplitude; improve drive / reduce source-Z → THD improves
Spurs/floor change with timing/edge strength Transition-driven error Change non-overlap / edge rate → tail/spurs scale predictably
Figure F6 — The C dilemma: kT/C floor vs settling/drive difficulty (sweet zone)
Sampling capacitor sizing: noise down vs settling/drive up Cost / risk C kT/C floor C ↑ → noise ↓ Settling / drive C ↑ → harder Sweet zone Noise Settling Power THD/SFDR
Larger C reduces kT/C but increases settling and drive burden. The best region is where both budgets meet margin.

H2-8 · Gm Drift, PVT, and Tuning Loops

In Gm-C filters, gm is not a constant. Temperature, process corners, supply/headroom, and operating point shift gm, which directly shifts fc/Q and can move the distortion boundary. Tuning loops can restore spec, but add new failure modes: injected tones (spurs), quantized tuning steps (fc jitter), and loop bandwidth tradeoffs.

Why gm moves (field-facing view)

Temperature: gm(T) drift shifts fc and can change linearity margin.

Process corners: board-to-board spread causes fc/Q dispersion without trim.

Supply / headroom: Vds/Vov shifts alter gm and compression behavior.

Operating point: Vcm and signal swing move gm and CMFB constraints.

Practical symptom mapping: fc drifts with temperature → gm(T). Large unit-to-unit fc scatter → PVT spread. THD knee moving with supply/headroom → gm compression/headroom.

Tuning loops: benefits and new pitfalls

Pitfall What it looks like Mitigation direction
Tuning tone injection Structured spur near tone/clock-related offsets Windowed calibration, isolate tone path, reduce leakage
Quantized tuning / measurement noise fc “micro-jitter” → skirt / wandering spur Hysteresis/deadband, averaging, quieter estimation
Loop bandwidth tradeoff Too slow: cannot track drift; too fast: noise imprinting Set BW for drift timescale; keep stability margin

Manufacturability: meeting fc/Q over PVT

  1. Factory trim: correct initial spread across process corners.
  2. OTP/EEPROM parameters: store per-unit tuning codes for consistent bring-up.
  3. Optional in-field self-cal: track temperature/aging using controlled windows to avoid spurs.
Figure F7 — gm vs temperature/PVT and the effect of tuning (spread → alignment)
gm drift and tuning: without tuning spreads, with tuning aligns (with new risks) gm vs Temp gm Temp SS TT FF tune Spread vs Alignment without tuning fc/Q spread with tuning spec aligned New risks from tuning tone spur fc jitter loop BW tradeoff
Tuning reduces PVT spread but can introduce tone spurs, quantization-driven jitter, and bandwidth/stability tradeoffs.

H2-9 · Linearity & Dynamic Range Limits

Linearity failures in SC and Gm-C chains leave recognizable fingerprints: the THD/SFDR curve versus amplitude bends differently for gm compression, swing/CMFB saturation, slew/drive limits, switch Ron nonlinearity, and sampling-capacitor drive transients. The fastest path is to separate mechanisms with a small set of “knob sweeps.”

Gm-C / OTA: where linearity breaks first

gm compression: distortion rises early with amplitude; sensitive to operating point (Vcm/bias) and temperature.

Swing / CMFB saturation: a sharp “knee” near a specific level; moving Vcm/headroom shifts the knee strongly.

Slew / drive limit: distortion grows faster at higher frequency or faster edges; looks like a smooth upward bend rather than a hard clip.

SC: dominant limits to watch

Switch Ron nonlinearity: distortion grows with amplitude and depends on node voltage; Vcm changes can shift the whole curve.

Sampling-cap drive transient: fs, effective C, and source impedance set the burden; higher fs can bring an earlier THD/SFDR knee.

Fingerprint idea: a “hard knee” often points to swing/CMFB saturation; an “early knee” that moves with Vcm/temp often points to gm or Ron; a “frequency-sensitive bend” often points to slew/drive/transient limits.

Fast isolation with four knob sweeps

Knob If the curve changes like this… Most likely limiter Next move
Amplitude Very sharp knee at one level Swing / CMFB saturation Adjust Vcm/headroom; check output CM control margin
Common-mode (Vcm) Knee shifts strongly with Vcm CMFB / swing limit or Ron operating point Re-center Vcm; reduce node voltage stress; verify CM range
Temperature Distortion slope changes with temperature gm compression or Ron nonlinearity Review bias/headroom; verify PVT margin and calibration strategy
Sampling rate (fs) Higher fs worsens THD at same level Drive transient / settling / dynamic limit Reduce burden (C, Zsrc); increase drive; relax edge/timing if possible
Figure F8 — Distortion fingerprints: THD vs amplitude (typical knees)
THD vs Amplitude: different mechanisms bend the curve differently THD Amplitude gm CMFB knee slew R_on Vcm shift Knobs Amplitude Vcm Temp fs
A hard knee suggests swing/CMFB; an early knee that shifts with Vcm/temp suggests gm or Ron; a frequency-sensitive bend suggests slew/drive limits.

H2-10 · Clock Quality, Jitter, Spurs & EMI

Clock issues show up as two different families: jitter tends to become a noise-like degradation that worsens for higher-frequency or higher-slope signals, while spurs are discrete tones created by clock generation, routing, switching activity, or calibration/tuning. Treat the problem as a spur budget stack, with explicit observability at each layer.

Jitter (engineering intuition)

Higher frequency / steeper slope → more sensitive to sampling time error → noise-like performance loss.

Fingerprint: SNR/SFDR degrades as input frequency rises, without a single fixed dominant tone.

Spur sources: minimum checklist

  • PLL (frac-N)
  • Dividers
  • Gating glitches
  • Digital crosstalk
  • Ground bounce
  • Routing reflections
  • Tuning leakage

EMI / coupling paths (what to control)

E-field coupling: clock edges capacitively couple into high-impedance sampling/REF nodes.

H-field coupling: large loop areas in clock/power return inject magnetic coupling into analog loops.

Common impedance: shared supply/ground impedance converts digital current into analog voltage noise.

Minimum countermeasures: manage edge rate, isolate clock/analog supply domains, enforce keepout near sampling/high-Z nodes, and plan continuous return paths.

Minimum executable countermeasures

  1. Edge control: avoid unnecessarily fast edges; use controlled drive / series damping where appropriate.
  2. Domain isolation: separate clock/digital and analog power; reduce shared return impedance.
  3. Keepout: route clocks away from high-Z sampling/REF nodes; keep sensitive nodes compact.
  4. Return planning: continuous reference planes and short, closed return paths; avoid split-plane surprises.
Figure F9 — Spur budget stack: gen → routing → switching → tuning (with observability)
Spur budget stack: locate the layer by checking the right observation point Clock gen PLL · frac-N · dividers obs: PLL out obs: div node Routing fanout · reflections · crosstalk obs: Rx pin obs: cable Switching gating · ground bounce · digital activity obs: PWR obs: state Tuning tone leakage · code updates obs: window obs: code Observed spur at output node measure here Tools Spectrum Scope Near-field Change one layer at a time.
Treat spurs as a layered budget: identify whether they originate in generation, routing, switching activity, or tuning—then verify at the layer’s observation point.

H2-11 · Layout & Isolation Playbook

SC and Gm-C filters are often “correct on paper” but fail on the board because the most sensitive nodes are high-impedance, clock-referenced, and easily contaminated by return currents. A practical layout playbook treats clock, sampling, bias, and reference as separate noise domains with explicit keepouts and controlled return paths.

Goal: suppress spur paths Goal: prevent folding via coupling Goal: keep tuning/bias quiet

SC (Switched-Cap) — Must do

  • Ring-fence the sampling node: shortest trace, no test pads, no via stubs; treat as “RF-like” even at kHz–MHz.
  • Bottom-plate discipline: route bottom-plate (or the quieter plate) with the tightest return loop; keep the top-plate away from clocks.
  • Non-overlap clock + edge control: slow the edge at the victim node (series R at the driver / buffer output) to reduce capacitive injection.
  • Guard/shield where impedance is high: guard ring to analog ground around high-Z nodes; keep clock traces out of the guard “moat.”
  • Return path is part of the signal path: explicitly plan where clock currents and digital burst currents return; avoid sharing with the analog reference loop.

SC — Optional (high leverage when spurs are stubborn)

  • Local clock buffer island: buffer close to the SC block, then route short, symmetric clock lines into the core.
  • Clock “keepout rectangle”: a no-routing box around sampling capacitors / virtual nodes; enforce in PCB rules.
  • Ferrite bead segmentation: split noisy digital rail from quiet analog rail (only if stability/PDN is verified).

SC — Absolute do not

  • Do not route clocks in parallel to high-impedance analog traces (even if spacing “looks ok”).
  • Do not place ESD parts with large capacitance directly on high-Z analog inputs unless the capacitance is confirmed.
  • Do not share a long, skinny analog ground return with clock driver ground (ground bounce becomes clock feedthrough).

Gm-C — Must do

  • Make the filter truly differential: matched routing, symmetric surroundings, and equal parasitics to both sides to cancel common-mode injection.
  • Keep CMFB loop compact: place CMFB RC and sense nodes tight; long CMFB loops convert supply/clock noise into distortion.
  • Quiet biasing: bias/reference decoupling directly at the pins (multiple caps, shortest loop), with a clearly defined “quiet return.”
  • Thermal symmetry: keep heat sources (DC/DC, PA, MCU) away or symmetric; gm drift + gradient shows up as fc/Q drift and IMD.

Gm-C — Absolute do not

  • Do not place digital clock generators/MCU crystal near OTA input pairs or CMFB nodes.
  • Do not let tuning DAC/ADC references share the same return segment as the OTA bias return.

Example material list (MPNs) — layout/isolation enablers

MPNs below are practical examples to make the playbook executable. Electrical values still need design-specific sizing.

Function Example MPN Where it helps Selection notes (field-minded)
Ultra-low-C ESD clamp Nexperia PESD3V3C1BSF Protect sensitive lines without killing bandwidth Prioritize diode capacitance (sub-pF class) and placement at the connector, not on the high-Z internal node.
Clock buffer (local island) TI CDCLVC1102 Reduce long clock routes; enable series-R at source Place close to the SC/Gm-C block; keep input clock quiet; add local decoupling with the smallest loop.
Series damping resistor Vishay CRCW040222R0FKED Edge-rate control to reduce injection & ringing Put at the driver/buffer output; start 10–33Ω typical and tune by looking at spur amplitude vs edge.
Thin-film precision resistor Vishay TNPW040210K0BEED Bias networks / ratios that must not drift Use for ratio-critical or temperature-sensitive nodes (OTA bias, CMFB RC) to reduce drift-induced spec escapes.
C0G/NP0 “quiet” capacitor Murata GRM1555C1H101JA01D (100pF) Timing/comp nodes; reference filtering with low distortion C0G is preferred where capacitance linearity matters (distortion/IMD) and for temperature stability.
Local decoupling MLCC Murata GRM155R71C104KA88D (0.1µF) Bias/reference pins; clock buffer supply Use multiple values (e.g., 0.1µF + 1µF) and place to minimize loop area; verify anti-resonance in PDN.
Ferrite bead (rail segmentation) Murata BLM18AG601SN1D (600Ω@100MHz) Split noisy digital rail from quiet analog rail Beads can create supply impedance peaks; always validate with step-load and spur scan (H2-12).
Ferrite bead (alternative) TDK MPZ1608S601A (600Ω class) Same purpose with different DC/I characteristics Pick by impedance curve + DC current + DC resistance; avoid “one bead fits all.”
Low-noise analog LDO TI TPS7A20 (family) Quiet bias/reference rails Use an LDO that keeps PSRR where spurs exist; place input/output caps per datasheet; watch stability with beads.
Ultra-low-noise LDO ADI LT3042 Best-in-class noise/PSRR rails for tuning/bias Helpful when tuning loops inject tones; still requires layout discipline (short returns, thermal plan).
Figure F10 — Practical PCB zoning: keepouts, returns, and “quiet loops”
Top View (Principle Sketch) Analog Core SC / Gm-C filter Clock Island PLL / buffer / routing rules Digital / MCU Burst currents / GPIO Bias & Reference Quiet decoupling + short returns Power Entry / DC-DC (keep far) KEEP-OUT Sampling / High-Z short + symmetric separate return quiet loop Analog boundary Keepout Return planning
Layout intent: isolate the sampling/high-Z region, keep clock routing short and symmetric, and prevent digital return currents from sharing the “quiet loop” used by bias/reference and the filter core.

H2-12 · Validation & Production Checklist

A SC/Gm-C design is “done” only when spurs, folding/images, drift, and large-signal distortion are bounded across temperature, supply perturbations, and layout variants. A validation plan must intentionally excite the coupling paths that create field failures, then turn each failure signature into a repeatable production screen.

Bench validation — tests that catch the real killers

Test Setup / stimulus What to measure Failure signature → fix entry point
Spur scan
(fs, 2fs, sidebands)		 Run nominal clocking. Sweep input tone in-band. Repeat with clock edges altered (series-R variants). Spur amplitude at fs harmonics and at fs±fin / sidebands. Spurs track edge-rate → layout/clock routing & source damping (H2-11).
Spurs track supply ripple → rail segmentation / LDO / return path (H2-11).
Folding / images Inject a strong out-of-band interferer (near DC/DC, clock, RF). Vary fs. In-band appearance of mirrored components and “new” tones. Images move with fs → sampling/folding issue; tighten pre-limit band or change fs plan (H2-5).
Images insensitive to fs → likely coupling/EMI path (H2-10/H2-11).
THD/SFDR fingerprint Amplitude sweep (small→large) at several frequencies; vary Vcm and temperature. THD vs amplitude curve shape, knee location, intermod products. Knee shifts with Vcm → OTA/CMFB headroom limit (H2-9).
Knee shifts with fs/edge → SC injection/settling (H2-6/H2-7).
Drift & warm-up Temp sweep (cold→hot). Include “power-up warm-up” dwell tests. fc/Q vs temperature; time-to-stable at each temp. Drift monotonic → gm PVT + thermal gradients; improve symmetry and tuning strategy (H2-8/H2-11).
Drift noisy/jittery → tuning loop spur/jitter coupling (H2-8/H2-10).
PSRR / supply injection Modulate analog rail (sine ripple) and digital rail separately; repeat. Spur rise / noise floor lift vs ripple frequency. Sensitive to digital rail → return path contamination; isolate domains (H2-11).
Sensitive to analog rail → LDO/cap loop and bead resonance (H2-11).
EMI near-field scan Scan around clock routes, sampling node boundary, and DC/DC loop under worst-case mode. Hot spots that correlate with spur rise or noise floor lift. Hot spot on clock island edge → tighten keepout + shield/ground stitching (H2-11).
Hot spot at DC/DC loop → move/contain power stage (H2-11/H2-10).

Example lab material list (models / MPNs)

Examples to make the checklist executable; equivalent instruments are acceptable.

  • Near-field probes: TekBox TBPS01 (H/E probes for EMC pre-compliance)
  • Spectrum analyzer (budget/mid): Siglent SSA3021X Plus / R&S FPC1000 / Rigol DSA815
  • Oscilloscope: any 2+ GS/s class scope with FFT + deep memory (example family: Keysight DSOX1102G)

Production screening — turn validation into repeatable factory gates

  • Golden clock profile: lock edge-rate, drive strength, and routing variant; production must not “silently change” clock trees.
  • Spur-at-markers test: measure at a small set of fixed bins (fs, 2fs, known sidebands) with defined pass/fail limits.
  • Quick THD point: one or two amplitude points that sit near the expected “knee” to catch headroom/settling regressions.
  • Thermal spot check: at least two temperatures (cold/hot) or a controlled heat soak to catch tuning loop instabilities.
  • Calibration traceability: store trim codes + measured fc/Q/THD markers in non-volatile memory; include board ID + timestamp in logs.
Figure F11 — Validation-to-production pipeline (what gets measured, where it gets logged)
From Bench Proof → Factory Gate → Field Evidence Stimulus tone + interferer fs sweep / edge variants DUT SC / Gm-C filter clock + tuning loops Measurement spectrum / FFT / markers spur + THD + noise floor Environmental Stress temperature sweep / warm-up supply injection (analog vs digital) near-field scan (hotspot correlation) Factory Gate fixed bins: fs / 2fs / sidebands quick THD point near “knee” store trim codes + markers Logs / Traceability board ID · clock profile · trim code · fc/Q markers · spur markers · THD markers · temp point field symptom mapping: “spur rise” / “noise floor lift” / “fc drift” → layout or tuning fix entry
The same signatures that prove robustness in the lab must be reduced to fixed, fast production markers and stored as traceable logs so a field return can be mapped back to a specific coupling path or tuning instability.

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H2-13 · FAQs (SC / Gm-C Caveats)

These FAQs focus on field signatures—spurs, images, drift, and sudden distortion collapse—and give minimal, repeatable discriminator tests. Each answer points to a specific fix entry (clock path, switching injection, tuning loop, layout isolation, or production markers) without expanding into unrelated filter topologies.

Spurs & feedthrough Folding vs IMD kT/C vs settling Drift & tuning ATE & logs
1) Why can spurs look worse after switching to a lower-noise clock source?

Lower phase noise can reduce the broadband skirt that previously “masked” discrete spurs, so the same spur becomes more visible. Also, a new clock source may introduce different fractional-N tones, divider artifacts, or ground/rail coupling paths. A fast discriminator is to compare spur height versus noise floor at identical fs, then toggle clock modes (spread-spectrum, gating, divider settings) and see whether the spur tracks configuration changes.

Fix entry: Clock feedthrough (H2-4) + Spur sources/clock quality (H2-10).

2) An SC filter is clean on the bench, but shows fixed “needle” tones in the system. What coupling path is most common?

The most common path is capacitive clock coupling into a high-impedance sampling node (or its reference/virtual node), followed by conversion into a differential error via parasitic mismatch. Second is common-impedance coupling: clock driver return currents share a segment with the “quiet loop.” A minimal test is to slow the edge at the clock driver (e.g., add a source series resistor), move/rotate cables, and compare spur sensitivity to physical proximity and return routing.

Fix entry: Feedthrough path taxonomy (H2-4) + Layout keepouts/returns (H2-11).

3) An in-band “image tone” appears. How to quickly tell folding/aliasing from intermodulation (IMD)?

If it is folding/aliasing, the tone’s frequency placement typically moves when fs changes (even if the analog chain is unchanged), because sampling maps out-of-band energy into baseband. If it is IMD, the tone placement depends more on input amplitude and operating point (common-mode, temperature, headroom) than on fs. The fastest discriminator is a two-step A/B: change fs first, then change input amplitude—observe which action moves or strengthens the artifact.

Fix entry: Folding/images (H2-5) vs Linearity fingerprints (H2-9).

4) Non-overlap clocks are used, but pedestal/step error is still obvious. Why?

Non-overlap prevents direct short-through, but it does not remove charge injection and asymmetric switch charge dump. Pedestal error usually comes from device charge being pushed into the sampling capacitor or the high-Z node during turn-off, especially with strong clock edges, large switch devices, or bottom-plate strategy that is not truly “quiet.” A quick test is to vary clock edge rate (series-R) and switch drive strength: pedestal amplitude typically tracks those changes more strongly than true feedthrough does.

Fix entry: Switch injection & charge dump (H2-6).

5) Why does reducing the sampling capacitor raise the noise floor but sometimes improves THD?

Smaller sampling capacitors increase kT/C noise (raising the in-band floor), but they also reduce the instantaneous charge the driver must deliver, improving settling and reducing transient-induced distortion. In many systems, THD is dominated by incomplete settling or driver nonlinearity under heavy charge demand rather than by small-signal noise. A clean discriminator is to compare the THD knee location versus capacitor value and to check whether THD improves more at higher frequencies or higher fs (settling-limited cases).

Fix entry: kT/C + settling budget (H2-7) and distortion fingerprinting (H2-9).

6) Gm-C cutoff drifts with temperature. Should debugging start at bias or the tuning loop?

Start from the signature. If fc/Q drifts smoothly and monotonically with temperature, bias/PVT and thermal gradients are primary suspects. If fc/Q “jitters,” jumps, or shows a sawtooth pattern, the tuning loop update quantization, tone injection, or loop bandwidth is often dominant. A minimal discriminator is to freeze tuning updates (or hold the calibration code) during a temperature dwell and observe whether the drift becomes smooth and predictable.

Fix entry: Gm drift, PVT, and tuning loops (H2-8).

7) What does a tuning-tone–induced spur spectrum typically look like, and how to keep it out of band?

Tuning-tone spurs often appear as a strong discrete line at the tone (or its harmonics) plus sidebands created by sampling/mixing with clocks or signal content. The pattern frequently tracks the tuning update cadence and can “walk” when the tone frequency or update rate changes. Mitigation starts with tone placement (choose frequencies far from passband and critical bins), reduce coupling (quiet bias/reference domain), and control update scheduling (avoid in-band windows). Verify by sweeping the tone frequency and observing whether spurs move in lockstep.

Fix entry: Tuning loop mechanisms (H2-8) + spur stack/clock coupling (H2-10).

8) THD suddenly “collapses” at one input amplitude. Is it gm compression or CMFB saturation?

CMFB saturation and headroom limits often produce a sharp knee and strong sensitivity to common-mode voltage and supply voltage. Gm compression typically shows a softer, earlier nonlinearity that shifts with bias and temperature. The fastest discriminator is to repeat the amplitude sweep while stepping common-mode and supply headroom: if the knee moves strongly with Vcm or rail, CMFB/swing is likely. If it moves mainly with temperature or bias settings and looks gradual, gm compression is more likely.

Fix entry: Linearity & dynamic range limits (H2-9).

9) Slowing clock edges reduces spurs, but bandwidth/noise worsens. How to balance?

The practical goal is to reduce edge energy at the victim node only as much as needed to meet spur targets, then confirm settling and noise budgets. Use source-side damping (e.g., 10–33Ω series resistors such as Vishay CRCW040222R0FKED) at the clock buffer output rather than adding RC at the sensitive node. Sweep a small resistor ladder and record spur amplitude and in-band SNR/THD markers—choose the smallest edge slow-down that clears the spur margin without degrading settling.

Fix entry: Clock quality/spurs/EMI (H2-10).

10) Why doesn’t a differential structure always cancel clock feedthrough?

Differential cancellation works best for symmetric common-mode injection. In practice, parasitic mismatch (layout asymmetry, unequal coupling capacitances, unequal return impedances) converts common-mode injection into differential error. Common-impedance coupling is especially harmful: if one side shares more noisy return path than the other, differential error appears even with a differential signal path. A minimal check is to inspect symmetry around the sampling/high-Z boundary and verify return paths with near-field probing or controlled rerouting of the clock.

Fix entry: Feedthrough mechanisms (H2-4) + Layout symmetry/keepouts/returns (H2-11).

11) How to design a minimal ATE test set that covers spurs, drift, and linearity?

Reduce each risk into fast “markers.” For spurs: measure a fixed set of FFT bins (e.g., at fs, 2fs, and known sideband locations) under a golden clock profile (a local buffer such as TI CDCLVC1102 can help keep routing consistent). For drift: add two-point thermal stimulus (cold/hot or controlled heat soak) and log fc/Q markers. For linearity: test one small-signal point plus one point near the expected THD knee. Store trim code + markers into NVM for traceability.

Fix entry: Validation & production checklist (H2-12).

12) In the field, how can logs/self-test pinpoint “temperature drift moved fc out of spec”?

Log only the minimal evidence needed to reproduce the signature: temperature, clock profile ID, tuning/trim code, and a small set of spectral or magnitude markers that correlate with fc/Q (plus a timestamp and firmware version). Trigger logging on threshold crossings rather than continuously to avoid log explosion. If drift is tuning-loop driven, markers often change in steps synchronized to update cadence; if it is bias/PVT driven, drift is smoother and monotonic with temperature. Store CRC-protected codes and include “last-good” markers for postmortem comparison.

Fix entry: Field evidence, factory markers, and traceability (H2-12).

Figure F12 — Fast discriminator map: spur vs image vs drift vs distortion
Field Signature → Minimal Test → Likely Mechanism → Fix Entry Spur “needle” fixed frequency tones often near fs bins Minimal test edge-rate A/B clock mode toggles Fix entry H2-4 / H2-10 H2-11 (returns) “Image tone” mirrors appear in-band looks like alias/IMD Minimal test change fs then change amplitude Fix entry H2-5 (folding) H2-9 (IMD) Drift / jitter fc/Q moves with temp or steps with updates Minimal test freeze tuning updates temp dwell comparison Fix entry H2-8 (tuning) H2-12 (logs) Rule of thumb: If it tracks fs → suspect folding; if it tracks amplitude/Vcm → suspect IMD; if it tracks edge/clock mode → suspect spur path.
Use a minimal A/B test (change fs, amplitude, clock edge, or tuning updates) to isolate the dominant mechanism before applying layout or tuning fixes.
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