• Quick check: confirm whether the spur tracks fCLK (SC) or moves with bias/temperature (Gm-C).
• Typical root: clock feedthrough / folding (SC) or Gm drift / nonlinearity (Gm-C).
• Where it is solved: tuning architecture + clock/EMI hygiene + calibration hooks (later chapters).

• Quick check: lock gain (disable AGC) to see whether the issue disappears; then adjust attack/release to observe sensitivity.
• Typical root: time constants vs group delay, detector bandwidth, and step-gain strategy (hysteresis, dwell, mute-settle).
• Where it is solved: AGC/PGA co-design + switching state machine (later chapters).

• Quick check: inject a single tone and track image level across modes; verify I/Q symmetry at the same observation node.
• Typical root: gain/phase/group-delay imbalance or DC offsets that change with mode.
• Where it is solved: I/Q matching strategy + phase/group-delay control + calibration (later chapters).

Focus on RF baseband analog: tunable Gm-C/SC filtering, AGC/PGA gain plans, I/Q consistency, spur management, and calibration/production hooks that keep modes repeatable.

• No RF front-end deep dive (LNA/PA/mixer/PLL/VCO/antenna).
• No “standard encyclopedia” (LTE/NR/Wi-Fi tables and protocol specifics).
• No DSP filter design textbook; only analog–digital partition rules.
• No ADC architecture/jitter theory beyond interface-level constraints.

Use these pages for module-level theory and implementation details (this page stays system-level and test-driven):

• Anti-alias / anti-blocker shaping that prevents ADC overload.
• Mode-repeatable gain and bandwidth (tuning + calibration hooks).
• I/Q symmetry basics (matching, stable VOCM/CM behavior in the chain).

• Residual fine shaping after the ADC (when analog shape is stable across modes).
• Adaptive compensation that relies on repeatable analog observations.
• In-field updates when coefficients remain stable and testable.

• Use when: wide BW, many modes, digital shaping is available after the ADC.
• Analog must own: first anti-blocker shaping + mode-repeatable gain/BW so DSP sees a stable plant.
• Tunable knobs: coarse BW steps + fine trim, segmented gain (PGA steps + small VGA range).
• Main risk: analog becomes too “thin”, letting blockers create IMD that DSP cannot remove.
• Quick check: under a blocker, verify IM3 growth is not dominated by the first active stage.
• Pass criteria: repeatable BW/phase per mode; blocker IMD margin meets system budget (X/Y/Z).

• Use when: narrowband operation, tight power budget, low latency or limited digital correction.
• Analog must own: deeper stopband and lower in-band noise density; fewer “moving parts” after the ADC.
• Tunable knobs: repeatable steps (often SC/digital), limited gain steps with stable settling.
• Main risk: higher order/Q increases settling time and makes mode switching slower than expected.
• Quick check: measure switch-settle time per mode using the same observation points (P1–P3).
• Pass criteria: settle within T ms; phase/group delay ripple stays within budget (X/Y).

• Use when: strong blockers, high IMD sensitivity, fast recovery is mandatory.
• Analog must own: headroom and overload recovery before deep filtering; prevent first-stage compression.
• Tunable knobs: segmented gain early + conservative filter peaking; optional soft limiting.
• Main risk: protection/limiting introduces distortion or phase asymmetry between I and Q.
• Quick check: compare small-signal THD and blocker-driven IMD; verify recovery time after overload.
• Pass criteria: IMD under blocker meets margin; recovery < T ms; image leakage stable across modes.

• Front-end overload is irreversible: a saturated first stage produces IMD that downstream tuning cannot remove.
• Noise budget collapses: late gain changes amplify upstream noise and SC folding artifacts.
• I/Q symmetry breaks: late-stage Q/phase changes often increase I/Q group-delay mismatch.
• Switching becomes slow: concentrating high order/high Q at the end increases mode-switch settling time.

• BW/f0: place the primary BW control early enough to gate blockers before they compress later stages.
• Gain: use segmented gain (coarse PGA + fine VGA/AGC) to avoid dithering between steps.
• Order/shape pressure: distribute order across stages; avoid a single “last-stage wall”.
• Q/peaking: keep high-Q knobs only where calibration and I/Q symmetry are enforceable.

Gm-C is strong when BW must sweep continuously across modes. Repeatability requires a defined calibration target (f0/Q/gain) rather than “best effort tuning”.

The tuning element (Gm) also sets noise and linearity. A platform budget should assign which stage owns input-referred noise to avoid over-spending power downstream.

Under blockers, Gm nonlinearity and headroom become dominant. If IMD under blockers is critical, linearity must be designed and verified at the same mode settings used in the field.

Gm varies with process, bias, and temperature. A baseband product needs a plan for coefficient storage and in-field re-tuning (coarse+fine), not a single factory trim.

Gm-C becomes “production-grade” when a measurable loop exists (frequency/phase detection or injection+measurement) with clear pass criteria for repeatability.

• Moves BW/f0 close to target quickly (coverage).
• Defines the mode identity (repeatable codebook).
• Reduces search time for fine calibration.

• Corrects process/temperature drift to restore the same response every time.
• Targets measurable quantities: f0, Q, gain, or a proxy metric that correlates with them.
• Stores coefficients (EEPROM) with versioning and optional re-trim conditions.

Detect a frequency proxy (internal tone/oscillator/response marker), count against a reference clock, then adjust Gm to reduce error.

Lock a phase/frequency metric to a reference. Useful when the platform already has stable clocks and needs fast re-lock after mode changes.

Inject a known tone (or sweep segment), measure amplitude/phase markers, then update trim coefficients. Best accuracy, heavier test burden.

• Likely: Gm drift or bias sensitivity.
• Check: track f0/BW error vs temperature at the same mode code.
• Action: enable fine closed-loop trim and store coefficients per mode.

• Likely: Gm nonlinearity/headroom limitation.
• Check: two-tone IM3 vs amplitude at the same tuning state.
• Action: increase headroom, linearize Gm, or shift blocker ownership earlier in the chain.

• Likely: parasitic coupling into bias/control nodes.
• Check: change digital activity/clocking and observe response jumps at P1.
• Action: tighten bias routing, shielding, and separation; validate with the same switching sequence.

Bandwidth is anchored by the clock. Treat every mode as a codebook entry (clock + filter code + gain code) that must be reproducible in production and in-field.

On-chip capacitor ratios provide stable shapes across modes. That stability is only useful when clock coupling is kept out of the sensitive band.

SC is a clocked system. Folding noise and injection can look like “mysterious baseband noise” unless identified by frequency movement when the clock changes.

• Use a mode table: BW ≈ fCLK / K (K depends on order/implementation).
• Keep K from a small validated set to control verification and switching time.
• Store per-mode: fCLK, filter code, gain code, trim version.

• Avoid small-integer relationships between fCLK and platform clocks (ADC sampling / decimation / I/Q control clocks).
• Prioritize: keep any beat component out of the sensitive baseband for every mode.
• Use buffered, documented dividers so each mode is traceable to a reference.

• Assign a per-mode jitter budget: jitter_rms < J(mode) (platform-defined).
• Verify in the worst mode: highest gain and most sensitive BW/shape.
• When in doubt, test by stepping fCLK and checking if the “noise issue” moves with it.

Step fCLK slightly. If the spur shifts in frequency with the clock, clock feedthrough / edge coupling is the primary suspect.

Toggle interface/logic activity. If the spectrum changes without changing input signal, suspect supply/ground return or bias-node coupling.

A broad noise-floor lift points to folding noise / sampling artifacts. Narrow peaks point to coupling spurs and should be traced by clock movement tests.

Compare I and Q amplitude/phase markers after mode switching. Large mode-dependent mismatch signals clock domain skew, asymmetrical coupling, or mismatched update timing.

• Risk: magnitude/phase template changes, group-delay ripple jumps, I/Q mismatch.
• Measure: P1 markers (filter output) vs mode template.
• Control: update I and Q with deterministic timing; avoid asymmetrical routing of control lines.

• Risk: peaking/overshoot, long settling time, mode-dependent stability margins.
• Measure: settling signatures at P2 after a controlled step change.
• Control: guard times and verified ramp/step sequences (avoid changing fc and gain simultaneously).

• Risk: saturation during transitions, slow overload recovery, “pumping” when control dithers near thresholds.
• Measure: P3 headroom and recovery at the ADC input under worst-case switching.
• Control: segmented gain plan, hold/blanking windows during transitions.

• MUTE to prevent transient overload.
• SWITCH codes deterministically (I/Q sync).
• SETTLE for the slowest element in the mode.
• VERIFY against a minimal mode template.
• RUN only after template passes.

• BW / fc marker
• Gain marker
• Image leakage / I-Q mismatch marker
• In-band spur marker (clock-related)

mode_id · fCLK · filter_code · gain_code · trim_version · temperature · supply · timestamp. This is enough to reproduce most “mode-only” failures without a full demod stack.

P1 (filter out) for BW/phase template · P2 (gain stage out) for settle dynamics · P3 (ADC in) for headroom/IMD/recovery.

• Best when: fast overload prevention is critical and chain group delay is large.
• Main risk: detector error maps directly into gain error (mis-compression).
• Measure: compare detector output vs P3 headroom during fast bursts.

• Best when: steady-state accuracy and repeatability dominate.
• Main risk: chain delay (filter group delay + detector bandwidth) eats stability margin → pumping.
• Measure: look for low-frequency gain ripple and slow recovery at P2/P3.

• Best when: both fast protection and accurate settling are needed across modes.
• Main risk: two paths “fight” unless the control bandwidths are separated.
• Measure: confirm the fast path only handles overload, while the slow path owns steady-state.

Attack should prevent P3 overload on worst-case bursts, but not react so fast that it modulates desired amplitude variations. Verify by injecting a controlled burst and checking that peak clipping disappears without creating low-frequency gain ripple.

Filter group delay and detector bandwidth add phase lag. If the AGC reacts at a comparable timescale, gain becomes an oscillating state. Verify by stepping gain demand and checking no ringing in envelope at P2/P3.

Release must be slow enough that short peaks do not cause repeated “gain breathing”, yet fast enough to recover usable range. Verify with a periodic peak train: gain should not track each peak; recovery should meet the platform settle target.

With tunable filters, group delay and peaking can change by mode. Attack/release must either be mode-specific or proven safe for the worst mode.

Use coarse steps to keep VGA/Gm within a linear, low-distortion region across modes. Coarse steps should not chatter: apply hysteresis, minimum dwell time, and hold-off after each step.

Fine gain should correct residual amplitude without forcing frequent step changes. Separate bandwidths: coarse logic acts slowly (range selection), fine loop acts faster but is limited by chain delay.

Apply the same step decision and timing to I and Q. Even small update skew can degrade image rejection and EVM, especially near band edges where group delay ripple is largest.

Envelope shows low-frequency oscillation and repeats even with constant input. Reducing loop bandwidth (slower attack/release) should immediately reduce the oscillation amplitude.

Gain moves even when output level is already correct. Temporarily narrowing detector bandwidth should reduce noisy gain motion without changing the main chain response.

After gain or mode changes, the output takes long to return to a stable template. Increasing hold-off/settle time improves the symptom without changing steady-state gain.

Gain steps back-and-forth around a boundary. Adding hysteresis and minimum dwell time should stop the chatter immediately, while leaving fine gain to maintain target level.

Symptom: image leakage with mostly constant severity across frequency. Isolation: compare I/Q amplitude markers under the same tone or in-band RMS. Fix: symmetric gain coding, matched networks, or stored trim.

Symptom: image leakage and EVM worsen; often frequency-dependent. Isolation: sweep a tone and track I/Q phase difference across the band. Fix: I/Q update synchronization, symmetric routing, and mode-specific correction.

Symptom: image leakage becomes worst near band edges; EVM degrades in a “mode-dependent” way. Isolation: compare phase slope vs frequency between I and Q (multi-point markers). Fix: mode-aware calibration tables; use phase equalization only when constant correction is insufficient.

Symptom: strong low-frequency artifact, LO leakage sensitivity, and baseline shifts across modes. Isolation: measure I/Q averages with a quiet input condition. Fix: DC servo or calibration subtraction; keep offset control consistent across mode transitions.

• Use when: δG or constant δφ is stable and repeatable.
• Workflow: measure → compute correction → store by mode.
• Risk: correction drifts when mode or temperature changes.

• Use when: mismatch is strongly mode-dependent or temperature-dependent (δτ-driven cases).
• Workflow: inject markers → readback → adjust coefficients → verify template.
• Risk: injection path must be isolated from normal traffic and validated per mode.

If image leakage changes sharply with frequency, constant δG/δφ correction is not enough. Phase equalization is warranted only after confirming δτ mismatch and defining a measurable improvement target.

Constant severity across frequency points to δG or constant δφ. Start by matching gain codes and verifying I/Q amplitude markers.

Edge-worst behavior points to δτ (group delay mismatch) or ripple differences between I and Q. Compare multi-point phase slopes.

Strong low-frequency artifacts suggest DC offset or mode-dependent baseline drift. Measure I/Q averages under quiet input and verify DC servo behavior.

If only certain modes fail, suspect mode-dependent filter peaking and delay ripple. Confirm by comparing I/Q phase markers per mode and logging mode_id and clock settings.

Scales predictably with bandwidth. If Rs dominates, adding amplifier power rarely buys much; bandwidth and impedance strategy become the primary levers.

en tends to dominate at low Rs; in·Rs tends to dominate at high Rs. In baseband, the gain plan determines how much later stages matter after input-referencing.

Dominates near DC and low-frequency bins, often interacting with DC servo and calibration strategy. Treat it as a separate budget line for low-BW modes.

Noise, linearity, and power are tightly linked. If a mode requires high blocker tolerance, bias may rise and the noise budget must remain coherent with the gain plan.

Wideband noise can fold into the passband, and clock feedthrough can raise in-band spurs and apparent floor. Treat folding as a first-class term tied to fCLK-to-BW planning and coupling paths (supply/ground/edge).

If the measured floor stops improving with analog changes, the chain is likely quantization-limited or limited by downstream noise. The gain plan must reclaim full-scale usage without breaking linearity.

Lock BW/ENBW, full-scale/back-off, and the required SNR or EVM margin for that mode. Treat “wide-BW” and “high-blocker” as separate worst cases.

Express the target as an allowable total in-band noise (RMS) at a chosen reference point (input-referred or ADC-referred). Keep one consistent reference per page.

For each block, record gain, bandwidth/ENBW, and its equivalent noise (density or RMS). Include Rs, en/in·Rs, 1/f line, Gm-C/SC terms, and quantization floor.

Convert each stage’s noise to input-equivalent (or ADC-equivalent) using the gains before it. Keep SC folding as a separate contributor rather than hiding it inside an “effective en”.

Use RSS to form total in-band noise, then rank top contributors. The top one or two terms are where power, topology, or clock planning actually moves the result.

Noise should scale with √BW when folding/quantization are not dominant. If it does not, the budget is missing a mechanism (folding, coupling, or floor limits).

Reduce BW (or switch to a narrow mode). If noise follows √BW, wideband terms are not folding-dominant. If it barely improves, a floor or folding term is limiting.

Keep fCLK constant and change the filter bandwidth. If in-band noise changes “too much” or shows spur movement, folding and clock coupling are likely dominant.

Hold BW and sweep fCLK. A repeatable change in floor and spur placement indicates a clock-related folding/coupling mechanism that must be addressed by planning and isolation.

Temporarily bypass a block or freeze a control loop. A step change in the measured floor identifies the dominant stage quickly and prevents wasting power in the wrong block.

Use two tones that place IM products in the passband. Track IM growth and identify which stage creates the rise by measuring at defined taps.

Sweep input level and record where gain deviates from linear. A stable knee location across modes indicates headroom planning; a mode-only knee indicates mode-specific peaking or swing limits.

Apply a controlled overload and measure time to return to the nominal template. Recovery strongly coupled to mode often implicates tunable filters, servo paths, or bias restoration effects.

In baseband, IM products are often unavoidable because they fold into the same band of interest. The design goal is to keep IM below the mode’s in-band margin and prevent stage entry into the non-linear region.

Compression is not only amplitude error; it often drags phase and group delay. Under blockers, preserve headroom so the knee stays outside the operating envelope for each mode.

Many blocker failures are swing or common-mode boundary violations disguised as “distortion.” Keep common-mode control coherent across mode switching and gain stepping so the last stage does not become the limiter.

• Blockers push a stage into deep saturation and recovery becomes the system bottleneck.
• AGC reacts too late to prevent overload in the worst burst case.
• Mode switching plus a blocker causes transient overshoot beyond headroom.

• Passband phase and group delay template (mode-defined).
• In-band distortion budget (THD/IMD) under normal traffic.
• Gain-step coherence with AGC and I/Q synchronization.

Recovery time < T ms · IM products < I dBc · No new spurs above S dBc · Phase template preserved across mode and gain changes

If IM rises while gain remains steady, a stage is entering nonlinearity before AGC action. Measure at taps to find the first point where IM appears.

A knee that shifts with filter mode suggests mode peaking, swing limits, or bias conditions tied to the tunable block. Confirm by repeating the sweep across modes with the same gain plan.

If recovery time increases sharply with overload level, deep saturation is the culprit. Protection that prevents deep saturation should reduce recovery immediately.

If distortion and slow recovery remain with AGC disabled and fixed gain, the dominant issue is analog saturation. If artifacts appear mainly with AGC enabled, the control strategy is the primary target.

• Mirror I and Q layouts: same layer transitions, via counts, and component orientation.
• Keep impedance and coupling consistent; avoid one side “hugging” ground fences more than the other.
• Place matched RC networks and filter capacitors with symmetric return paths.

• Inject VOCM once, keep it short, and shield it from clock/digital edges.
• Use a quiet local decoupling loop for common-mode/bias pins (no shared narrow return necks).
• Prevent contamination-driven leakage: keep high-impedance nodes away from board edges and residue-prone regions.

• Avoid crossing plane splits under differential routes (creates spur injection and phase errors).
• Provide stitching vias to keep high-frequency return loops local to the aggressor.
• Keep clock return loops out of the analog baseband zone.

Clock edges draw pulsed current. If the clock driver shares impedance with analog rails, ripple modulates baseband gain and creates clock-related spurs. Prioritize local decoupling at the clock driver and low-impedance analog rails.

A shared return neck or broken reference plane lets clock return current lift “analog ground.” Keep clock return loops short and fenced; stitch ground near zone boundaries.

Parallel routing between clock traces and high-impedance analog nodes creates capacitive injection. Increase spacing, avoid long parallels, and add grounded shields where needed.

In-band clock spur < Z dBc · No new spur vs fCLK plan changes · I/Q phase template preserved after reroute/shield · VOCM ripple < V mVpp

• Input capacitance and nonlinearity (phase, THD/IMD).
• Extra poles/zeros from RC limiting networks (group delay ripple).
• Return-current path during ESD/surge events (ground lift into analog zone).

• Amplitude/phase/group-delay sweep before vs after protection population.
• Two-tone IMD with and without protection in-circuit.
• Spur map vs fCLK and supply ripple (captures coupling paths).

ADI LT3042, ADI LT3045, TI TPS7A47, TI TPS7A20, Microchip MIC5504

TI LMK1C1102, TI CDCLVC1102, Renesas 5PB1108, NXP 74LVC1G17 (Schmitt buffer)

Murata BLM18AG102SN1, Murata BLM18AG601SN1, TDK MPZ1608S101A, TDK MPZ1608S221A

TI TPD1E10B06, TI TPD2E007, Nexperia PESD5V0S1UL, Semtech RClamp0502B, Littelfuse SP0502BAHT

ADI ADG1209, ADI ADG1409, TI TS5A23157, TI TS5A3359

• Frequency sweep: amplitude / phase / group delay template.
• Two-tone IMD: IM2 / IM3 in-band.
• Noise: in-band noise + scaling checks vs BW and fCLK.
• Overload recovery: recovery time after a defined overload.
• Mode switching: run→mute→switch→settle→verify (I/Q synchronized).
• Temperature re-check: compare templates across temperature points.

• Spur map vs fCLK and supply ripple amplitude.
• I/Q matching: image leakage and phase skew signature.
• Tap measurements at TP1/TP2/TP3 to localize dominant stages.

• Injection tone / two-tone / overload pulse (known templates).
• Loopback path for stable regression (fixture-controlled).
• Defined tap points (TP1/TP2/TP3) to isolate failures quickly.

• Mute and bypass controls to avoid transient saturation during mode changes.
• State machine timing that enforces settle and verify steps.
• I/Q synchronization hooks (shared triggers or aligned update events).

Serial · Lot · HW rev · FW rev · Cal rev · Mode ID · BW · fCLK · Gain step · VOCM setting · PASS/FAIL bin · Failure signature tag

• Image leakage < X dBc (mode-defined).
• Mode switch settling < Y ms (run→mute→switch→settle→verify).
• Clock spur < Z dBc in-band (worst-case fCLK plan).
• Total in-band noise < N RMS at the chosen reference point.
• IM3 < I dBc (two-tone, specified spacing and levels).
• Recovery time < T ms after a defined overload depth.

Microchip 24LC256, Microchip 24AA02, ST M95M02, Winbond W25Q32JV (SPI flash for extended logs)

ADI AD5272, ADI AD5160, TI TPL0102, Microchip MCP41010, Maxim DS3502

ADI ADG1419, ADI ADG1408, TI TS5A9411, TI TMUX1108

Omron G6K-2F-Y, Panasonic TX2SA, TE Connectivity IM03

ADI AD9833 (DDS), ADI AD5683R (DAC), TI DAC60501 (DAC), TI OPA1656 (buffer/driver)