Log/Antilog amplifiers turn “multiplicative” signals into a linear domain so one chain can cover many decades of dynamic range.
Practical success is defined by bottom-decade leakage control, temperature-stable slope/intercept, and a testable decade-fit + recovery plan.
What is a Log / Antilog Amplifier and when to use it
A log amplifier maps a multiplicative input scale (often spanning many decades) into an additive, manageable output scale.
An antilog amplifier performs the inverse mapping, expanding a compressed domain back to a linear domain (or generating an exponential current/voltage from a control voltage).
In practice, many real systems behave more naturally in current (photodiodes, ion/chemical sensors, leakage-dominated nodes), while downstream processing and ADCs are typically voltage-based.
Log/antilog blocks provide a deliberate “domain conversion” that preserves monotonicity across a very wide range.
Use log/antilog when
A sensor spans multiple decades (e.g., nA → mA), but only one ADC range is available.
Ratios matter more than absolute amplitude (e.g., dB, absorbance, concentration relationships).
Compression must remain monotonic across temperature (no fold-back or “dead decades”).
Not a fit when
The goal is true-power equivalence or energy averaging → use RMS-to-DC (sibling page).
The goal is envelope/peak capture or fast limit detection → use Precision Rectifier / Peak Hold.
The goal is range matching via variable gain without logarithmic mapping → use PGA / AGC.
Engineering framing
Specify performance in the log domain: slope (dB/decade equivalent) and intercept drift, not only “linearity.”
Define the usable range by two floors/ceilings: low-end decade (leakage/bias/noise) and high-end (compliance/swing/recovery).
Block view: domain conversion and where it sits in the chain
Core transfer law: exponential devices → log/exp mapping
The log/antilog function is built on devices whose current–voltage relationship is exponential (diodes and BJTs in forward operation).
With an op-amp enforcing a virtual node, the exponential element converts current ratios into voltage differences—exactly what a logarithm does.
Vt (thermal voltage) scales with absolute temperature, so the log “slope” is inherently temperature-dependent.
Practical designs therefore treat slope drift and intercept drift as first-class specs—especially across decades.
What breaks the ideal ln/exp behavior
1) Device terms
Is and n drift → slope/intercept move with temperature.
Series resistance → curvature at the high end (compressed output “bends”).
Quick check: fit slope at mid-range, then compare end-decade residuals for systematic bend.
2) Op-amp terms
Input bias/offset → low-end decade floor and intercept error.
Output swing / recovery → overload “stickiness” and long settling.
Quick check: step to overload, return to a low decade, and time the recovery to within a target residual.
Intuition diagram: exponential device → log-linear behavior in decades
The “straight line” behavior is most reliable in the mid-range. Curvature typically appears at the low end (leakage/bias/noise floors)
and at the high end (series resistance, swing/compliance, recovery). Those end effects define usable decades and drive temperature-compensation strategy.
Practical log/antilog designs rely on exponential devices (diodes or BJTs) plus a structure that enforces a predictable operating region.
Architecture choice is driven by input domain (current vs voltage), the target decades, recovery behavior, and how temperature drift is managed.
Four implementation families cover most real systems: op-amp log (exponential element in feedback), op-amp antilog (inverse mapping),
translinear loops (matched BJT ratio structures), and piecewise / multi-slope approximations (programmable and calibration-friendly).
A) Op-amp Log Amplifier
I → V
Core idea
Input current is forced into an exponential element in the feedback path. The op-amp holds a virtual node, producing a log-voltage output.
Best for
Wide current decades into a bounded voltage swing.
Sensor front-ends where low-end behavior is the limiting factor.
Gotchas
Low-end decade floor set by leakage, bias currents, and contamination.
Overload recovery can dominate if the loop saturates at the ends.
B) Op-amp Antilog Amplifier
V → I / V
Core idea
An exponential element maps an input voltage into an exponential current (or voltage), often used to expand a compressed domain or build exponential control laws.
Best for
Reconstruction / expansion stages after log-domain processing.
Generating exponential currents with bounded control voltage.
Gotchas
Compliance limits: insufficient swing forces curvature at the high end.
Saturation and recovery can create long tails after overload events.
C) Translinear Loop (Matched BJTs)
Ratio domain
Core idea
A matched BJT loop enforces current-ratio relationships. Ratio structures reduce dependence on absolute device saturation current, improving temperature behavior when matching is good.
Best for
Temperature stability with monolithic matching.
IC-friendly implementations where device pairing is controlled.
Gotchas
Matching and thermal coupling dominate performance (layout-sensitive).
Headroom requirements can reduce usable range in low-supply systems.
D) Piecewise / Multi-Slope Log
Programmable
Core idea
The log curve is approximated with multiple linear segments. Segment thresholds and slopes can be designed for calibration and repeatability.
Best for
Calibration-friendly systems and programmable platforms.
Stable mapping when exact log physics is not required.
Gotchas
Segment transitions must stay monotonic (avoid kinks or steps).
End segments still hit leakage floors and compliance limits.
Architecture comparison (selection lens)
Input type
I → VV → I/VRatioProgrammable
Best for
Low-currentSpeedTemp stabilityCalibration
Gotchas
Leakage floorRecoveryComplianceSegment kink
Architecture map (4-panel block view)
Temperature compensation: Vt, Is, matching, and ratio tricks
Temperature drift in log/antilog stages comes from the same root: the exponential device parameters change with temperature.
The thermal voltage Vt scales with absolute temperature, while Is is strongly temperature-dependent and the ideality factor n can vary.
These changes appear as two distinct error modes: slope drift and intercept drift.
A robust design treats slope and intercept as first-class specifications across decades.
Compensation strategy should be chosen based on what dominates the error: device matching, ratio structures, digital calibration, or controllable bias injection.
Problem
Slope drift
The output change per decade shifts with temperature (log gain scales with Vt). A fixed “dB per decade” mapping no longer holds.
Intercept drift
The curve shifts up/down due to Is change, bias/leakage offsets, or reference movement—often destroying the lowest decades first.
Fix options
Matched devices
Use monolithic pairs and tight thermal coupling to reduce differential drift.
Ratio / translinear
Favor ratio structures that reduce dependence on absolute Is when matching is controlled.
Temp + digital cal
Measure temperature and apply 2-point or LUT compensation for slope/intercept.
Bias injection
Make intercept a controllable parameter by injecting known bias or isolating drift sources.
Pass criteria (system-budget driven)
Slope temperature drift stays within a system budget: drift < X dB over the full temperature range.
Intercept drift does not eliminate low-end decades: mapping remains monotonic down to the target minimum input.
After compensation, residual error across decades remains within a fit residual budget (e.g., residual < Y dB).
Drift path and compensation hooks
The most useful decomposition is slope versus intercept. Ratio structures and matching reduce parameter spread, while temperature-aware calibration can correct residual drift.
A pass decision should be made in the log domain: drift budgets across the full temperature range and guaranteed monotonic decades at the low end.
Error budget across decades: offset, bias, leakage, saturation
The most practical way to specify a log stage is the usable decades: the input span where the log-domain mapping is monotonic and the fit error stays within budget.
In real hardware, decades are bounded by two endpoints: Imin (set by false currents and noise) and Imax (set by compliance, swing, and recovery).
This chapter treats errors as a three-region problem: low-end floor (leakage/bias/contamination), mid-range (device and amplifier non-idealities),
and high-end limit (swing/clamp/series resistance/output drive). “Log linearity” here means log-domain monotonicity + fit residual, not classic linear-domain distortion metrics.
In log feedback loops, the exponential element creates a level-dependent small-signal resistance rd(I). As input current changes across decades,
rd(I) changes, moving pole locations and altering loop gain. Bandwidth and stability are therefore not constant with input level.
Compensation choices (Ccomp, feed-forward shaping, or gain limiting) should be selected against the worst-case current point and verified using both
small-signal response and large-signal recovery after overload or clamp events.
Small-signal OK, but step recovery slow
Likely cause
Loop saturation, clamp engagement, or compensation that is correct for small-signal but too slow when large-signal charge must be removed.
Quick check
Force a single overload event, return to a mid-range current, and measure time to re-enter the log-domain error budget.
Fix
Add headroom or adjust clamp points; tune Ccomp to meet recovery targets without violating stability at the lowest current point.
Pass criteria
Recovery time back to residual < Y dB is < X (system budget).
Bandwidth changes with input level
Likely cause
The effective resistance rd(I) changes across decades, moving loop poles. A compensation network tuned at one current point will not behave the same at another.
Quick check
Measure step or small-signal response at three points: near Imin, mid-range, and near Imax. Compare settling and ringing.
Fix
Choose compensation against the worst-case current point; consider gain limiting or shaping that preserves phase margin across the full current span.
Pass criteria
Settling and overshoot remain within system limits at Imin / mid / Imax.
Ringing after clamp / ESD event
Likely cause
Clamp injection and parasitic capacitances disturb the loop; the effective pole/zero set shifts, reducing phase margin and causing ringing.
Quick check
Trigger a controlled clamp event and observe ringing frequency and decay at the output; compare with the “no clamp” case.
Fix
Reduce clamp capacitance and injection into the summing node; re-tune Ccomp or add damping to keep phase margin across clamp transitions.
Pass criteria
Ringing amplitude and decay time stay within the system transient budget after clamp events.
Compensation selection flow (practical)
1) Define target bandwidth / settling. 2) Identify worst-case current points (near Imin, mid, near Imax).
3) Model pole movement via rd(I) and Ccomp/parasitics. 4) Tune compensation for worst-case phase margin.
5) Verify small-signal response and large-signal recovery (including clamp events).
Level-dependent loop model: rd(I) moves the pole
A compensation network must be validated across the full current span. The worst-case point is usually near the lowest usable current where rd(I) is largest,
but clamp transitions and overload recovery often dominate the system-level behavior.
Noise & dynamic range: input-referred noise, 1/f, and ripple effects
In log-domain chains, noise is best managed in the input domain. A small current noise that looks harmless at mid-range can destroy the lowest decade,
setting the practical Imin. Low-frequency components (1/f and leakage variability) often look like drift, while ripple and interference become
amplitude-modulation-like error after the logarithmic mapping.
A practical budget uses a single language: equivalent input current noise (Ieq) or effective decade resolution (Δdecade) at defined bandwidth/integration settings.
This supports a clear trade between averaging/filtering and response-time requirements.
1) Noise target
Imin goalΔdecade goalBW / Tint
Define the minimum usable input current and the smallest acceptable log-domain resolution. Lock the measurement bandwidth or integration time first,
because it directly sets the noise floor and the bottom-decade survivability.
2) Minimum measurable decade (Imin)
Key idea
Convert all contributions into equivalent input current at the summing node. The largest term near the bottom decade becomes the “owner”
of Imin and should drive layout, parts choice, and fixture controls.
What often dominates
sensor noiseop-amp noiseleakage1/f
1/f and leakage variability often appear as slow drift. Treat them as low-frequency error terms and verify with time-domain stability tests.
3) Verification method
Low-end check
Verify the bottom decade using a fixed BW/Tint and a controlled cleanliness state. Record noise statistics at the lowest intended current point.
Ripple / interference check
Treat ripple as an input proportional error. After log mapping it becomes amplitude-modulation-like output variation, which can look worse across decades.
Pass criteria
Effective decade resolution meets the system budget at the bottom decade and remains stable across the intended bandwidth/integration settings.
Noise budget stacking to effective decade resolution
Lock bandwidth or integration time first. Then budget noise in the input domain to protect the bottom decade and keep decade resolution stable across the intended operating span.
Measurement & verification: how to test “decades” correctly
Decade testing is primarily limited by the stimulus quality and the environment. The lowest decade is usually dominated by shielding, cleanliness, and leakage control,
while high-end behavior is often limited by headroom and overload recovery. A correct verification plan therefore needs a repeatable fixture, a step sequence, and a fit-based pass/fail rule.
A) Fixture / setup
VrefR laddershieldcleanADC / DMM
Use a stable voltage reference and a precision resistor ladder to generate repeatable current steps. Treat shielding and cleanliness as first-class fixture elements
for the bottom decade. Keep the readout bandwidth/integration settings fixed during the test plan.
B) Procedure (repeatable)
Generate decade steps using a 1-2-5 sequence across the target input span.
For each decade, collect N points and compute slope/intercept and fit residual.
Run at 2–3 temperature points to confirm slope drift behavior.
Apply a controlled overload injection and measure recovery back into the residual budget.
C) Data schema (minimum set)
current_step_id (1-2-5)
decade_id
measured_out
fit_residual
temperature
BW / integration_time
recovery_time
conditions (clean/dry/shield)
These fields allow root-cause separation: bottom-decade issues (leakage/shielding), slope drift (temperature), and usability after overload (recovery).
D) Pass / fail (budget placeholders)
fit < X dBrecovery < Y msdrift < Z
X/Y/Z must be set by the system error budget. Use consistent stimulus and BW/Tint so results compare across labs, fixtures, and temperature runs.
Test bench block diagram: decade steps → fit → pass/fail
Use fit-based metrics (slope/intercept and residual) across decades, lock BW/Tint, and include temperature points and overload recovery.
This ensures the “usable decades” claim matches real system behavior.
Log/antilog blocks are often limited by the lowest decade, where leakage, contamination, and guarding dominate. This checklist is organized for
repeatable execution: Review → Build → Test → Pass. Each item is written as a direct check so design reviews and bring-up can converge quickly.
Review (schematic)
Input protectionRClow leakage
Verify protection elements are low-leakage at the bottom decade. Add a bypass option so Imin can be tested with and without the protection path.
Feedback elementmatched pairthermal
Prefer monolithic or array-matched devices. Ensure the schematic supports close thermal coupling and avoids series resistance that compresses high-end behavior.
Calibration hooksswitchEEPROM
Reserve injection points (pads, resistor options, or switchable paths) so slope/intercept can be verified and trimmed without board rework.
Test hooksoverloadreadback
Provide essential pads for readback, stimulus injection, and overload recovery testing. Keep them few, placed away from the high-Z zone.
Build (layout & guarding)
High-Z node: shortest route, minimal surface area, away from connectors and user-touch zones.
Guard ring: continuous ring around high-Z pads/traces; keep the guard low-impedance and consistent.
Clean zone: no silkscreen, no exposed flux traps, no test pads inside the high-Z keepout.
Cleaning/coating: specify process requirements; treat cleanliness as a functional requirement for the bottom decade.
Thermal match: matched devices share the same thermal island; symmetric copper and distance to heat sources.
Leakage paths: highlight flux residue, humidity, fingerprints; keep the high-Z zone physically protected.
ESD path: route discharge currents away from the high-Z zone; avoid return paths under sensitive nodes.
Bottom-decade performance is usually layout and cleanliness limited. Treat guarding, keepout rules, and assembly process notes as part of the circuit definition.
Test (bring-up order)
Gate 1 — Imin (bottom decade)
Verify Imin first under fixed BW/integration settings and controlled cleanliness state. Record stability vs time and handling (touch/move).
If Imin moves with humidity or handling, prioritize leakage/guarding/protection elements before tuning anything else.
Gate 2 — slope (mid-range fit)
Fit slope/intercept across decades using a 1-2-5 stimulus sequence. Confirm slope drift at 2–3 temperature points.
If drift dominates, prioritize matching and thermal coupling, then use calibration hooks.
Gate 3 — Imax & recovery (top-end)
Validate high-end compression/headroom and overload recovery. Measure time to return into the residual budget after a controlled overload injection.
If recovery is slow, prioritize headroom, clamp behavior, and compensation decisions.
Pass (budget placeholders)
fit residual < X dBdrift < Zrecovery < Y msbottom decade stable
X/Y/Z are system-defined. Pass criteria must be evaluated with fixed BW/integration settings and documented cleanliness/fixture conditions for repeatability.
Keep the high-Z node physically isolated, guarded, and clean. Place matched devices in the same thermal island and route ESD/RC discharge paths away from sensitive regions.
Applications (optics / chemistry / acoustics)
These templates help decide whether a log/antilog block fits the chain. Each card uses the same fields:
Input type → Range (decades) → Bandwidth → Temp need → Pass criteria.
The focus stays on signal-chain requirements, not domain theory.
Optics
photodiode Imany decades
Input type: current
Range: decades (wide light)
Bandwidth: chain-defined
Temp need: slope stability
Pass: bottom decade stable
Common limiter: dark current and leakage set the usable bottom decade.
Chemistry
ratio mappingcal interval
Input type: sensor output
Range: multiple decades
Bandwidth: slow/medium
Temp need: drift control
Pass: residual & drift budget
Common limiter: long-term drift drives recalibration strategy and test hooks.
Acoustics
dB scalerecovery
Input type: audio envelope
Range: large dynamics
Bandwidth: application-defined
Temp need: moderate
Pass: recovery & ripple
Common limiter: overload behavior and recovery time dominate perceived performance.
If the chain matches a card above, proceed with IC selection using targets for decades, bandwidth, temperature stability, and recovery.
If the goal is envelope or power measurement rather than logarithmic mapping, a rectifier or RMS path may be a better fit.
Use the templates to translate application needs into engineering targets. Decades protect the ADC range, temperature stability protects slope, and recovery protects usability after overload.
Selection focus: define decades, then lock bandwidth, then set temperature drift and recovery budgets. These inputs drive IC selection and calibration strategy.
IC selection logic (what to ask vendors + decision flow)
This section converts the log/antilog design requirements into two reusable assets:
(1) a 4-step selection flow and (2) a vendor question list that can be copied into RFQs and design reviews.
The goal is to converge on a candidate list that will survive the bottom decade, top-end recovery, temperature drift, and level-dependent bandwidth.
A) Selection flow (4 steps)
Output of each step must be written down as a requirement (not a “nice to have”). If a vendor cannot answer a required line item, the part is not ready for selection.
Step 1Fix Imin (bottom decade)
leakagebiasnoiseclean/guard
Goal
Define the minimum usable decade: the smallest input current/voltage that stays monotonic and stable under real cleanliness and humidity conditions.
Required inputs
Target bandwidth / integration time and acceptable settling behavior.
Bottom-decade stability requirement (no “touch/humidity” sensitivity).
Allowed input protection elements and their leakage constraints.
Reject rules
No max leakage/bias spec at the intended temperature range.
No guidance for guarding/cleaning when used as a bottom-decade instrument.
Output
Imin target + ownership of the limiter (leakage vs bias vs noise) + required cleaning/guarding notes.
Step 2Fix Imax (top-end + recovery)
headroomcomplianceclamprecovery
Goal
Ensure the top-end does not compress unpredictably and returns from overload fast enough for the application’s peak/step behavior.
Required inputs
Supply rails and maximum output swing / drive limits into the next stage.
Maximum expected input level and allowed compression error in log domain.
Overload stimulus definition (amplitude, duration) and recovery time target.
Reject rules
Only static swing specs are provided; overload recovery is unspecified.
Clamp behavior is unclear (risk of “sticking” after saturation).
Output
Imax target + compliance/headroom constraints + overload recovery target and test definition.
Step 3Choose temperature strategy
slopeinterceptmatchingLUT/cal
Goal
Keep the log-domain mapping monotonic and predictable across temperature by deciding what is controlled by hardware matching and what is corrected digitally.
Required inputs
Allowed drift budget expressed in log-domain terms (slope and intercept).
Whether a temperature sensor and periodic calibration are permitted.
Production test capability: points per decade, temperature points, soak time.
Reject rules
Temperature drift is stated only as a “typical curve” without boundaries.
Calibration hooks are not supported (no injection points or trim path).
Bandwidth and recovery requirements written as testable criteria, plus a candidate list ready for lab verification.
Selection flow diagram (4 steps → candidate list)
B) Vendor questions (copy/paste list)
Copy the following blocks into a vendor email/RFQ. Keep the answers in a single table with test conditions.
1) Input & bottom decade
Supported input type: current / voltage (recommended interface).
Input bias current: typ/max, with temperature and test method.
Input leakage paths: max bounds, and guarding/cleaning guidance.
Minimum usable input decade (or minimum current/voltage guidance) and conditions.
Impact of recommended ESD/protection components on bottom-decade leakage.
2) Dynamic range & top-end
Compliance/headroom limits (input and output), including clamp behavior.
Output swing and load drive limits into the next stage (ADC/control).
Overload behavior: what saturates first and how it recovers.
Overload recovery time definition and guaranteed bounds.
3) Temperature drift & long-term stability
Drift expressed as slope/intercept (or equivalent log-domain error) vs temperature.
Matching strategy: monolithic pair/array vs discrete guidance.
Recommended compensation methods and required external components.
Long-term stability/aging notes and recalibration interval guidance.
4) Bandwidth & level dependence
Small-signal bandwidth vs input level (or clear qualitative guidance).
Stability notes with external capacitance/filters and recommended compensation.
Ripple/interference sensitivity notes across decades (if characterized).
5) Integration & calibration support
Supply range (single/dual), output type, and reference availability.
Calibration hooks: injection points, trim pins, EEPROM/LUT support.
Production test guidance: recommended fixtures, points per decade, temperature points.
C) Reference part numbers (starting points; verify with the flow above)
These part numbers are provided to speed up datasheet lookup and vendor discussions. Selection must follow the 4-step flow
(Imin → Imax → temperature strategy → bandwidth/recovery) and be confirmed by decade-stepping and overload recovery tests.
Precision log / log-ratio (current-domain)
TI LOG114
log/log-ratiowide current rangeref included
Example orderable PN: LOG114AIRGVT (package-dependent).
TI LOG112 / LOG2112
log/log-ratiophotodiode biasdark corr
Use when bottom-decade behavior and photodiode biasing are central requirements.
TI LOG101
log/log-ratio1 V/deceasy use
Example orderable PN: LOG101AID (package-dependent).
Multi-stage / special log amplifier
TI TL441
log stagestemp compwide dyn
Consider only when the intended behavior matches the device’s stage-based architecture and test conditions.
Use when the “log mapping” must track fast signals and bursts; verify output scaling and intercept stability against the system’s decade criteria.
ADI AD8310
dc–RFlog conformancefast out
Suitable for wide dynamic range detection with fast voltage output; verify recovery and ripple effects across decades.
ADI AD8318
1 MHz–GHzlog detectorfast
Use when the application is RF/baseband measurement or control; confirm that “decade resolution” maps to the output scaling used by the device.
Practical rule: pick one candidate set, then validate with decade stepping (1-2-5), temperature points, and overload recovery.
If bottom-decade stability fails, fix leakage/guarding before switching parts.
Scope: leakage / drift / fit error / recovery / bandwidth vs input level / temperature compensation & calibration / test traps.
Each answer is a fixed 4-line, measurable structure.
Why does the low-end decade look “stuck” even with no input signal?
Likely cause: Equivalent input current is dominated by leakage/bias/contamination, so the circuit never reaches true “zero” at the bottom decade.
Quick check: Short the input to the intended reference node (or install a known “zero” plug) and compare output before/after dry air bake (e.g., 60–80°C for 30–60 min) and after cleaning.
Fix: Add guard ring/keepout around high-Z nodes, reduce exposed high-Z length, switch to lower-leakage protection parts, and enforce cleaning + conformal coat policy for the high-Z area.
Pass criteria: With “zero” input applied, equivalent input offset < X pA (or < X% of Imin) and no step change > Y% after touch/humidity challenge (X/Y set by system bottom-decade budget).
My slope is correct at room temperature but changes a lot over temperature—why?
Likely cause: The log mapping slope is temperature-sensitive (Vt/Is/mismatch/thermal gradients), so gain-in-log-domain drifts even if room-temp fit looks perfect.
Quick check: Measure 2–3 temperature points (e.g., low / room / high) using the same decade stepping (1-2-5). Fit slope per temperature and compare Δslope.
Fix: Improve device matching/thermal coupling (monolithic/matched pair, same copper island), reduce thermal gradients, or apply temperature-aware calibration (2-point per temp zone or LUT) if drift is repeatable.
Pass criteria: Slope drift < Z dB/dec over the full temperature range (Z set by end-to-end gain/accuracy budget), and slope sign remains monotonic (no reversals) across decades.
Why does touching/cleaning the board change the reading dramatically?
Likely cause: Surface leakage and dielectric absorption around high-Z nodes is dominating the bottom decades; finger oils/moisture change the parasitic resistance and capacitance.
Quick check: Compare output with (a) guard driven vs not driven (if available), and (b) with temporary shield/cover placed over the high-Z region; observe if error scales strongly with proximity.
Fix: Enforce guard ring + clean keepout, remove soldermask in guarded region if needed, shorten high-Z traces, relocate flux residues away from high-Z, and add conformal coating after verified cleaning.
Pass criteria: Touch/near-hand test causes < Y% output change at Imin decade, and settling returns within T s after removal (Y/T set by application stability requirement).
Bandwidth is fine at high current but becomes very slow at low current—normal?
Likely cause: The effective resistance of the exponential element increases at low current, moving poles lower; added compensation capacitance makes low-current response slower.
Quick check: Measure step response at two levels separated by ≥2 decades and compare time constants; if τ scales strongly with level, the dominant pole is level-dependent.
Fix: Re-tune compensation for the minimum-current operating point (worst-case pole), limit bandwidth requirement at the bottom decade, or use architecture/device options designed for flatter dynamics across range.
Pass criteria: At Imin, 1% settling time < S ms (or group delay < D ms) and no ringing > R% for the defined step (S/D/R set by system latency and stability budget).
Why does the output take seconds to recover after a large overload?
Likely cause: The loop saturates/clamps and internal nodes store charge; the recovery path is limited (output current limit, protection clamp, or exponential element bias recovery).
Quick check: Apply a defined overload pulse (amplitude A, width W) then return to a low-level decade; measure time to return within ±1% (or within log-domain error band).
Fix: Prevent deep saturation (headroom/compliance), add controlled discharge/reset path for the saturated node, or reduce overload energy via front-end limiting that preserves low-leakage at Imin.
Pass criteria: Recovery time < Y ms after overload defined as (A, W), and post-recovery fit residual returns to < X dB across the validated decades (X/Y defined by application peak rate).
Log response looks linear for 2–3 decades but bends at the ends—what limits it?
Likely cause: Bottom end is limited by leakage/bias/noise; top end is limited by compliance, output swing, series resistance, or clamp behavior—both appear as curvature in ln-domain fit.
Quick check: Fit the mid-range and plot residual vs input level; if residual grows only at low end → leakage/noise; if only at high end → headroom/compliance; if both → range is overclaimed.
Fix: Redefine usable decades (Imin/Imax), improve bottom-end cleanliness/leakage, increase headroom/compliance at top end, and avoid protection/clamps that conduct in normal operation.
Pass criteria: Fit residual < X dB across ≥N points/decade for the declared decade span, with endpoints not exceeding 2X dB (X/N set by required accuracy and production margin).
Using a diode vs a BJT: why does drift/curvature change so much?
Likely cause: Different ideality factors, saturation currents, series resistance, and matching quality change both slope and intercept drift, producing different curvature at the extremes.
Quick check: Compare two builds with identical layout/guarding and fit slope/intercept over 2–3 temperature points; inspect whether changes appear as slope drift, intercept drift, or end curvature.
Fix: Prefer monolithic/matched devices for repeatable behavior, ensure tight thermal coupling, and avoid series resistance dominance at high end; use calibration only when drift is repeatable and measurement uncertainty is well below the target.
Pass criteria: Across the declared decades, slope/intercept variation stays within the allocated drift budget (e.g., <Z dB/dec slope drift and <W dB intercept shift over temperature).
My fitted line (ln domain) is noisy—how do I separate noise from leakage drift quickly?
Likely cause: Random noise averages down with time, while leakage drift and humidity/contamination effects show slow trends and strong sensitivity to environment.
Quick check: At a fixed low-level decade, record output for T seconds and compute (a) short-term RMS and (b) long-term slope; repeat after dry air bake—noise stays similar, leakage drift changes materially.
Fix: If noise-dominated: increase averaging or reduce bandwidth at that decade. If drift-dominated: fix leakage paths (guard/clean/coating) and remove leaky protection components near high-Z nodes.
Pass criteria: After the chosen averaging window, short-term RMS corresponds to <X dB decade-resolution noise, and long-term drift <Y dB over T seconds at Imin (X/Y/T set by stability requirement).
Why does adding input protection (RC/TVS) worsen accuracy at low current?
Likely cause: Protection parts add leakage and dielectric absorption; even “low-leakage” clamps can dominate the bottom decade and appear as a false input current.
Quick check: Measure “zero input” output with and without the protection population option (DNP test). If the bottom decade shifts by a large fraction of Imin, leakage is the limiter.
Fix: Move protection away from the high-Z node, use series resistance to limit surge energy before the clamp, select ultra-low-leakage TVS/diodes, and guard the clamp node if it sits near the measurement node.
Pass criteria: With protection installed, bottom-decade offset increase <X pA (or <X% of Imin) and decade-fit residual stays within the allocated budget across temperature/humidity corners.
How do I generate accurate decade current steps without expensive equipment?
Likely cause: Many “current sources” are not accurate across decades; the fixture itself leaks and creates systematic error at low current.
Quick check: Build a voltage reference + precision resistor ladder (1-2-5 sequence) and verify each step by measuring the resistor value and applied voltage; perform a DNP/short test to quantify fixture leakage.
Fix: Use guarded high-value resistors, keep ladder physically away from the DUT high-Z node, add shielding, and document a calibration factor per decade if needed (only if repeatable and uncertainty is low).
Pass criteria: Step ratio error <X% per decade and fixture leakage <Y pA equivalent at the DUT input (X/Y set so measurement uncertainty is <25% of allowed DUT error).
When is digital calibration (2-point/LUT) worth it vs matched hardware?
Likely cause: Hardware mismatch and drift can be compensated only if the error is repeatable and the measurement uncertainty is much smaller than the target error.
Quick check: Repeat the same decade sweep across temperature and time; if slope/intercept errors are consistent (low scatter) and residual shape is stable, calibration can help; if not, leakage/instability dominates and calibration will not hold.
Fix: Use 2-point calibration for mainly slope/intercept errors; use LUT only when curvature is stable and production test can support enough points per decade; otherwise, invest in matching/guarding to reduce the root cause.
Pass criteria: Post-cal residual <X dB across the declared decades and remains <X dB after temperature cycling; measurement uncertainty <0.25X (rule-of-thumb for avoiding overfit).
Why does humidity make the error explode, and what’s the fastest mitigation?
Likely cause: Humidity lowers surface insulation resistance and activates ionic contamination; the resulting leakage can exceed the intended bottom-decade current by orders of magnitude.
Quick check: Run the same “zero” and one low-decade point at two humidity conditions (ambient vs dry box) and compare the equivalent input offset; large shifts indicate surface leakage dominance.
Fix: Immediate: dry/bake and keep the high-Z region covered/shielded. Permanent: improve cleaning, add guard ring/keepout, use conformal coat, and avoid hygroscopic materials/flux residues near high-Z nodes.
Pass criteria: Across the specified humidity range, bottom-decade offset shift <X pA (or <X% of Imin) and fit residual stays within the same accuracy budget (X set by worst-case environmental spec).
