HART FSK Modem for 4–20 mA Loops
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This page explains how to add and recover HART FSK on a 4–20 mA loop without disturbing the DC measurement: model the AC/DC split, choose injection/extraction and isolation partitions, then close noise and recovery risks with measurable pass/fail gates.
Definition & Scope
This section pins down what “HART FSK modem” means at the physical layer, where it sits in a 4–20 mA loop, and what is intentionally excluded to prevent topic drift.
What a HART FSK modem is (one sentence)
A HART FSK modem is a physical-layer analog/mixed-signal block that injects and extracts low-amplitude FSK tones on top of a 4–20 mA DC current loop, while keeping the loop’s DC accuracy and stability intact and preserving a measurable detection margin under real cable, isolation, and noise conditions.
- A minimal loop model to reason about “DC vs AC overlay” failures without over-explaining 4–20 mA theory.
- Practical RX/TX partitioning patterns for stable injection/extraction under isolation and cable variability.
- A noise-to-failure map with first probes (where to measure first, and what signature to look for).
- Verification gates (bench → production) with pass criteria placeholders (X/Y/Z) that can be tied to system budgets.
Where it sits in a 4–20 mA loop (host vs field device)
The modem is the “overlay boundary” between a noisy, impedance-variable loop (cable + supply + load) and a clean decision domain (bit stream into/out of a digital controller). It may appear on:
- Focus: compatible injection, detection robustness across unknown field wiring, diagnostics and logging.
- Typical failure signatures: “tone visible on scope” but decode unstable; station-to-station mismatch; susceptibility to conducted noise.
- Focus: isolation partitioning, noise mitigation, stable extraction without disturbing the loop’s DC measurement path.
- Typical failure signatures: decode breaks on long cable, ground shift, or after ESD/surge recovery; injection causes DC offset or loop oscillation.
- FSK decode passes on bench but fails with real cable, isolation, or cabinet wiring.
- Enabling injection shifts the reported 4–20 mA value or creates slow settling/oscillation.
- Decode errors correlate with supply ripple, ground shift, or barrier-related coupling paths.
Not-in-scope (kept out to prevent cross-page overlap)
The topics below are intentionally not expanded here. When needed, only a brief reference is made and the reader is redirected to the canonical page.
- 4–20 mA loop fundamentals (accuracy, scaling, sensor/transmitter basics)
- HART protocol stack (frames/commands/host software)
- Intrinsic safety (entity parameters, approvals, certification workflow)
- EMC / surge standards (IEC details and full compliance reporting)
- Gateways & asset management (system integration and fleet tooling)
- Other overlay PHYs (PLC / OFDM overlays and their coupling networks)
System Context: 4–20 mA + FSK Overlay
The modem problem is not “communication in isolation.” It is a constrained overlay in a current loop where DC accuracy and loop stability are non-negotiable, while AC detection must survive cable variability, conducted noise, and isolation-related coupling.
Loop elements (minimal model, only what impacts overlay)
The overlay can be analyzed with a minimal set of loop elements. Each element is included only because it changes the AC transfer, injects interference, or modifies the effective impedance seen by injection/extraction networks.
- Supply (PSU): conducted ripple/noise that can sit in-band or create broadband raising of the noise floor.
- Sense resistor / measurement point: defines where AC becomes observable as voltage; may create “measurement mismatch” between stations.
- Cable / wiring: distributed capacitance/inductance; acts as both an impedance shaper and an antenna for common-mode pickup.
- Load / field device impedance: changes with operating current, temperature, and internal biasing; shifts tone amplitude and phase.
- Isolation barrier + isolated power: parasitic coupling and power noise can form a hidden path that bypasses intended filters.
Overlay robustness depends on controlling the transfer function between injection and extraction, and controlling the unwanted coupling paths that raise in-band noise or distort the tone. When the loop changes, the modem must keep enough detection margin without corrupting DC behavior.
Overlay principle: AC rides on DC, but DC must remain stable
Overlay means the same two-wire loop carries two “contracts” simultaneously: a DC contract for process measurement/control, and an AC contract for data. Any design choice must satisfy both.
- No mean shift: injection must not change the average loop current (DC offset < X).
- Controlled transients: enable/disable or switching must not create large steps/ringing (transient < Y).
- Loop stability preserved: injection/extraction networks must not destabilize the loop (stability margin > Z).
- Detection margin: tone-to-noise margin must remain above a budgeted floor (margin > X dB).
- Distortion control: coupling/filter choices must not distort tone phase/group delay beyond the demod tolerance.
- Recovery behavior: after ESD/surge or overload, the chain must recover within a bounded time (recovery < Y).
- Bench cabling is short and stable; field wiring is long and variable, shifting impedance and common-mode pickup.
- Cabinet power and ground conditions introduce conducted ripple and ground shift that change the in-band noise floor.
- Isolation introduces a hidden coupling path (barrier capacitance + isolated power noise) that can bypass intended filters.
Where coupling happens (injection / extraction / hidden common-mode paths)
Coupling points are design points and failure points. Each coupling point should map to: what it does, how it fails, and what to probe first.
- Does: adds controlled AC energy to the loop without changing mean current.
- Fails: DC shift, slow settling, or loop oscillation due to unintended poles/zeros.
- First probe: DC current step and transient at sense point when injection toggles.
- Does: converts loop AC into a usable signal for filtering/detection.
- Fails: tone amplitude collapses with cable/impedance changes; in-band noise dominates.
- First probe: in-band tone-to-noise at the extraction output (before deep filtering/AGC).
- Does: unintentionally moves noise across barrier/cable through parasitics and return paths.
- Fails: clean-looking tones on one measurement point but decode errors at the detector.
- First probe: common-mode activity across the barrier and isolated supply ripple correlated with errors.
The modem must treat DC and AC as separate responsibilities with explicit interfaces: a DC-safe injection boundary, an AC extraction boundary, and a containment plan for hidden coupling paths. This is the foundation for isolation partitioning, noise mitigation, and measurable verification gates.
Next, the design is built on this model by detailing the receive extraction/detection chain, the transmit injection chain, and the isolation partitioning choices that reshape noise paths and determine measurable verification gates.
Signal Fundamentals: FSK, Spectrum, and Budget
The overlay must be engineered as a budgeted signal chain. Tone levels, loop impedance, noise sources, bandwidth, and pass criteria must be stated in measurable terms, not as abstract “communication” assumptions.
FSK tones & spectral placement (filtering and interference only)
The receive chain “sees” two narrowband tones in a real spectrum shaped by cable impedance and power/EMI artifacts. The design goal is to keep the tones separable after the intended band-pass filtering, while preventing near-band and out-of-band energy from becoming in-band errors through distortion or aliasing.
- In-band: directly raises the noise floor and reduces tone margin.
- Near-band: may leak through the BPF and bias detection thresholds.
- Out-of-band: can fold into band via limiter nonlinearity or ADC aliasing.
- Confirm both tones are visible at the extraction output with a stable baseline noise floor.
- Look for narrow spurs correlated with PSU switching or cabinet interference signatures.
- Check whether near-band energy rises when injection is enabled or when cable length changes.
AC amplitude vs loop impedance (why “too strong” can break DC)
Increasing tone amplitude is not a free gain knob. The loop presents an effective impedance that shifts with wiring, load, and operating point. Excess injection energy can violate the DC contract through mean shift, transients, or stability degradation.
- Higher observable tone at extraction.
- Higher tone-to-noise margin in-band.
- Lower sensitivity to cable impedance changes.
- Mean shift: injection must not create DC offset (X).
- Transient shock: injection toggling must stay bounded (Y).
- Stability loss: added networks must keep margin above target (> Z).
Tone amplitude must be defined at a named measurement point (typically the extraction output), and validated against DC disturbance at the sense point. Any “bigger tone” change must be accompanied by a DC mean-shift check, a transient check, and a stability-margin check.
Noise budget view: SNR, in-band interference, out-of-band blockers
A useful noise budget names the dominant noise sources, the coupling paths, and the signatures that indicate which term is limiting. Budgeting should prioritize what raises the in-band floor and what biases detection through distortion or aliasing.
- Conducted ripple: probe isolated supply ripple and loop ripple near the extraction point.
- Common-mode pickup: probe barrier common-mode activity and cable-related CM spikes.
- Nonlinearity folding: probe limiter/clamp activity correlated with errors.
- Aliasing: probe pre-ADC spectrum and confirm anti-alias boundary behavior.
- Fix what raises in-band floor at the extraction output.
- Fix what biases detection (limiter artifacts, near-band leakage).
- Fix what folds/aliases out-of-band into band.
Design targets as placeholders (X/Y/Z)
Thresholds depend on system requirements and site conditions. Use placeholders to keep the page portable while still engineering with hard pass/fail gates.
- Tone margin (at extraction output): tone-to-noise > X dB.
- DC mean shift (at sense point): < Y.
- Injection transient (toggle event): < Z.
- Recovery time (after event): < T.
Placeholders should be derived from loop accuracy requirements, cable-length ranges, site noise environment, and diagnostic objectives. The verification chapter should bind X/Y/Z/T to measurable station settings and logging fields.
- Observable tone amplitude at extraction output: ≥ X.
- Tone-to-noise margin in-band (pre/post BPF): > Y dB.
- Allowed tone distortion / group delay impact: < Z.
- Conducted ripple (loop + isolated supply).
- Common-mode pickup (cable + barrier parasitics).
- Nonlinearity folding (clamp/limiter artifacts).
- Aliasing (anti-alias boundary leakage).
- Reduce in-band floor at extraction output before adding gain.
- Prevent near-band leakage that biases detection thresholds.
- Block out-of-band blockers from folding/aliasing into band.
Receiver Path: Extract → Filter → Detect
The receiver must convert an impedance-variable, noise-exposed loop waveform into a stable bit stream. The chain is structured so each block has a clear purpose, an associated failure signature, and a first measurement tap.
Extraction coupling network (pick up AC without disturbing DC)
Extraction defines where the overlay becomes observable. The coupling must preserve the DC measurement path while providing a predictable AC transfer across cable and load variation. Common-mode pickup should be contained before it enters the detection chain.
- Make tones observable at a named node (Tap1) with minimal DC impact.
- Limit common-mode energy that can masquerade as differential tone.
- Tap1 (coupler output): tone amplitude and baseline floor before aggressive filtering.
Front-end protection & limiting (avoid event-driven failures)
Protection is part of the signal chain. Clamps and limiters prevent damage and overload, but they can also introduce nonlinearity that folds out-of-band energy into the detection band and can create long recovery artifacts after events.
- Decode errors correlate with clamp activity or after event recovery time.
- Spur-only failures appear when averaging hides transient overload behavior.
Detailed IEC/ESD compliance requirements are referenced via the protection canonical page; this section focuses on how protection affects detectability.
Analog conditioning (BPF / gain / anti-alias)
Conditioning should preserve tone separability while keeping the detector unbiased. Narrowing the band-pass filter can improve rejection but may increase group-delay distortion or create sensitivity to impedance shifts. Gain should be chosen to avoid saturation and avoid integrating noise unnecessarily.
- “Cleaner spectrum” caused by measurement settings rather than true margin improvement.
- Limiter/ADC saturation that looks like random errors but is event-driven.
- Aliasing of out-of-band noise due to insufficient anti-alias boundary control.
- Tap2 (BPF out): verify tone separation and near-band leakage.
- Pre-ADC node: confirm anti-alias control of out-of-band blockers.
Detection options (analog vs digital, trade-offs only)
Detection should be selected based on required diagnostics and tolerance to loop variability. The choice is not “better algorithm” but “better budget closure” with measurable taps and stable thresholds.
- Pros: low latency, low compute, simple integration.
- Risks: threshold drift, part-to-part variation, sensitivity to limiter artifacts.
- Pros: adaptive thresholds, richer logging/diagnostics, easier correlation across stations.
- Risks: aliasing sensitivity, processing latency, dependence on anti-alias boundary.
Tap3 (detector input): confirm that tone separation and baseline noise meet the margin placeholder before tuning detection logic.
- Tap1 (Coupler out): tone amplitude, baseline floor, CM-related spikes.
- Tap2 (BPF out): tone separation, near-band leakage, group-delay sensitivity signatures.
- Tap3 (Detector in): detection margin check before tuning thresholds or DSP logic.
Transmitter Injection: Add FSK Without Breaking DC
Injection must deliver observable FSK tones while preserving the loop’s DC contract. Common failure modes are DC mean shift, toggle transients, and loop instability caused by added impedance paths and parasitics.
- DC mean shift must remain below X at the DC sense point.
- Injection transient on enable/disable must remain below Y (step/ring limit).
- Stability margin must stay above Z across cable and load variation.
Injection topologies (voltage vs current injection)
The practical difference is where the overlay is controlled: voltage injection shapes an AC voltage at a chosen node, while current injection shapes an AC current through a defined path. Both must prevent DC leakage and prevent “hidden rectification” that creates a mean shift.
- Strength: direct control of a local AC node amplitude (TapTX).
- Risk: node impedance drift changes delivered tone and transient shape.
- Failure signature: tone looks strong at TapTX but DC sense shows step/ring.
- Strength: overlay scales with defined AC current path (less node-sensitive).
- Risk: unintended return paths can back-inject noise into the loop.
- Failure signature: in-band floor rises when injection is enabled (noise backfeed).
- TapTX: injected waveform integrity and switching edge artifacts.
- TapDC: DC mean shift and toggle transient envelope.
Mute / soft-start / blanking (control toggle transients)
Enable/disable events are often the dominant source of DC disturbance and decode spikes. A robust strategy defines an event timeline: mute → precharge/soft-start → steady modulation → release blanking.
- TapDC: peak step/ring during t0→t1 and t1→t2 transitions < Y.
- TapDC: steady-state mean shift after t2 settles < X.
- TapTX: injected waveform free of switching spikes that correlate with decode errors.
Interaction with loop stability (injection network adds zeros/poles)
Any injection network is an impedance added to the loop. It can create new time constants, shift phase margin, and amplify sensitivity to cable/load variation. Stability issues typically present as oscillation, slow recovery, or “only certain combinations fail.”
- DC reading shows slow settling after injection enable/disable.
- TapDC exhibits ringing that scales with cable length or load.
- Decode fails only at specific cable/load corners (critical combinations).
- Toggle injection on/off and record TapDC peak and recovery time.
- Sweep representative cable/load corners and confirm margin > Z.
- Verify injection damping reduces ringing without increasing mean shift.
Pass criteria (placeholders) and TX injection checklist
- DC mean shift (TapDC steady): < X.
- Toggle transient (TapDC peak/ring): < Y.
- Stability margin (corner sweep): > Z.
- Isolation/AC coupling enforces DC blocking (no leakage path across PVT corners).
- Damping is present to limit ringing at the injection node.
- Mute + soft-start + blanking timeline is defined and verified at TapDC.
- Injection driver noise does not backfeed into the loop (Tap1 floor does not rise).
- At least two measurement taps are reserved: TapTX (injection node) and TapDC (DC sense).
Isolation Partition: Where to Put the Barrier
Isolation placement reshapes noise coupling paths. The key decision is whether the barrier sits in the analog path (before ADC) or in the digital path (after ADC), and how barrier parasitics and isolated power inject or block interference relevant to FSK detection.
Partition options (analog-before-barrier vs digital-after-ADC)
- Strength: common-mode disturbances are cut earlier.
- Risk: barrier parasitics and isolated power noise become critical.
- Debug: fewer direct analog nodes on the safe side (requires planned taps).
- Strength: analog chain stays in one domain for easier probing.
- Risk: ADC/front-end still sees ground shift and CM pickup.
- Debug: better logging and diagnostics across the digital barrier.
Choose the partition that closes the tone margin budget while minimizing event-driven in-band floor rise. Debug visibility should be planned via taps and logs, not assumed.
Barrier parasitics (shielding and capacitive coupling)
Barrier capacitance can transmit fast common-mode events across the isolation boundary. Asymmetry converts common-mode into differential artifacts that can land inside the detection band or bias thresholds. Shielding and layout symmetry are the practical levers.
- Decode errors correlate with high dv/dt events (motors, relays, drives).
- In-band floor jumps temporarily at Tap1/Tap2 without DC mean shift.
- Spur bursts appear that disappear under excessive averaging.
- Compare barrier-side common-mode activity during events.
- Observe Tap1/Tap2 floor changes synchronized with dv/dt events.
Isolated power strategy (noise injection paths)
Isolated DC/DC ripple and switching currents can dominate the interference budget if their return paths couple into the extraction and conditioning nodes. The goal is to prevent isolated power artifacts from becoming in-band floor rise or near-band bias.
- Ripple couples into analog reference nodes near extraction.
- Switching current loops radiate into the front-end and cable.
- Digital edge currents cross-couple through the barrier into analog nodes.
- Power ripple correlates with Tap1 floor rise (injection enabled/disabled A/B).
- Relocate/contain switching loops and confirm the floor drop at Tap2.
- Confirm no new spurs appear at detector input when digital traffic increases.
CMTI / ground shift scenarios (only what breaks detection)
- Ground potential step causes short decode dropouts while DC remains nominal.
- High dv/dt events create bursts that bias thresholds (Tap3 shifts).
- Recovery after events must meet the time placeholder T.
- Tap1/Tap2 in-band floor rise during event: < ΔN.
- Tap3 margin during event: > M.
- Event recovery time back to nominal margin: < T.
- If ground shift / high dv/dt events dominate failures: prefer A to cut CM earlier (then control isolated power noise).
- If debug visibility / diagnostics is a top requirement: prefer B and enforce anti-alias and CM control at the ADC front-end.
- If isolated power noise is hard to contain: avoid placing the barrier where ripple directly feeds the extraction/conditioning nodes.
- Finalize by verifying: event floor rise < ΔN, event margin > M, recovery time < T (placeholders).
Noise & Interference: What Actually Breaks Demod
Real failures are best organized by how they break detection: raising the in-band floor, biasing thresholds, or creating burst artifacts after events. Each noise type is mapped to a coupling path, a signature at Tap1/Tap2/Tap3, a fast A/B check, and a minimal mitigation action.
- Conducted (power ripple / ground shifts) → in-band floor rise (ΔN).
- EMI pickup (cable/common-mode) → bursty errors & slicer bias during activity.
- Protection events (ESD/surge recovery) → post-event artifacts & slow recovery (T).
Conducted noise (SMPS ripple, ground shifts)
Conducted noise typically breaks demod by lifting the in-band floor or by biasing comparator/decision thresholds through shared references and return paths. The most frequent mechanism is event-synchronized ripple that enters the extraction or conditioning nodes and reduces tone-to-floor margin.
- Tap2 in-band floor rises by ΔN (placeholder), even when tones remain present.
- Tap3 decision level drifts (threshold/bias shift) under load or switching activity.
- Errors become periodic (tied to switching cadence), not random.
- Disable/enable a dominant switching load and compare Tap2 floor (ΔN) and Tap3 margin (M).
- Hold injection constant and compare floor with alternate power configuration (same cable/load).
- Reduce shared impedance in sensitive returns (shorten/define the return path into extraction and threshold nodes).
- Harden reference nodes used by detection (reduce ripple coupling into Tap2/Tap3 domains).
- Pass intent: Tap2 floor rise < ΔN and Tap3 margin > M (placeholders).
EMI pickup (cable antenna, common-mode injection)
Cable pickup is often common-mode first. Asymmetry (termination, layout, barrier parasitics) converts common-mode into differential artifacts that land near or inside the detection band. The result is bursty errors, slicer bias, or false detects—often with DC loop behavior appearing normal.
- Errors correlate with cable routing, length, or proximity to aggressors.
- Tap1/Tap2 show event-synchronous bursts; Tap3 exhibits momentary bias shifts.
- False detect increases when activity (motors/relays/drives) occurs nearby.
- Change only cable routing/position and compare burst rate at the bit output.
- Add a temporary common-mode suppression experiment and compare Tap2 floor rise during aggressor events.
- Increase symmetry around the coupling and detection nodes (reduce CM→DM conversion).
- Control the common-mode return path and ensure consistent shielding/ground reference strategy.
- Pass intent: burst-driven Tap2 rise < ΔN and false-detect rate < F (placeholders).
Protection events (ESD/surge causing recovery artifacts)
Many field issues are not hard damage, but recovery artifacts: temporary floor rise, transient saturation, or threshold bias that persists for a window after the event. The demod chain should define an event window, measure recovery, and reject or mask decisions until margin returns.
- Short bursts of errors after an event, even with stable DC behavior.
- Tap2 shows temporary floor elevation; Tap3 shows saturation/clip signatures.
- Margin recovers slowly and depends on clamp/limiter release behavior.
- Log Tap2 floor and Tap3 margin in the post-event window and measure recovery time T.
- Compare clamp/limiter enable vs bypass (if possible) and observe burst rate change.
- Define event masking/blanking until Tap3 margin returns above M.
- Reduce recovery artifacts by controlling clamp release and front-end overload behavior.
- Pass intent: recovery time < T and post-event error bursts < B (placeholders).
Mitigation tactics mapped to noise type (signature → action → pass)
Action: shorten returns, harden references.
Pass: ΔN < X, margin > M (placeholders).
Action: improve symmetry; control CM return path.
Pass: false-detect < F, ΔN < X (placeholders).
Action: event masking; control overload release.
Pass: recovery < T, bursts < B (placeholders).
Demod Implementation: Analog vs DSP, and Practical Traps
Implementation choice is less about “algorithm names” and more about measurable margins, latency, and failure signatures. This section compares analog and DSP paths, highlights traps (over-filtering, AGC/limiter bias, timing windows), and specifies mandatory taps and production log fields.
Analog demod vs DSP demod (tradeoffs only)
- Strength: short chain, low latency, minimal compute.
- Trap: threshold drift and overload/rectification artifacts bias decisions.
- Must watch: Tap2 tone-to-floor and Tap3 threshold/bias stability.
- Strength: adaptable detection and direct “confidence/margin” telemetry.
- Trap: long windows reduce apparent noise but increase sensitivity to timing and events.
- Must watch: Tap2 alias/floor and Tap3 margin vs latency (L placeholder).
Timing/latency vs robustness (the “cleaner but weaker” trap)
Narrower filters or longer detection windows often reduce apparent noise, but can increase sensitivity to frequency drift, burst interference, and post-event recovery. Robust demod must trade off margin telemetry against latency constraints.
- Tap2 looks quieter, but bit errors become burstier during events.
- Margin becomes “peaky”: high when quiet, collapses when drift or bursts occur.
- Event recovery time increases beyond T when filters/windows are too long.
- Change only filter/window strength and compare burst rate and margin telemetry at Tap3.
- Record latency L and verify margin > M under event windows.
AGC / limiter artifacts (compression biases decisions)
Compression can remove amplitude cues and distort tone balance. When AGC responds to interference, it can shift effective thresholds and change the decision boundary. The demod should explicitly log gain/clip state and correlate it with margin and burst errors.
- Tap3 “margin” collapses only when AGC moves or limiter clips.
- False detect increases after strong bursts even though Tap2 tones are present.
- Bias appears as asymmetry in decision statistics (threshold offset).
- Hold input constant; vary AGC time constant and compare burst rate vs Tap3 bias.
- Log limiter/clip flag and correlate with decode failures (event-driven).
Debug signals to log (production-ready fields)
The log set should allow “noise type → signature → mitigation” mapping without lab equipment. Fields below are intentionally implementation-agnostic and tie to Tap points.
- Tap2_inband_floor (ΔN)
- Tap2_tone_A0 / Tap2_tone_A1
- Tap3_margin_or_confidence (M)
- Tap3_threshold_estimate
- AGC_gain_state / Limiter_clip_flag
- Window_length_or_latency (L)
- Event_flag (surge/ESD/power_dip)
- Recovery_time_estimate (T)
- Burst_error_count_per_window (B)
- ΔN rise with stable A0/A1 → conducted or pickup floor dominance.
- M collapse with limiter flag → compression-driven bias.
- Event_flag + long T → recovery artifact dominance.
- Tap1: extraction/input node (noise coupling visibility).
- Tap2: BPF output (tone vs floor margin).
- Tap3: detector/slicer input (threshold bias and decision margin).
Verification: Bench Setup, Metrics, Pass/Fail Gates
The verification flow is structured as a reusable SOP: build a minimal loop bench, measure Tap-based margins, apply pass/fail gates, and avoid configuration artifacts. All thresholds are placeholders (X/Y/Z/T/ΔN/M/B) to match system budgets.
- Bench setup (loop + cable + injection + stress)
- Metrics (Tap2 floor/tones, Tap3 margin, bursts, recovery, DC disturbance)
- Pass/Fail gates (ordered checks)
- Settings traps (filter/BW/sample-rate artifacts)
Bench setup (loop simulator / cable emulation / isolator stress)
A good bench isolates variables. The core loop must stay stable while injection/noise/stress modules are switched in one at a time. Each module connects to defined nodes so results map directly to Tap1/Tap2/Tap3 signatures.
- Loop supply + sense resistor + DUT + return path.
- Defined injection point (TX) and extraction point (RX).
- Tap points: Tap1 (extraction), Tap2 (BPF out), Tap3 (detector/slicer).
- Cable emulation: length/RC worst-case steps (placeholder values).
- Noise injection: ripple/CM stimulus at defined nodes.
- Isolation stress: ground shift / CM step / barrier coupling stimulus.
Change one variable per run. Keep cable, loop supply, and injection amplitude constant when comparing partitions or demod settings.
Metrics: margin, bursts, recovery, DC disturbance (placeholders only)
Metrics must be observable at Tap points and tie to gates. Favor proxies that correlate with failures: Tap2 tone-to-floor, Tap3 margin/confidence, burst counters, recovery time, and DC loop disturbance.
- Tap2_inband_floor (ΔN) and Tap2_tone_A0/A1.
- Tap3_margin/confidence (M) at detector/slicer input.
- Pass intent: ΔN < X and M > Y (placeholders).
- Burst_error_count per window (B), not just average error rate.
- False-detect counter (F) if available.
- Pass intent: B < X and F < Y (placeholders).
- Recovery time T: event → Tap3 margin returns above threshold.
- Measure within a defined post-event window.
- Pass intent: T < X (placeholder).
- DC shift during injection switching and stress events.
- Settle time after switching or recovery actions.
- Pass intent: DC shift < X and settle < T (placeholders).
A/B isolation tests (same DUT, different partitions)
Isolation decisions should be validated experimentally. Keep the loop and cable identical and change only the isolation partition or isolated power strategy. Compare Tap2 floor (ΔN), Tap3 margin (M), and recovery time (T) under the same stress profile.
- Cable, load, loop supply, injection amplitude.
- Same demod settings and the same event window definition.
- ΔN change at Tap2 (floor dominance).
- M change at Tap3 (decision robustness).
- T change (recovery artifact dominance).
Partition A is preferred when ΔN and M improve under cable/CM stress. Partition B is preferred when recovery time T shortens and burst errors B reduce under event windows. Use placeholders only; thresholds come from system budgets.
Settings traps (filters, bandwidth, sampling rate artifacts)
“Cleaner plots” can be artifacts. Treat Tap3 margin and burst counters as primary pass/fail signals, and use setting changes as falsification tools.
Falsify: change window/filter strength; verify B and M respond (placeholders).
Falsify: keep Tap3 M and burst B as gating metrics, not plot aesthetics.
Falsify: vary sampling rate / anti-alias settings; verify ΔN stability (placeholder).
Pass/Fail gates (ordered checks)
- Gate 0 — DC: DC shift < X; settle < T (placeholders).
- Gate 1 — Tap2: ΔN < X and A0/A1 stable (placeholders).
- Gate 2 — Tap3: margin/confidence M > Y (placeholders).
- Gate 3 — Recovery: event recovery time T < X (placeholder).
- Gate 4 — Bursts: B < X and F < Y (placeholders).
- Gate 1 fails → conducted or pickup floor dominance (ΔN).
- Gate 2 fails → threshold/compression/timing traps (M).
- Gate 3 fails → protection recovery artifacts (T).
- Gate 0 fails → injection network or loop stability interaction (DC disturbance).
Engineering Checklist (Bring-up → Production)
The checklist turns experience into a repeatable pipeline. Every item is written as an actionable check with evidence (Tap/metrics) and a placeholder pass criterion. The scope stays within HART modem coupling, conditioning, isolation, protection, and production test hooks.
Layout & grounding checklist (HART modem focused)
- Check: keep extraction and Tap2/Tap3 nodes away from high dv/dt return currents.
Evidence: Tap2 ΔN stays stable when nearby aggressors switch.
Pass: ΔN < X (placeholder). - Check: enforce symmetry to reduce CM→DM conversion around coupling and threshold nodes.
Evidence: burst errors B do not increase with cable routing changes.
Pass: B < X (placeholder). - Check: define short, deterministic return paths for sensitive references used by detection.
Evidence: Tap3 margin M is insensitive to load switching.
Pass: M > Y (placeholder).
Protection placement checklist (location + return intent)
- Check: place clamps to intercept events before sensitive extraction/conditioning nodes.
Evidence: post-event Tap2 floor rise is limited; Tap3 does not saturate.
Pass: recovery time T < X (placeholder). - Check: ensure clamp return paths do not share impedance with Tap2/Tap3 references.
Evidence: Tap3 threshold estimate does not drift during event windows.
Pass: threshold shift < Y (placeholder). - Check: validate overload release does not create long recovery tails.
Evidence: margin M returns quickly after events.
Pass: T < X and bursts B < Y (placeholders).
Isolation power checklist (back-injection paths)
- Check: identify barrier parasitics and confirm isolated supply switching does not raise Tap2 floor.
Evidence: Tap2 ΔN does not track isolated converter activity.
Pass: ΔN < X (placeholder). - Check: keep isolated power return currents from coupling into detection thresholds.
Evidence: Tap3 margin M does not collapse when isolated loads switch.
Pass: M > Y (placeholder). - Check: stress ground shift and verify recovery time under the worst CM step.
Evidence: recovery T is bounded across stress profiles.
Pass: T < X (placeholder).
Production test hooks (self-test fields and diagnostics)
Production hooks should allow the same gates used on the bench to run in fixture or field diagnostics. Prefer observable counters and margins over subjective plots.
- Tap-derived fields: ΔN, A0/A1, margin M, threshold estimate.
- Event window telemetry: event flag, recovery T, burst counter B, false detect F.
- Configuration echo: window length/latency L, AGC/clip state.
- Use A/B fixture checks to reject “settings artifacts” (same DUT, same cable model).
- Gate-based screening: DC → Tap2 → Tap3 → recovery → bursts.
Copy-ready checklist template (staged)
- Check: define Tap1/2/3 observability.
Evidence: fields available.
Pass: all present. - Check: define gates and placeholders.
Evidence: SOP list.
Pass: complete. - Check: isolation partition hypothesis.
Evidence: A/B plan.
Pass: testable.
- Check: controlled returns near Tap2/Tap3.
Evidence: no shared impedance.
Pass: review pass. - Check: symmetry at coupling nodes.
Evidence: CM→DM minimized.
Pass: review pass. - Check: clamp returns separated.
Evidence: event currents isolated.
Pass: review pass.
- Check: Gate 0 DC behavior.
Evidence: DC shift/settle.
Pass: < X / < T. - Check: Gate 1 Tap2 margin.
Evidence: ΔN, A0/A1.
Pass: ΔN < X. - Check: Gate 2 Tap3 margin.
Evidence: M.
Pass: M > Y.
- Check: recovery under events.
Evidence: T, bursts B.
Pass: T < X; B < Y. - Check: cable worst-case steps.
Evidence: ΔN/M stable.
Pass: within placeholders. - Check: fixture correlation.
Evidence: settings-trap A/B.
Pass: consistent.
Applications & IC Selection Logic
This section compresses the earlier architecture, noise, demod, and verification work into a first-pass decision system: use cases → selection axes → a decision tree → anti-overbuild rules. It intentionally avoids long product lists and focuses on measurable evidence (Tap/Gate proxies).
Use Cases (what drives the decision)
Each use case below is defined by a decision driver that maps to measurable Tap/Gate evidence.
Primary goal: keep the DC process variable stable while allowing AC FSK overlay as a controlled disturbance. Decision driver: worst-case loop impedance and transient sensitivity (DC shift / settle evidence).
Primary goal: robust demod with explainable failure signatures. Decision driver: availability of diagnostic fields (ΔN/M/T/B/F) and production/field reproducibility.
Primary goal: tolerate common-mode stress and ground shifts without losing carrier detect or mis-detecting tones. Decision driver: barrier placement and isolated-power back-injection paths (ΔN/M/T evidence under stress).
Selection Axes (measurable knobs, not slogans)
Each axis below specifies: what to look at → the trade-off → the evidence. Thresholds use placeholders (X/Y/Z) to avoid fake absolutes.
- Look: Tap2 tone-to-floor ΔN, Tap3 decision margin M
- Trade: “cleaner” filtering may increase latency and burst errors
- Evidence: Gate(ΔN > X dB), Gate(M > Y)
- Look: DC shift, injection transient, settle time
- Trade: stronger drive can disturb DC loop stability
- Evidence: Gate(DC shift < X), Gate(settle < Y)
- Look: ΔN/M/T under CM stress and ground shifts
- Trade: barrier parasitics + isolated power noise back-injection
- Evidence: A/B partition comparison (same DUT)
- Look: loop power margin and isolated-rail ripple headroom
- Trade: low power may limit DSP depth and logging richness
- Evidence: Gate pass maintained at power limit
- Look: ability to log ΔN/M/T/B/F and event recovery signatures
- Trade: richer hooks increase firmware and test complexity
- Evidence: production screening gates doable in time
- Look: “black-box” vs tunable chain, layout sensitivity
- Trade: integration saves time but may reduce debug transparency
- Evidence: sensitivity to setup traps in A/B tests
- Analog Devices AD5700 / AD5700-1
- onsemi A5191HRT
- Texas Instruments ISO7741
- Analog Devices ADuM1401
- Skyworks/Silicon Labs Si8641
- Murata NXE1S0505MC (5V→5V, 1W class)
- ADC: TI ADS7042 / ADI AD7680
- Op amp: TI OPA197 / ADI LTC2057
Notes: verify package/suffix, temperature grade, isolation rating class, and supply headroom against the project constraints.
Decision Tree: Integrated Modem vs Discrete AFE + MCU/DSP
The decision tree below produces a first-pass architecture (A/B/C). Each leaf requires evidence: ΔN (tone-to-floor), M (decision margin), T (recovery time), B (burst error proxy), F (false detect rate).
- When: fast bring-up is priority; environment is moderate; basic logs are sufficient
- Evidence: ΔN/M pass with minimal tuning; stable DC shift/settle
- Example IC: AD5700 / AD5700-1, A5191HRT
- When: noise is complex; tuning/logging is mandatory; failure must be explainable
- Evidence: ΔN/M improved without T/B regression; F reduced with calibrated thresholds
- Example parts: ADS7042 or AD7680 (ADC), OPA197 or LTC2057 (analog conditioning)
- When: strong CM/ground shift; isolation is non-negotiable; recovery is critical
- Evidence: T stays < X after stress; ΔN/M remain above thresholds
- Example parts: ISO7741 / ADuM1401 / Si8641 (isolators), NXE1S0505MC (isolated DC/DC)
- Loop impedance range (min/max) and worst-case cable condition
- Isolation requirement and expected CM / ground shift scenarios
- Power headroom (loop supply margin) and isolated-rail ripple allowance
- Target evidence gates: ΔN > X dB, M > Y, T < Z, B < W, F < V
- Required diagnostic fields for production/field logs (ΔN/M/T/B/F)
“Do Not Overbuild” Rules (failure signatures → correction)
Each rule below is written as: overbuild → signature → correction.
- Signature: spectrum looks “cleaner” but burst errors B increase; recovery T worsens
- Correction: judge by M/B/T, not only noise floor; reduce latency and window mismatch
- Signature: ΔN worsens or varies with isolated power activity; T stretches under stress
- Correction: run A/B partition tests; treat isolated power back-injection as a first-class noise path
- Signature: DC shift fails gate; settle tails appear; demod degrades after injection events
- Correction: add mute/blanking/soft-start strategy; validate stability margins after injection-network changes
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FAQs (Troubleshooting Only)
These FAQs close long-tail failures without introducing new theory. Each answer is strictly structured: Likely cause / Quick check / Fix / Pass criteria. Numeric thresholds are placeholders (X/Y/Z) and must follow the project’s budget and gates.
Same loop, different isolator方案 causes different error rates — which two coupling-path metrics to compare first?
Isolation coupling · isolated power · CM injection
RX shows high SNR but still mis-detects — what limiter/AGC artifact is most common?
Limiter · AGC pumping · window bias
Injection enabled → 4–20 mA reading shifts instantly — which DC-leak item to check first in the injection network?
DC leakage · clamp conduction · bias path
Long cable suddenly becomes unstable — verify cable capacitance/impedance first, or common-mode coupling first?
Cable model · CM pickup · margin collapse
Switching ripple increases → link drops — which two isolated-power nodes to measure first?
Isolated DC/DC · rail ripple · back-injection
After ESD, recovery takes seconds — which stage is saturating/resetting/locking?
Event recovery · saturation · deterministic reset
BPF narrower looks “cleaner” but performance worsens — how to detect group-delay/phase distortion failure?
Group delay · phase warp · margin vs prettiness
Errors happen only at certain loop currents (low/high) — which headroom issue is most common?
Headroom · bias shift · clamp region
ATE passes but the field is unstable — which missing environment/cable/CM log field is most common?
Production correlation · missing stressors · logging
Oscilloscope shows a clean tone but demod is poor — how to rule out bandwidth/coupling measurement artifacts first?
Measurement template · probe loading · false confidence
After isolation, common-mode looks cleaner but BER is worse — what barrier-capacitance coupling is typical?
Barrier C · CM→diff conversion · hidden injection
Same board, different batch behaves differently — which passive tolerances / layout parasitics to lock first?
Tolerance · parasitics · corner shift
Note: X/Y/Z thresholds must be derived from the system budget and verification gates. Avoid treating “clean-looking” waveforms as a primary pass criterion.
