Glitch-Free Clock Mux / Fan-Out for Hitless Switchover
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Glitch-free clock mux and hitless fan-out distribute clocks across multiple domains without runt pulses, missing/double cycles, or uncontrolled phase/skew steps—keeping downstream timing stable across real board, load, and temperature corners.
Definition & Scope
Glitch-free clock muxing and hitless fan-out distribution are electrical-layer functions that keep the output clock edge-legal during source selection and multi-domain routing. The goal is not “better clocks” in general, but controlled handover with measurable pass/fail criteria: no runt pulses, no unexpected missing/extra cycles (as defined by the device), bounded phase step, and predictable channel-to-channel skew.
What it is
- A clock selection + distribution block (REF A/B → mux → fan-out → domains).
- A mechanism that enforces edge legality at the output during switching.
- A tool to control skew and support multi-domain timing consistency.
What it is not
- Not a PLL/clock-cleaner tutorial (loop theory is out of scope).
- Not a PTP/SyncE/TSN timing system guide (network time is out of scope).
- Not SerDes CDR theory (refer to retimer/CDR pages if needed).
Cross-page topics should appear only as one-line pointers, never expanded here.
When you need it
- Redundant references (A/B) where the output clock must not glitch or pause.
- Multiple timing domains requiring bounded skew (FPGA + SerDes + ADC/DAC + SoC).
- Systems where an illegal edge triggers PLL unlock, frame errors, link retrain, or safety faults.
Typical “need” signal: stable steady-state but failures appear during source switching, warm reboot, or fault recovery.
Quick spec map
- Input relation: related vs unrelated (defines hitless assumptions).
- Switch behavior: no runt pulses; missing/extra cycles policy; bounded phase step (Δφ < X).
- Outputs: count N, electrical standard, load drive, per-output enable (OE).
- Skew: channel-to-channel + temperature drift (skew < Y ps, drift < Z ps/°C).
- Additive jitter: typ/max (JRMS_add < A ps in stated BW).
- Monitoring: LOS/MON, switchover flag, configuration interface (if any).
Diagram: scope boundary (two refs → glitch-free mux → fan-out → domains)
The scope boundary is source selection (SEL), edge legality / hitless behavior, monitoring (MON/LOS), and multi-domain skew control (OE/SKEW). Anything that requires loop theory or network time belongs to sibling pages.
Why Clocks Glitch (and why it is not random)
Clock “glitches” during switching are usually deterministic outcomes of asynchronous control meeting a clock edge, overlap windows between two sources, or output enable/tri-state actions near transitions. The most useful approach is to classify the failure mode first, then apply a one-step discrimination check before changing hardware or firmware.
Failure Mode 1: Asynchronous SEL competition (setup/hold violation)
Failure Mode 2: Edge coincidence / overlap (same-phase or opposite-phase hazards)
Failure Mode 3: Naive AND/OR clock gating (duty distortion, missing/extra cycles)
Failure Mode 4: Output enable / tri-state contention or release
Failure Mode 5: Frequency mismatch (“fake hitless” in unrelated sources)
Diagram: glitch generation vs clean boundary (three common implementations)
Practical discriminator (fast, high-yield)
- If errors align to SEL/OE edges within a few cycles → suspect control timing (Mode 1/4).
- If errors cluster at certain relative input edge spacing → suspect overlap hazard (Mode 2).
- If duty/period histograms form multiple discrete clusters → suspect naive gating (Mode 3).
- If output looks clean but downstream loses margin after switching → check frequency relation and bounded phase step (Mode 5).
Architectures (Mux, Switchover, Fan-Out, Crosspoint, Clock Matrix)
Interface clock parts use many names, but they reduce to a small set of engineering structures. The correct choice is determined by input relationship (related vs unrelated), required switching behavior (hitless definition), output count, and whether channel-to-channel skew must be controlled.
Glitch-Free Mux (N→1)
- Purpose: select one clock source without illegal output edges.
- Best case: inputs are related (same origin / bounded drift).
- Unrelated inputs: edge legality can be guaranteed, but phase continuity cannot unless explicitly specified (bounded phase step Δφ < X).
Hitless Switchover (A/B redundancy)
- Policy: active/standby, priority, manual/automatic control.
- Health: input-present/LOS, freq_ok, phase_ok (device-defined windows).
- Stability: deglitch/debounce avoids oscillating switches on noisy LOS.
- Logging: switchover flag/interrupt supports correlation and production screening.
Fan-Out Buffer (1→N distribution)
- Purpose: replicate a clock with controlled edge integrity across domains.
- Skew: fixed vs adjustable per-output delay (skew < Y ps; drift < Z ps/°C).
- Optional functions: divide-by, duty correction (treated as a measurable behavior, not a loop tutorial).
- Standards: common outputs include LVCMOS/LVDS/LVPECL/HCSL (impedance/termination impacts the edge).
Crosspoint / Clock Matrix (M×N routing)
- Purpose: route multiple inputs to multiple outputs (multi-board or multi-subsystem distribution).
- Constraint: switching rules become stricter; monitoring and policy matter more than raw muxing.
- Risk: more routing freedom increases configuration and validation surface area.
Architecture → Engineering constraints (high-signal map)
| Structure | Input relation assumption | Hitless capability (definition-dependent) | Skew control & domains | Monitoring & controls |
|---|---|---|---|---|
| Glitch-Free Mux | Related inputs preferred; unrelated inputs require explicit phase-step/pause assumptions. | “No runt pulses” is the baseline; phase continuity must be stated separately (Δφ < X). | Typically single output; used before a fan-out when multi-domain skew matters. | SEL, switchover flag, input-present/LOS (if supported). |
| Hitless Switchover | Often assumes same nominal frequency; “hitless” must specify related/unrelated case. | Includes policy + health qualification; may allow bounded pause time (pause < X). | Usually a single stabilized output feeding fan-out or a clock tree. | LOS, freq_ok/phase_ok, priority pins/regs, event flag/interrupt. |
| Fan-Out Buffer | Inherits the upstream clock relation; focuses on replicating edges consistently. | Not a switchover device; validates additive jitter and output enable behavior. | Channel skew and drift define multi-domain timing consistency. | Per-output OE, optional delay/phase trim, sometimes output fault flags. |
| Crosspoint / Matrix | Mixed; routing freedom demands explicit per-route assumptions and validation. | Hitless can be route-dependent; “clean boundary” requires enforced switching rules. | Often supports per-output delay; skew planning becomes a configuration task. | Rich config, status flags, and logging are mandatory for debugging/production. |
This map selects the architecture class only. Detailed part selection (numbers, thresholds, thermal/power) belongs to the dedicated selection chapter.
Diagram: architecture family & decision tree (input → relation → hitless → outputs → skew)
The decision tree places input relationship first, because that constraint determines what “hitless” can mean in practice. Output count and skew control appear as a parallel branch (fan-out), since distribution quality is a separate, measurable requirement.
What “Hitless” Means (Measurable Acceptance Metrics)
“Hitless” must be interpreted as a verification contract, not a marketing label. A compliant design states the assumptions (related vs unrelated, same frequency, allowed pause) and passes a repeatable measurement set: edge legality, cycle accounting, bounded phase step, and bounded switching time.
Metric 1: No runt pulses
Observe: high-bandwidth capture with correct termination and persistence.
Fail: any pulse width < X (min high/low width) or any extra edge.
Note: a “tiny” spike can be a logical edge at the receiver threshold.
Metric 2: No extra/missing cycle
Observe: edge-count consistency (waveform + counter/time-stamp correlation).
Fail: double-edge or skipped edge during the switchover window.
Note: “frequency looks right” can still hide cycle-accounting failures.
Metric 3: Bounded phase step (Δφ)
Observe: phase/time-interval error step at switchover.
Fail: Δφ > X (or TIE step > Y).
Assumption: unrelated inputs usually cannot guarantee continuity; only a bounded boundary can be specified.
Metric 4: Switching time bounds
Observe: SEL/LOS event → stable output (latency) and any pause window.
Fail: latency > X or pause > Y (if pause is not allowed).
Note: devices may be “glitch-free” but still allow a short pause; that must be explicitly stated.
Diagram: hitless acceptance waveforms (✔/✘ quick visual contract)
Minimal acceptance set (repeatable and production-friendly)
- Edge legality: no runt pulses and no extra edges (Metric 1).
- Cycle accounting: no missing/extra cycles in the switch window (Metric 2).
- Phase boundary: bounded phase step (Δφ < X) or explicitly allowed pause (pause < Y).
- Time bounds: switching latency < Z and stable output after the event.
The Switching State Machine (Control Logic That Makes SEL Safe)
A hitless design treats SEL as a request, not an immediate mux action. The output can switch only after synchronization, input qualification, an alignment strategy, a controlled handover, and a post-switch verification step. This prevents runt pulses, missing/extra cycles, and uncontrolled phase steps.
1) SEL synchronization & handshake
- Goal: eliminate asynchronous competition with clock edges.
- Minimum: 2-FF sync for single-bit control; optional req/ack for robust control.
- Debounce: prevent SEL chatter that causes repeated switching.
Log hook: sel_req_ts / sel_ack_ts (timestamp placeholders).
2) Input qualification (present / amplitude / frequency)
- Present (LOS): detect missing/invalid input with debounce and hysteresis.
- Amplitude/CM: verify signal margin at the receiver input (standard-dependent).
- Frequency window: qualify ppm / divider ratio before alignment.
- Stability: require stable_for > T before ALIGN (T is a placeholder).
Pass: los=0, freq_ok=1, amp_ok=1 for ≥ T.
3) Alignment strategy (edge / cycle / divider)
- Edge align: best when inputs are related; supports bounded phase step (Δφ < X).
- Cycle align: prioritizes correct edge counts; may allow a defined phase boundary.
- Divider align: required if downstream relies on divider phase; must define timeout.
- Unrelated inputs: phase continuity is not guaranteed; specify bounded Δφ or allowed pause.
Pass: phase_ok=1 (or pause < Y) before SWITCH.
4) Handover + failure behavior
- Break-before-make: avoids overlap/contension; may introduce pause (pause < Y).
- Make-before-break: reduces pause risk but can create overlap hazards (runt/double edges).
- Hold-last / freeze: defined output behavior when both inputs fail (system must accept it).
- Event flags: start/done/fail for correlation and production screening.
Pass: no runt pulses; no missing/extra cycles; latency < Z (placeholders).
Diagram: switching state machine (LOCK A → PREPARE → ALIGN → SWITCH → VERIFY → LOCK B)
Minimal control contract (placeholders)
- Allow switching only when qual_ok=1 for ≥ T and phase_ok=1 (or pause is explicitly allowed).
- Bound the event: latency < X, pause < Y, Δφ < Z.
- Emit flags: sw_start, sw_done, sw_fail (for correlation and production gating).
Skew, Phase, and Domain Alignment (What Multi-Domain Distribution Buys)
Multi-domain clock distribution succeeds only when skew is controlled and predictable. Skew is not a single number; it is a budget composed of device channel mismatch, PCB routing mismatch, load sensitivity, and temperature/voltage drift. A correct design tracks both static skew and dynamic skew across operating corners.
Skew components (budget view)
- IC channel: output-to-output mismatch inside the fan-out.
- Trace: routing length/impedance mismatch on the PCB.
- Load: termination and receiver loading change edge timing.
- Temp/V: drift across temperature and supply variation.
Model: total_skew = Σ(parts)
Static vs dynamic skew
- Static: same corner, fixed load — baseline channel alignment.
- Dynamic: corner drift (hot/cold, Vmin/Vmax, load changes) — the usual field failure root.
Risk: “passes at room” but fails after warm-up or configuration changes.
Per-output delay adjust (boundaries)
- Step: delay_step = X ps (placeholder).
- Monotonic: delay code should move the edge in one direction (or specify exceptions).
- Default: power-up codes must be known and repeatable.
- Range: min/max delay must cover PCB mismatch with margin.
Pass: trim repeatability < Y ps (placeholder) across corners.
Duty-cycle distortion (DCD) & phase planning
- DCD: changes threshold crossing time and edge sensitivity.
- Metric: duty = 50% ± X% (placeholder).
- In-phase: align edges across domains for coherent sampling/triggering.
- Intentional shift: controlled phase offsets for setup/hold margin planning.
Diagram: skew budget (stacked components → total skew pass criteria)
The stacked budget forces worst-case thinking: if any component is uncontrolled (especially drift), multi-domain alignment will degrade even when typical room-temperature skew looks acceptable.
Clock Integrity Budget (Jitter, Duty, Noise, and Measurement Traps)
Clock integrity must be expressed as a budget with reproducible measurement conditions. A mux/fan-out path adds jitter and can shift threshold crossing time under load, supply ripple, or bandwidth-limited measurements. Without locked settings and logged conditions, “better numbers” can be a measurement artifact.
Budget model (what must be bounded)
- Additive jitter: mux/fan-out introduce incremental jitter on top of the input.
- Edge sensitivity: duty and threshold crossing depend on load, termination, and supply noise.
- Budget form: J_out = f(J_in) + J_add(mux) + J_add(fanout) + margin.
Pass (placeholder): J_out(RMS@BW) < X and duty = 50% ± Y%.
RMS vs pk-pk (statistical misuse)
- pk-pk drifts: pk-pk typically increases with longer capture windows (rare events appear).
- RMS budgets: RMS is better for margin tracking, but only under fixed BW and filters.
- Quick check: change capture length; if pk-pk “improves” only by reducing samples, it is not a real improvement.
Record: Ncycles / capture_time / histogram mode (placeholders).
Bandwidth, RBW/VBW, and gating (false “improvements”)
- Bandwidth limit: low BW can hide real edge noise and make jitter appear smaller.
- RBW/VBW knobs: spur visibility and “noise floor” can change with RBW/VBW settings.
- Threshold/gates: exclusions and histo gates can remove worst cases and shrink numbers.
- Quick check: compare results under two BW settings and two gate settings; large swings indicate artifacts.
Pass: delta under config change < X (placeholder); config must be locked for comparisons.
Trigger jitter vs true edge jitter
- Trigger chain: external trigger routing or reflections can “stabilize” the display while edges drift.
- Recovery modes: analyzer recovery/averaging can hide rare boundary failures.
- Quick check: measure with two trigger references; disagreement indicates trigger/reference artifacts.
Record: trigger_source / timebase_mode / ref_in (placeholders).
Reproducibility log fields (minimum set)
Environment
- Temperature: T (placeholder)
- Supply ripple: V_ripple (placeholder)
- Input amplitude: Vin_amp (placeholder)
Load & termination
- N_load (placeholder)
- Termination type (placeholder)
- Cable/fixture (placeholder)
Instrument config
- BW / RBW / VBW / filter (placeholders)
- Gate/threshold + capture length (placeholders)
- Trigger source + ref mode (placeholders)
Pass (placeholder): identical DUT results under locked config; Δ(jitter/duty) < X across repeated captures.
Diagram: measurement chain with traps (loading, termination, bandwidth)
Pass (placeholder): results remain consistent after changing probe method and bandwidth within a defined range; Δ < X.
Layout, Power, and Real-World Failure Modes (Board-Level Reality)
A theoretically hitless switch can fail on the board when power noise, return-path discontinuities, poor termination, or split nodes create reflections and threshold drift. Distribution stability depends on controlled impedance, clean return current paths, and a load plan that prevents edge and delay drift under fan-out changes.
Power noise & switching transients
- PSRR ≠ immunity: supply ripple can modulate threshold and delay.
- Event spikes: switching edges can cause ground bounce and local droop.
- Log fields: V_ripple@switch, V_drop, ground_bounce (placeholders).
Pass (placeholder): supply ripple below X and no edge shift beyond Y under switchover.
Return current paths (differential vs single-ended)
- Plane continuity: splits and reference changes force return detours.
- Common-mode risk: broken return paths increase coupling and edge uncertainty.
- Quick check: avoid crossing plane gaps under clock pairs; minimize layer transitions.
Pass (placeholder): continuous reference plane and controlled return under the clock route.
Termination & reflection sensitivity
- Where termination sits: source vs receiver vs mid-point changes the reflection pattern.
- Reflection can mimic glitches: ringing can create double-threshold crossings.
- Quick check: identify reflection point (often the split node or long stub).
Pass (placeholder): reflection amplitude < X and ringing settles within Y.
Split nodes, stubs, and length matching
- Long stubs: create strong reflections and can break hitless boundaries.
- Branch control: prefer controlled star points with short, matched branches.
- Placeholders: stub_length < X, pair_match < Y.
Fan-out loading changes (dynamic drift)
- N_load variations: edge rate and delay change with connected loads.
- Timing drift: load-dependent threshold crossing shifts skew over time/configuration.
- Log fields: N_load, OE states, connector population (placeholders).
Pass (placeholder): total_skew < X across worst-case load combinations.
Diagram: PCB return path + split node (Bad vs Good)
Use the same measurement chain discipline from H2-7 when validating routing fixes: reflections and return-path issues can be hidden by bandwidth limits or incorrect probing.
Protection & Robustness (ESD, EMI, Fault Tolerance, Redundancy)
Protection must preserve clock integrity. Any ESD/EMI measure is acceptable only if it does not materially change amplitude, duty, jitter, or skew under the locked measurement conditions defined in the integrity budget.
Input protection (keep the edge intact)
- ESD path: keep the discharge loop short; avoid injecting ground bounce into the clock input.
- Cap/leak risk: excess input capacitance can slow the edge and shift crossing time.
- Sanity check: compare Vin_amp and J_out before/after protection under the same config.
Pass (placeholder): ΔVin_amp within X and ΔJ_out(RMS@BW) < Y.
Output protection (series R / RC edge shaping)
- Benefit: reduces reflection spikes and radiated emissions.
- Risk: slower edges can increase threshold sensitivity, DCD impact, and timing drift.
- Decision rule: accept only if jitter/duty/skew remain within the budget across load and temperature.
Pass (placeholder): duty = 50% ± X% and J_out increase < Y under worst-case N_load.
Redundancy (dual input / dual supply isolation)
- Fault must not propagate: a failing path must not clamp or corrupt the healthy path.
- Isolation points: define where the system separates A/B inputs and supply domains.
- Event proof: correlate switchover flags with downstream stability metrics.
Pass (placeholder): fault-injected A does not degrade B beyond ΔJ < X and no false switch.
LOS/LOL usability (false triggers and debounce)
- False LOS: noise or amplitude margin can chatter near thresholds.
- Debounce/hysteresis: required to prevent oscillating switchover events.
- Log fields: LOS duration, debounce time, false_switch_rate (placeholders).
Pass (placeholder): false_switch_rate < X and LOS stable for ≥ T before switching.
EMI trade (edge rate vs emissions)
- Edge rate drives EMI: slowing edges can reduce emissions but changes timing sensitivity.
- Budget verification: any edge shaping must be re-validated for jitter/duty/skew and system correlation.
- Corner test: validate at hot/cold and max load; EMI fixes often fail at corners.
Pass (placeholder): EMI improvement achieved with ΔJ_out < X and no downstream error-rate increase.
Diagram: protection placement overlay (where protection belongs)
Verification & Bring-Up (From Bench Pass to System Proof)
Bring-up must establish a reproducible evidence chain: input qualification → output integrity → scripted switching sweep → downstream correlation → root-cause assignment. Measurements must be compared only under locked instrument configuration.
1) Pre-check (before power-on)
Action
- Confirm input standard + termination strategy (placeholder).
- Confirm routing constraints: no long stubs; controlled split node.
- Fix N_load and connector population for baseline.
Log
- Vin_amp, freq, termination type (placeholders).
- Instrument config: BW/RBW/VBW, gate, capture length (placeholders).
- Trigger source + ref mode (placeholders).
Pass
- Vin_amp > X and freq_ok=1 (placeholders).
- termination_ok=1 and baseline J_out < Y (placeholders).
2) Switch test (scripted, statistical, cornered)
Action
- Execute A→B→A sweeps with fixed interval (placeholder).
- Force LOS events (controlled) to validate state machine response.
- Repeat at hot/cold and Vmin/Vmax; include max N_load.
Log
- Counts: runt, missing, double (placeholders).
- Latency, pause, Δφ distributions (placeholders).
- Event flags: sw_start/sw_done/sw_fail (timestamps).
Pass
- 0 runt; 0 missing/double (placeholders).
- sw_fail_rate < X; latency < Y; pause < Z (placeholders).
- Δφ bounded < W (or pause allowed < V) (placeholders).
3) System correlation (downstream proof)
Action
- Align downstream logs to sw_start/sw_done timestamps.
- Compare error rate inside vs outside switch windows.
- Repeat correlation under corner conditions and load changes.
Log
- FPGA: lock flag, error counters (placeholders).
- SerDes: link drop, CRC, retry (placeholders).
- ADC/SoC: sync loss, frame slip (placeholders).
Pass
- No error-rate spike at switchover beyond X (placeholder).
- Downstream lock remains stable across repeated sweeps.
Diagram: bring-up flow (evidence chain)
Pass (placeholders): no runt/missing/double; bounded latency/pause/Δφ; no downstream error spike aligned to switchover windows.
Engineering Checklist (Design → Bring-up → Production)
This checklist compresses the full page into executable gates. Every item is written as: Check (do) → Record (log) → Pass (threshold placeholders). Comparisons are valid only under a locked measurement configuration.
Design (gates before PCB release)
Input assumptions
Check: define related/unrelated, same-frequency assumption, and allowed phase step/pause.
Record: fA/fB, relation, allowed_Δφ, allowed_pause (placeholders).
Pass: relation matches use-case; allowed_Δφ ≤ X; allowed_pause ≤ Y (placeholders).
Switch control integrity
Check: SEL is never directly muxed; switching must be state-machine qualified (sync, qualify, align, verify).
Record: SEL_sync_mode, debounce, timeout, sw_flags (placeholders).
Pass: no runt/missing/double in acceptance waveforms; sw_fail_rate < X (placeholders).
Skew budget (multi-domain)
Check: budget skew as IC_channel + routing + load + temp drift; plan calibration if delay steps exist.
Record: skew_ic, skew_trace, skew_load, skew_temp, step_ps (placeholders).
Pass: total_skew < X ps; drift < Y ps/°C (placeholders).
Board-level gates
Check: no long stubs; controlled split node; defined return path; power transient containment at switching edges.
Record: stub_mm, split_topology, return_ok, PDN_ripple (placeholders).
Pass: stub < X mm; PDN_ripple < Y mVpp at switchover (placeholders).
Bring-up (bench proof → system proof)
Locked measurement config
Check: lock BW/RBW/VBW, gate, capture length, trigger strategy; keep identical for comparisons.
Record: config_hash, BW/RBW/VBW, gate, capture_len (placeholders).
Pass: config_hash matches across all A/B and before/after changes.
Baseline (no switching)
Check: establish J_out, duty, and skew baselines at nominal load and corners.
Record: J_RMS@BW, duty%, skew_ps, T/V/N_load (placeholders).
Pass: within budget: J_RMS < X, duty = 50% ± Y%, skew < Z (placeholders).
Scripted switch sweep
Check: run A→B→A sweeps; inject controlled LOS; count runt/missing/double; repeat across corners.
Record: switch_count, interval, runt/missing/double counts, sw_latency, pause (placeholders).
Pass: runt=0; missing=0; double=0; sw_fail_rate < X (placeholders).
Downstream correlation
Check: align sw_start/sw_done timestamps to FPGA/SerDes/ADC lock and error counters.
Record: lock_flags, CRC/errors, frame_slip, timebase (placeholders).
Pass: no error-rate spike inside the switch window beyond X (placeholder).
Production (repeatable yield and traceability)
Fixture invariance
Check: keep termination, cables, and probe method fixed; station-to-station variance must be bounded.
Record: fixture_id, cable_id, term_type, config_hash (placeholders).
Pass: station_delta(J/skew/duty) < X (placeholder).
Fast screens (most lethal failures)
Check: detect runt/missing/double during a short switch burst; verify LOS behavior is non-chattering.
Record: burst_count, runt_detect, LOS_events, false_switch_rate (placeholders).
Pass: 0 runt; 0 missing/double; false_switch_rate < X (placeholder).
Distribution monitoring
Check: track statistical drift of J_out/skew/duty (P50/P95/P99) and alarm trends.
Record: histogram_id, P50/P95/P99, drift_per_week (placeholders).
Pass: P99 < thresholds; drift < X/week (placeholders).
Suggested logged fields (placeholders): timebase_id, config_hash, f_in, Vin_amp, T, V, N_load, sw_latency, pause, Δφ, runt/missing/double counters, LOS/LOL counters.
Diagram: checklist pipeline (low-noise summary)
Applications & IC Selection Notes (How to Choose)
Selection is driven by three facts: (1) input relationship and switching assumptions, (2) output fan-out and skew control requirements, and (3) measurable hitless criteria under a locked measurement configuration. Internal PLL/DPLL theory is intentionally out of scope; features are treated as black-box capabilities.
Redundant reference A/B
Prioritize LOS/LOL reliability, debounce, event flags, and a defined hitless grade (no runt / no missing/double / bounded pause or phase step).
Multi-domain distribution
Prioritize channel-to-channel skew, temperature drift, optional per-output delay steps, and stable defaults at power-up.
EMI-sensitive systems
Edge shaping (series R/RC) is acceptable only if jitter/duty/skew remain within budget across corners and max load.
Field diagnostics
Prefer parts with readable status/flags (LOS, switchover cause, counters) and deterministic behavior on input loss.
Selection Matrix (Requirement → Device capability → Acceptance)
Inputs: single vs dual, related vs unrelated
Capability: selectable inputs + input-present detection (LOS/clock detect) + defined behavior when one input stops.
Acceptance: LOS is stable (no chatter) and switchover does not violate hitless grade (placeholders).
Example MPNs: Renesas/IDT ICS580-01 (glitch-free mux + clock detect), Renesas/IDT ICS581-02 (auto switch, zero-delay, PLL-based).
Hitless grade: no runt / no missing/double / bounded pause or phase step
Capability: qualified switching (state machine), optional holdover, event flags.
Acceptance: runt=0, missing=0, double=0; latency < X; pause < Y; Δφ < Z (placeholders).
Example MPNs: TI LMK04228 (redundant inputs, hitless switching/LOS, holdover), Renesas/IDT ICS581-01 (user-controlled switching).
Outputs: N-way fan-out and output standards
Capability: 1→N distribution, stable OE behavior, format support, low skew specification.
Acceptance: channel-to-channel skew < X ps; duty within ±Y%; additive jitter within budget (placeholders).
Example MPNs: TI LMK00101 (fanout buffer/level translation), Renesas 852911I (1-to-9 fanout, two selectable inputs), Microchip PL138-28 (1-to-2 differential fanout).
Skew control: per-output delay and deskew plan
Capability: programmable skew/delay steps or external deskew elements; deterministic power-up defaults.
Acceptance: step size known; monotonicity verified; total_skew < X; drift < Y (placeholders).
Example MPNs: TI CDCE18005 (fan-out mode with divide and skew control), Infineon CY7B991V (programmable skew clock buffer), onsemi MC100EP196 (programmable delay for deskew).
Control/monitor and traceability
Capability: SEL/OE, LOS/LOL, switchover flag, optional I²C/SPI config/status.
Acceptance: events are timestampable; false switches bounded; logs reproduce failures (placeholders).
Example MPNs: TI LMK04228 (status and clock switching modes), Renesas/IDT ICS580-01 (clock detect and automatic switch option).
Power/thermal and robustness check items
Capability: per-output enable, predictable current draw, package thermal headroom; ESD/EMI design guidance can be executed at PCB level.
Acceptance: per-Gbps or per-output power within limit; temperature drift remains within skew/jitter budget (placeholders).
Example MPNs: validate in context; verify package/suffix/availability for all listed devices.
MPN note: example material numbers are provided as capability anchors. Always verify datasheet revision, package suffix, temperature grade, and supply constraints before committing.
Diagram: selection matrix (needs → features)
Concrete material numbers (examples; verify suffix/package/availability)
Glitch-free mux (non-PLL)
- ICS580-01 (clock detect; manual/auto switch option)
Zero-delay glitch-free mux (PLL-based)
- ICS581-01 (user-controlled switching)
- ICS581-02 (automatic switching)
Redundant input + hitless switching (conditioning-class)
- LMK04228 (redundant inputs, hitless/LOS, holdover)
Fan-out buffers (distribution anchors)
- LMK00101 (fanout buffer / level translation)
- 852911I (1-to-9 fanout; two selectable inputs)
- PL138-28 (1-to-2 differential fanout buffer)
Skew / deskew elements
- CDCE18005 (fan-out mode with divide + skew control)
- CY7B991V (programmable skew clock buffer)
- MC100EP196 (programmable delay chip for deskew)
Procurement guardrail
Record and lock: package suffix, temp grade, supply range, default state, and configuration method. Do not mix “similar-looking” substitutes without re-running the switch sweep and skew/jitter baselines.
Pass criteria placeholders: additive jitter ΔJ_RMS@BW < X, duty = 50% ± Y%, total_skew < Z ps, false_switch_rate < W, runt/missing/double = 0 (placeholders).
Engineering Checklist (Design → Bring-up → Production)
This checklist compresses the full page into executable gates. Every item is written as: Check (do) → Record (log) → Pass (threshold placeholders). Comparisons are valid only under a locked measurement configuration.
Design (gates before PCB release)
Input assumptions
Check: define related/unrelated, same-frequency assumption, and allowed phase step/pause.
Record: fA/fB, relation, allowed_Δφ, allowed_pause (placeholders).
Pass: relation matches use-case; allowed_Δφ ≤ X; allowed_pause ≤ Y (placeholders).
Switch control integrity
Check: SEL is never directly muxed; switching must be state-machine qualified (sync, qualify, align, verify).
Record: SEL_sync_mode, debounce, timeout, sw_flags (placeholders).
Pass: no runt/missing/double in acceptance waveforms; sw_fail_rate < X (placeholders).
Skew budget (multi-domain)
Check: budget skew as IC_channel + routing + load + temp drift; plan calibration if delay steps exist.
Record: skew_ic, skew_trace, skew_load, skew_temp, step_ps (placeholders).
Pass: total_skew < X ps; drift < Y ps/°C (placeholders).
Board-level gates
Check: no long stubs; controlled split node; defined return path; power transient containment at switching edges.
Record: stub_mm, split_topology, return_ok, PDN_ripple (placeholders).
Pass: stub < X mm; PDN_ripple < Y mVpp at switchover (placeholders).
Bring-up (bench proof → system proof)
Locked measurement config
Check: lock BW/RBW/VBW, gate, capture length, trigger strategy; keep identical for comparisons.
Record: config_hash, BW/RBW/VBW, gate, capture_len (placeholders).
Pass: config_hash matches across all A/B and before/after changes.
Baseline (no switching)
Check: establish J_out, duty, and skew baselines at nominal load and corners.
Record: J_RMS@BW, duty%, skew_ps, T/V/N_load (placeholders).
Pass: within budget: J_RMS < X, duty = 50% ± Y%, skew < Z (placeholders).
Scripted switch sweep
Check: run A→B→A sweeps; inject controlled LOS; count runt/missing/double; repeat across corners.
Record: switch_count, interval, runt/missing/double counts, sw_latency, pause (placeholders).
Pass: runt=0; missing=0; double=0; sw_fail_rate < X (placeholders).
Downstream correlation
Check: align sw_start/sw_done timestamps to FPGA/SerDes/ADC lock and error counters.
Record: lock_flags, CRC/errors, frame_slip, timebase (placeholders).
Pass: no error-rate spike inside the switch window beyond X (placeholder).
Production (repeatable yield and traceability)
Fixture invariance
Check: keep termination, cables, and probe method fixed; station-to-station variance must be bounded.
Record: fixture_id, cable_id, term_type, config_hash (placeholders).
Pass: station_delta(J/skew/duty) < X (placeholder).
Fast screens (most lethal failures)
Check: detect runt/missing/double during a short switch burst; verify LOS behavior is non-chattering.
Record: burst_count, runt_detect, LOS_events, false_switch_rate (placeholders).
Pass: 0 runt; 0 missing/double; false_switch_rate < X (placeholder).
Distribution monitoring
Check: track statistical drift of J_out/skew/duty (P50/P95/P99) and alarm trends.
Record: histogram_id, P50/P95/P99, drift_per_week (placeholders).
Pass: P99 < thresholds; drift < X/week (placeholders).
Suggested logged fields (placeholders): timebase_id, config_hash, f_in, Vin_amp, T, V, N_load, sw_latency, pause, Δφ, runt/missing/double counters, LOS/LOL counters.
Diagram: checklist pipeline (low-noise summary)
Applications & IC Selection Notes (How to Choose)
Selection is driven by three facts: (1) input relationship and switching assumptions, (2) output fan-out and skew control requirements, and (3) measurable hitless criteria under a locked measurement configuration. Internal PLL/DPLL theory is intentionally out of scope; features are treated as black-box capabilities.
Redundant reference A/B
Prioritize LOS/LOL reliability, debounce, event flags, and a defined hitless grade (no runt / no missing/double / bounded pause or phase step).
Multi-domain distribution
Prioritize channel-to-channel skew, temperature drift, optional per-output delay steps, and stable defaults at power-up.
EMI-sensitive systems
Edge shaping (series R/RC) is acceptable only if jitter/duty/skew remain within budget across corners and max load.
Field diagnostics
Prefer parts with readable status/flags (LOS, switchover cause, counters) and deterministic behavior on input loss.
Selection Matrix (Requirement → Device capability → Acceptance)
Inputs: single vs dual, related vs unrelated
Capability: selectable inputs + input-present detection (LOS/clock detect) + defined behavior when one input stops.
Acceptance: LOS is stable (no chatter) and switchover does not violate hitless grade (placeholders).
Example MPNs: Renesas/IDT ICS580-01 (glitch-free mux + clock detect), Renesas/IDT ICS581-02 (auto switch, zero-delay, PLL-based).
Hitless grade: no runt / no missing/double / bounded pause or phase step
Capability: qualified switching (state machine), optional holdover, event flags.
Acceptance: runt=0, missing=0, double=0; latency < X; pause < Y; Δφ < Z (placeholders).
Example MPNs: TI LMK04228 (redundant inputs, hitless switching/LOS, holdover), Renesas/IDT ICS581-01 (user-controlled switching).
Outputs: N-way fan-out and output standards
Capability: 1→N distribution, stable OE behavior, format support, low skew specification.
Acceptance: channel-to-channel skew < X ps; duty within ±Y%; additive jitter within budget (placeholders).
Example MPNs: TI LMK00101 (fanout buffer/level translation), Renesas 852911I (1-to-9 fanout, two selectable inputs), Microchip PL138-28 (1-to-2 differential fanout).
Skew control: per-output delay and deskew plan
Capability: programmable skew/delay steps or external deskew elements; deterministic power-up defaults.
Acceptance: step size known; monotonicity verified; total_skew < X; drift < Y (placeholders).
Example MPNs: TI CDCE18005 (fan-out mode with divide and skew control), Infineon CY7B991V (programmable skew clock buffer), onsemi MC100EP196 (programmable delay for deskew).
Control/monitor and traceability
Capability: SEL/OE, LOS/LOL, switchover flag, optional I²C/SPI config/status.
Acceptance: events are timestampable; false switches bounded; logs reproduce failures (placeholders).
Example MPNs: TI LMK04228 (status and clock switching modes), Renesas/IDT ICS580-01 (clock detect and automatic switch option).
Power/thermal and robustness check items
Capability: per-output enable, predictable current draw, package thermal headroom; ESD/EMI design guidance can be executed at PCB level.
Acceptance: per-Gbps or per-output power within limit; temperature drift remains within skew/jitter budget (placeholders).
Example MPNs: validate in context; verify package/suffix/availability for all listed devices.
MPN note: example material numbers are provided as capability anchors. Always verify datasheet revision, package suffix, temperature grade, and supply constraints before committing.
Diagram: selection matrix (needs → features)
Concrete material numbers (examples; verify suffix/package/availability)
Glitch-free mux (non-PLL)
- ICS580-01 (clock detect; manual/auto switch option)
Zero-delay glitch-free mux (PLL-based)
- ICS581-01 (user-controlled switching)
- ICS581-02 (automatic switching)
Redundant input + hitless switching (conditioning-class)
- LMK04228 (redundant inputs, hitless/LOS, holdover)
Fan-out buffers (distribution anchors)
- LMK00101 (fanout buffer / level translation)
- 852911I (1-to-9 fanout; two selectable inputs)
- PL138-28 (1-to-2 differential fanout buffer)
Skew / deskew elements
- CDCE18005 (fan-out mode with divide + skew control)
- CY7B991V (programmable skew clock buffer)
- MC100EP196 (programmable delay chip for deskew)
Procurement guardrail
Record and lock: package suffix, temp grade, supply range, default state, and configuration method. Do not mix “similar-looking” substitutes without re-running the switch sweep and skew/jitter baselines.
Pass criteria placeholders: additive jitter ΔJ_RMS@BW < X, duty = 50% ± Y%, total_skew < Z ps, false_switch_rate < W, runt/missing/double = 0 (placeholders).
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FAQs (Troubleshooting, within switching/skew/jitter/measurement/board scope)
Each FAQ is intentionally short and executable. Every answer uses the same 4-line structure and ends with measurable pass criteria (threshold placeholders).
Switching occasionally causes downstream PLL unlock — check runt pulses or excessive phase step first? Focus: hitless criteria vs bounded phase continuity (no new PLL theory).
Likely cause: (1) electrical violation at boundary (runt/missing/double), or (2) phase step/pause exceeds the downstream tolerance.
Quick check: capture a switch window with persistence + runt/missing/double counters; then correlate sw_start/sw_done to PLL unlock timestamp to estimate Δφ and pause.
Fix: enforce qualified switching (sync+qualify+align+verify); tighten LOS debounce; constrain allowed phase step; reduce PDN ripple during switchover.
Pass criteria: runt=0; missing=0; double=0; |Δφ| ≤ X; pause ≤ Y; sw_latency ≤ Z (placeholders).
A/B are same frequency but switching still drops a cycle — SEL sync or input qualification logic? Focus: control path integrity (SEL) vs qualify chatter (LOS/freq_ok).
Likely cause: (1) SEL changes too close to a clock edge (insufficient sync/handshake), or (2) qualify/freq_ok/LOS chatters and forces re-entry to switching.
Quick check: log SEL transitions and qualify/LOS flags at high rate; verify SEL is double-synchronized or handshake-latched; check if cycle drop aligns with qualify toggles.
Fix: add SEL synchronization and minimum-hold time; widen qualification window; add debounce/hysteresis; require stable input for ≥ X cycles before switching (placeholder).
Pass criteria: SEL is never asynchronous at the mux boundary; qualify does not chatter; sw_fail_rate < X; missing cycles=0 over N switches (placeholders).
Switching fails only at max fan-out load — is edge slowing making thresholds sensitive? Where to probe first? Focus: load-dependent edge rate, duty distortion, termination sensitivity.
Likely cause: heavy load changes rise/fall, crossing point, duty, and reflection behavior; the “switch boundary” becomes marginal only under max loading.
Quick check: compare light-load vs max-load at the same measurement config: rise/fall, duty%, eye height, and runt statistics inside the switch window; probe at the fan-out output and at a far-end receiver.
Fix: correct termination topology; reduce stubs; buffer or segment loads; adjust output drive/slew if available; re-validate with max load.
Pass criteria: at N_load=max: runt=0; missing/double=0; duty=50% ± X%; J_RMS@BW ≤ Y; skew_total ≤ Z (placeholders).
Hitless in the lab, but occasional glitches in the chassis — power ripple, return path, or crosstalk first? Focus: board-level reality (PDN/return/crosstalk) without leaving this page.
Likely cause: chassis conditions add PDN ripple/transients, return-path discontinuities, or aggressor activity that modulates the switching boundary.
Quick check: time-align sw_event with (a) PDN ripple at the clock IC rails, (b) ground bounce reference, and (c) aggressor activity; prioritize the strongest correlation.
Fix: tighten PDN (local decoupling, via/plane integrity); restore return continuity; increase spacing/shielding; re-check termination at chassis harness points.
Pass criteria: sw_window PDN_ripple ≤ X mVpp; runt=0; missing/double=0; downstream error-rate increase ≤ Y (placeholders).
One output suddenly shows much larger skew — routing, load, temperature drift, or channel config first? Focus: isolate by swapping (channel vs load vs route) and quantify drift.
Likely cause: (1) mis-configured per-output delay/deskew, (2) load/termination change, (3) routing/connector change, or (4) temperature/voltage drift.
Quick check: swap outputs (keep routing fixed) to see if the skew follows the channel; then swap loads/terminations; finally sweep temperature to measure drift slope.
Fix: reset and lock delay settings; normalize loads/terminations; correct routing mismatches; add calibration step at bring-up if drift matters.
Pass criteria: Δskew(ch_i-ch_ref) ≤ X ps; drift ≤ Y ps/°C; repeatability (3 runs) ≤ Z ps (placeholders).
No glitch visible on the oscilloscope, but the system still errors — trigger limits, bandwidth, or probe loading? Focus: measurement “false good” traps (BW/trigger/probing).
Likely cause: limited bandwidth or trigger strategy hides rare runt pulses; probe/fixture loading reshapes the edge; termination mismatch filters the event.
Quick check: lock a config_hash (BW, trigger, capture length) and enable persistence; use runt/glitch trigger or statistical counters; verify with proper 50Ω/100Ω termination and minimal loading.
Fix: increase effective bandwidth; change trigger to runt/timeout; reduce probe capacitance/lead inductance; fix termination and fixture repeatability.
Pass criteria: under locked config_hash: runt_count=0 over capture ≥ X s; station_delta ≤ Y; termination verified (placeholders).
Enabling OE / tri-state causes anomalies — break-before-make or output contention? Focus: OE timing policy vs electrical contention/reflection.
Likely cause: OE transitions near an active edge cause runt/missing; or two drivers overlap (contention), amplified by reflections at poor terminations.
Quick check: capture OE edge relative to clock edges; look for overlap windows or current spikes; compare far-end waveform with/without OE changes.
Fix: enforce break-before-make windows ≥ X ns; avoid overlapping drivers; correct termination; add series damping only if jitter budget still passes.
Pass criteria: OE toggles produce no runt/missing/double; contention window=0; sw/OE events do not increase J_RMS@BW by > Y (placeholders).
Input-loss detection chatters and causes ping-pong switching — how to set LOS threshold and debounce? Focus: LOS/qualify stability and false switch rate.
Likely cause: LOS threshold too close to real amplitude margins; debounce too short; qualify window too narrow under vibration/EMI/PDN noise.
Quick check: log LOS_events vs measured Vin_amp and f_in; identify whether LOS toggles at specific ripple/temperature/load conditions.
Fix: add hysteresis; increase debounce to ≥ X cycles; require stable input for ≥ Y ms before re-switch; lock revert policy (no oscillation).
Pass criteria: LOS_chatter=0 over T; false_switch_rate < X; recovery time within Y (placeholders).
Different board batches show different switching phase jumps — layout variance or default configuration? Focus: config hash first, then physical variance (routes/loads/PDN).
Likely cause: (1) strap/register defaults differ (unintended), or (2) routing/termination/load/PDN differs enough to alter effective phase/skew around the boundary.
Quick check: compare config_hash (register dump/strap states) across batches; then compare key nets (stub length, split node, term parts) and PDN ripple at switchover.
Fix: enforce explicit configuration at boot; standardize term/loads; tighten layout constraints; add batch acceptance based on measured Δφ/Δskew.
Pass criteria: config_hash identical; |Δφ_batch| ≤ X; Δskew_batch ≤ Y ps; sw_fail_rate < Z (placeholders).
With a small frequency offset (ppm), can switching still be “hitless”? What prerequisites are required? Focus: define allowed pause/phase step; do not pretend Δf=0.
Likely cause: with Δf ≠ 0, phase error accumulates; a “perfectly continuous” phase boundary is impossible unless the system allows bounded pause/step or alignment strategy.
Quick check: measure Δf (ppm) and compute worst-case phase drift during the switch window; compare to allowed_Δφ and allowed_pause constraints.
Fix: tighten Δf (better references) or relax acceptance to bounded pause/Δφ; ensure switching occurs only after stable qualify and optional alignment.
Pass criteria: |Δf| ≤ X ppm; resulting |Δφ| ≤ Y (or pause ≤ Z) inside sw_window (placeholders).
Production: how to do a fast hitless check — what is the minimum test set? Focus: short burst + counters + traceability fields.
Likely cause: fast tests miss rare events unless the burst and capture strategy is defined; station variance (fixture/cables/termination) creates false fails or false passes.
Quick check: run a defined switch burst (A→B→A) with fixed config_hash; count runt/missing/double; add a short LOS false-trigger check; log fixture_id and cable_id.
Fix: standardize fixture/termination; define burst_count and capture rules; reject stations with station_delta beyond limit; add periodic fault-injection sampling.
Pass criteria: burst_count ≥ N; runt=0; missing=0; double=0; false_switch_rate < X; station_delta ≤ Y (placeholders).
After skew tuning, the eye diagram worsens — added jitter from delay elements or termination changed? Focus: isolate delay-induced jitter vs load/termination effects.
Likely cause: (1) delay/deskew path adds additive jitter or distorts edges, or (2) termination/load changed (often unintentionally) when probing or reworking.
Quick check: keep termination fixed and sweep delay setting while logging J_RMS@BW and rise/fall; then hold delay fixed and change only termination/load to see which variable moves the eye.
Fix: use minimal delay steps; re-validate termination; avoid probe-induced loading; if required, re-budget additive jitter and re-check max-load behavior.
Pass criteria: ΔJ_RMS@BW ≤ X; eye margin ≥ Y; skew meets target ≤ Z ps without violating runt/missing/double=0 (placeholders).
Recommended record fields (placeholders): config_hash, fixture_id, cable_id, T(°C), V(V), N_load, fA/fB, Vin_amp, LOS/LOL counters, sw_start/sw_done, sw_latency, pause, Δφ, runt/missing/double counters, J_RMS@BW, duty%, skew_total.
