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Electrical Layer: Swing, Common-Mode, Emphasis, Eye/Jitter Budget

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This page turns the electrical layer into a deliverable: a measurable link budget from swing/common-mode and termination to FFE and Rx eye/jitter margin, with clear pass/fail thresholds at a declared reference plane.

The goal is not “a pretty eye,” but a repeatable workflow that maps channel inputs (IL/RL/XT) to a safe preset window and verified BER-time stability across cables, ports, and temperature.

Scope: Electrical Layer (Swing · Common-mode · Emphasis · Eye/Jitter Budget)

One-line thesis

Electrical layer success is a measurable loop: define swing/common-mode, choose Tx shaping, verify Rx sensitivity using eye/jitter margins, and lock pass criteria that stays valid across cable/board/temperature variation.

Covered in this page

  • Swing: amplitude definitions, where swing “breaks first,” and what to tune vs what to measure.
  • Common-mode: VOCM range, AC-coupling + bias networks, CM-to-DM coupling symptoms, and quick discrimination checks.
  • Emphasis/FFE knobs: pre/de-emphasis intent, safe tuning strategy, and what to log for repeatable results.
  • Rx sensitivity + Eye/Jitter budgets: mask/margin language, bathtub interpretation, and budget-to-pass workflow.

What this page produces (deliverables)

  • Budget template: reference plane → target → measured → margin → notes (no protocol assumptions).
  • Measurement checklist: TP definitions, instrument fields to record, fixture/de-embedding boundaries, and pattern sanity checks.
  • Pass-criteria placeholders: minimum eye height/width, BER threshold, and robustness conditions (temperature/cable variance) using threshold placeholders (X).

Not covered (to prevent cross-page overlap)

  • Protocol training/state machines (PCIe/USB/DP/Ethernet/HDMI…): only electrical symptoms are referenced, no protocol-level walkthroughs.
  • Deep architecture tutorials (CTLE/DFE/CDR/PLL statistics): only treated as “knobs/allowed ranges,” not as a full theory chapter.
  • TSN/PTP/SSC system timing: referenced only as constraints; dedicated pages should host the full details.
  • Isolation/safety and ESD/TVS design as primary topics: referenced as boundary conditions, not expanded here.

Practical rule

Cross-page mentions are “pointer-only”: one line for context + a sibling-page pointer. No expanding into new sub-chapters.

Scope map (Electrical Layer vs sibling pages)

Electrical Layer Scope Map Four electrical-layer focus blocks (Swing, Common-mode, Emphasis/FFE, Rx+Eye/Jitter Budget) with pointer-only sibling pages on the right. Electrical Layer (focus) Tx Channel Rx Swing Common-mode Emphasis / FFE Rx + Eye/Jitter Sibling pages (pointer-only) Retimer / CDR USB Redriver / Hub PCIe Retimer Ethernet PHY / TSN ESD/TVS / EMC

Reliable electrical work starts with a shared coordinate system: a differential signal path carries the data, while the common-mode/return path often decides whether failures become “rare and random.” A reference plane definition makes every eye/jitter result comparable across boards, fixtures, and labs.

Key rules (make results repeatable)

  • Rule 1 — define reference planes: every metric must state where Tx “output” starts and where Rx “input” ends.
  • Rule 2 — fix test points (TPs): use a consistent TP1/TP2/TP3 naming so reports remain comparable.
  • Rule 3 — separate what is removed vs kept: de-embedding must state which fixture effects are removed and which remain part of the channel.

Vocabulary card (engineering meaning, not theory)

Differential vs Common-mode

Differential carries the data eye. Common-mode carries return/bias currents and couples into noise/crosstalk. Common-mode issues often appear as “intermittent” errors rather than clean failures.

Reference plane

The declared boundary for measurement and budgeting. Without it, swing/eye/jitter numbers cannot be compared between vendors, fixtures, or stations.

De-embedding

A declared operation that removes known fixture effects to relocate the reference plane. It must specify what is removed (fixture) and what remains (channel).

Test-point checklist (TP1/TP2/TP3)

  • TP1 — Tx-side reference: validates Tx swing and Tx shaping settings before the channel dominates.
  • TP2 — mid-channel discriminator: separates “reflection/impedance” issues from “insufficient loss compensation” issues.
  • TP3 — Rx-input truth: the only place where Rx sensitivity and eye/jitter margins must be proven for pass criteria.

Minimum measurement header (template)

  • TP definition (TP1/TP2/TP3 coordinates and connectors)
  • Tx/Rx reference plane statement (where specs apply)
  • Instrument fields: bandwidth, sampling mode, fixture ID, de-embed file revision
  • Pattern/payload used (PRBS type or stress pattern label)

Typical link blocks (each maps to a failure signature)

  • AC coupling + bias: baseline wander, common-mode range violations, slow drift across temperature/leakage.
  • Termination + impedance steps: reflections (return loss), stubs/vias/connector discontinuities, pattern-dependent errors.
  • Cable/backplane/connectors: insertion loss rise, frequency-selective notches, crosstalk sensitivity, eye closure under load.

Output of this section

A project-specific diagram that pins down TP1/TP2/TP3 and the de-embedding boundary, so every eye/jitter plot in later sections is traceable and comparable.

Differential link diagram (reference planes, TPs, and de-embedding boundary)

Differential Link and Reference Planes Tx to channel to Rx block diagram with three test points (TP1 TP2 TP3) and a dashed de-embedding boundary around the fixture and connectors. Tx Swing FFE knobs Channel AC cap Bias Term Conn Via Cable / Backplane Rx Sensitivity Eye/Jitter TP1 TP2 TP3 De-embedding boundary (declare what is removed) Tx reference plane Rx reference plane

Swing & Amplitude: What Matters, and What Breaks First

Swing is not “more is always better.” Amplitude numbers only become meaningful when tied to a declared test point (TP), bandwidth/settings, and pattern. Stability is decided by the combined margin of amplitude, reflections/ISI, and time-domain uncertainty (jitter).

Key rules (keep swing discussions engineering-grade)

  • Rule 1 — declare TP + settings: report swing with TP (TP1/TP2/TP3), bandwidth/filters, pattern, and de-embedding revision.
  • Rule 2 — amplitude ≠ eye: a large Vdiff-pp can coexist with a closed eye when reflections, ISI, or jitter dominate.
  • Rule 3 — tune in the right order: fix reflections/termination first, then sweep swing, then validate eye/jitter margin for pass criteria.

Swing metrics quick map (engineering use only)

Vdiff-pp

Use for: quick amplitude sanity checks at a declared TP.
Easy to fake by: overshoot/ringing, probe loading, fixture resonance.
Always record: TP + bandwidth + pattern + de-embed rev.

Vse (single-ended)

Use for: symmetry/common-mode drift checks (A vs B).
Easy to fake by: reference/ground issues, asymmetrical probing.
Always record: probe reference + ground method + TP.

RMS (effective)

Use for: energy/noise comparisons and “before/after” tuning with stable settings.
Easy to fake by: bandwidth filtering, pattern dependence, sampling mode.
Always record: bandwidth/filtering + pattern + capture method.

Mean / average

Use for: baseline/bias drift detection (AC coupling, leakage, slow variables).
Not for: deciding eye opening or BER directly.
Always record: temperature + time window + pattern.

Top 5 amplitude traps (and the fastest discrimination check)

  1. Overshoot looks “strong”: Vdiff-pp increases but ringing reduces eye margin.
    Quick check: compare TP2 vs TP3 and reduce bandwidth artifacts; watch for settling/ringing signatures.
  2. Probe/fixture loads the link: amplitude is compressed and noise looks worse than reality.
    Quick check: swap probe method/fixture and confirm the de-embedding boundary and file revision.
  3. AC coupling baseline drift: mean shifts over time/pattern, changing effective decision threshold.
    Quick check: run a DC-balanced vs unbalanced pattern and log mean drift over time (limit placeholder: X).
  4. Load changes change swing: termination or parallel branches alter the effective amplitude at TP3.
    Quick check: verify termination presence/value and remove stubs/branches for an A/B test.
  5. Settings mismatch across labs: RMS/pp values differ due to bandwidth, sampling, filtering, or trigger modes.
    Quick check: standardize a “measurement header” and require it on every plot/report.

Tuning sequence (protocol-agnostic)

  1. Lock TP + reference plane + instrument settings (otherwise numbers are not comparable).
  2. Eliminate obvious reflections/termination issues (amplitude can be “high” yet invalid).
  3. Sweep swing in bounded steps; log Vdiff-pp/RMS + eye height/width + BER (threshold placeholders: X).
  4. Freeze a “safe swing window” that keeps margin across temperature/cable/board variance.

Deliverables (make swing decisions repeatable)

  • Swing measurement header: TP, bandwidth/filtering, pattern, fixture ID, de-embed file revision, temperature.
  • Swing sweep log: setting → Vdiff-pp/RMS → eye height/width → BER → notes (pass threshold placeholders: X).
  • Amplitude sanity checklist: overshoot/ringing, probe/fixture loading, baseline drift, termination/branches, settings consistency.

Waveform/eye comparison (same link, different swing outcomes)

Swing vs Eye Outcome Three side-by-side cases showing that higher amplitude does not always mean better eye margin; reflections, ISI, and jitter can close the eye. High swing Eye closed Mid swing Eye open Low swing Margin OK Amplitude Amplitude Amplitude Margin OK Eye window Eye window Eye window

Common-Mode & Biasing: VOCM, AC Coupling, and CM Range Compatibility

Common-mode is a compatibility contract between the transmitter, the receiver, and the bias network after AC coupling. When that contract is violated, failures often become intermittent and temperature-sensitive even if differential amplitude “looks fine.”

Core model (what must be proven at TP3)

  • VOCM sources: Tx output common-mode, Rx allowed input CM range, and the external bias network.
  • AC coupling slow variables: capacitor value/leakage + bias resistors create RC drift and baseline wander.
  • CM-to-DM conversion: asymmetry in layout/termination/fixture/return path turns CM noise into differential errors.

Allowed CM range (placeholders for specs + acceptance)

VOCM_TX range

[Xmin, Xmax] @ TP1/TP2 (declare the reference plane)

VOCM_RX allowed

[Xmin, Xmax] @ TP3 (worst-case temperature and cable/board)

Pass rule (compatibility contract)

Overlap must exist with margin ≥ X. Verify at TP3 using a declared pattern and stable measurement header.

Bias network checklist (AC coupling + resistors + symmetry)

  • AC caps: value class + leakage category; confirm baseline drift limit ≤ X over time window X.
  • Bias resistors: tolerance + symmetry (A vs B); mismatch creates CM-to-DM conversion.
  • Rx internal bias: confirm whether an internal bias exists; avoid “double-bias” conflicts.
  • Termination presence: confirm the diff termination value/topology at the declared reference plane.
  • Single-ended symmetry check: |Vse(A) − Vse(B)| ≤ X at TP3 under worst-case conditions.

CM-to-DM quick discrimination (fastest checks first)

  1. If changing shielding/ground/return routing changes errors sharply → prioritize return path and symmetry checks.
  2. If mean/baseline drifts with time/pattern → prioritize AC coupling + bias RC and leakage checks.
  3. If errors correlate with port-to-port variance → prioritize termination/bias component tolerance and connector asymmetry.

Deliverables (make CM issues measurable)

  • VOCM compatibility sheet: VOCM_TX, VOCM_RX allowed, external bias result, TP3 measured, margin (placeholders X).
  • Baseline wander recipe: DC-balanced vs unbalanced patterns, duration X, temperature points X, log mean drift + burst errors.
  • CM-to-DM triage flow: return-path sensitivity → symmetry → bias RC → termination (fast isolation order).

Electrical diagram (AC coupling, bias, VOCM node, and termination)

Common-Mode and Biasing Diagram Block diagram showing Tx, AC coupling capacitors, bias resistors to VOCM node, differential termination at Rx, and test points TP2 and TP3, with VOCM_TX and VOCM_RX range badges. Tx VOCM_TX AC AC Bias network R R VOCM REF Term Zdiff TP2 TP3 CM path sensitivity VOCM_TX range VOCM_RX range

Termination & Impedance: Zdiff, Return Loss, Stubs, and Reflections

Impedance continuity is a geometry-and-boundary problem, not a guess. Reflections often present as “amplitude looks fine, yet errors happen” because ringing and re-reflections reduce eye width and create burst errors. The fastest path is: classify (reflection vs loss), locate the discontinuity (TDR), confirm severity (return loss), then close the loop at TP3 margin.

Key rules (avoid “measurement illusions”)

  • Rule 1 — declare the reference plane: Zdiff and return loss mean nothing without a stated boundary (TP + de-embed revision).
  • Rule 2 — reflection is a time-domain event: locate it first (TDR), then confirm severity (return loss).
  • Rule 3 — close the loop at TP3: fixing a reflection must increase eye/jitter margin or BER at the Rx input (threshold placeholders: X).

Reflection triage flow (short-cable OK, long-cable fails)

  1. Symptom: short cable/short trace passes; long reach fails or shows burst errors.
    Fast check: compare TP2 vs TP3; if TP2 is clean but TP3 shows ringing/bursts, prioritize a discontinuity near Rx/connector.
  2. Symptom: failures are sensitive to plug/unplug, flex, or port-to-port variation.
    Fast check: swap connector/cable; if the error rate shifts sharply, prioritize connector/return path continuity.
  3. Symptom: changing data pattern changes failure probability (burstiness, periodic errors).
    Fast check: run a stress pattern; reflections often create pattern-dependent ISI/ringing that collapses eye width.
  4. Decision: if TDR shows a large step/peak aligned to a structure, fix that structure before EQ/FFE tuning.
    Pass criteria: TP3 eye/jitter margin ≥ X and BER ≤ X across worst-case cable/temperature.

Minimal TDR + return loss workflow (6 steps)

  1. Declare TP and de-embed boundary (fixture removed vs channel kept).
  2. Run TDR to locate the discontinuity (time position of step/peak).
  3. Map Δt to a physical location using velocity factor (placeholder values).
  4. Run return loss to confirm severity and frequency-selective notches.
  5. Do an A/B isolation (remove stub, replace connector, bypass via segment).
  6. Re-verify at TP3: eye width/height + BER margin (threshold placeholders: X).

Impedance continuity checklist (what to verify before tuning EQ)

  • Termination location: is the termination at the declared reference plane, not “somewhere nearby”?
  • Zdiff continuity: known discontinuities (connector, via array, package escape) documented and bounded.
  • Stubs/branches: test pads, branch connectors, and debug headers removed or length-controlled.
  • Pair symmetry: A/B routing symmetry (length, via count, reference transitions) to avoid CM-to-DM conversion.
  • Fixture realism: fixture/probe discontinuities declared; de-embedding file revision recorded.
  • Return path: reference plane continuity (no unexpected splits/neck-downs) across connectors and layer transitions.

Deliverables (make reflection fixes auditable)

  • Structure suspect list: element name → physical location → A/B isolation action → result.
  • Measurement header: TP, de-embed boundary, instrument settings, fixture ID, revision control.
  • Acceptance placeholders: TP3 margin ≥ X and BER ≤ X under worst-case conditions.

Reflection localization (TDR time peak → physical discontinuity)

TDR Reflection Localization A link block diagram (Tx to Rx) with connector, via, and stub discontinuities, and a TDR step response showing reflection peaks mapped back to those structures. Physical path (structures) Tx Conn Via Cable / Backplane Stub Rx TDR step response (time → distance) Time Step Δt → location Conn Via Stub

Tx Pre-Emphasis / De-Emphasis / FFE: What to Tune, What to Log

Tx equalization is not guesswork when the goal is defined: restore usable high-frequency energy at the Rx input to improve TP3 margin. The tuning loop should start from a bounded preset set, log every change with a stable measurement header, and stop when incremental margin gain falls below a threshold placeholder (X).

Guardrails (avoid overlap with Retimer/CDR pages)

  • This section covers: Tx shaping knobs (preset, pre/main/post taps) and a repeatable tuning+logging workflow.
  • This section does not expand: Rx CTLE/DFE/CDR internal algorithms or protocol training state machines (pointer-only elsewhere).
  • Final validation: TP3 eye/jitter margin and BER with defined stress conditions (threshold placeholders: X).

Parameters (what can be controlled)

  • Preset: start with a small candidate set (3–5) based on rough channel loss classification.
  • Pre/Main/Post taps: refine around the best preset; keep changes bounded and logged.
  • Step strategy: fix main → sweep post → adjust pre → re-check swing guardrails.
  • Stop criteria: stop when margin gain per step < X or side effects exceed guardrails.

Must-log fields (turn tuning into engineering)

  • Preset/taps + firmware/tool revision
  • TP + de-embed boundary + instrument settings
  • Pattern/stress condition + temperature point
  • TP3 eye height/width + BER + error burst notes

Symptoms (what changes indicate)

  • Eye width increases: ISI is being compensated (good direction), confirm BER improvement at TP3.
  • Eye height drops while width rises: excessive HF boost may be amplifying noise/crosstalk.
  • Overshoot/ringing increases: reflections may dominate; revisit termination/impedance before further boost.
  • Burst errors appear: an over-emphasis + reflection combo is likely; tighten guardrails and back off.

Actions (repeatable tuning loop)

  1. Precondition: termination/impedance issues are bounded (reflection hotspots fixed or minimized).
  2. Preset search: select 3–5 candidates, run the same script on each, rank by TP3 margin.
  3. Top-2 refinement: refine with small tap steps; keep the same pattern and instrument header.
  4. Guardrails: if noise/crosstalk sensitivity increases or burst errors rise, back off to the last stable setting.
  5. Freeze a safe window: define a stable preset/tap range that survives temperature and cable variance.

Over-emphasis guardrails (placeholders)

  • Max tap magnitude ≤ X (to limit noise amplification and overshoot)
  • Burst error rate must not exceed X (otherwise treat as unstable)
  • Crosstalk sensitivity delta ≤ X under controlled A/B stimulus

FFE concept (pre/main/post taps → compensates channel loss)

FFE Three-Tap Concept Tx FFE block with pre/main/post taps feeding a lossy channel and a conceptual frequency shaping panel showing HF boost and margin outcome badges. Tx FFE (controls) FFE Pre Main Post Channel Loss Shaping (concept) LF HF HF restore Margin ↑ Too much → noise

Rx Sensitivity: Noise, ISI, and What “Margin” Really Means

Rx sensitivity is not a single “mV number.” It is a budget: usable signal at TP3 minus penalties from noise, ISI, jitter, and threshold/baseline drift. A PRBS test can pass while payload fails when the penalty mix changes (pattern spectrum, burst disturbances, or Rx operating state), even if swing appears similar.

Engineering definition (budget view)

  • Signal term: effective eye opening at the declared measurement point (TP3), not just Vpp.
  • Penalty terms: Noise + ISI + jitter penalty + threshold/baseline drift.
  • Margin: remaining budget after penalties; must stay ≥ X under worst-case conditions.

Margin composition (what to size and what to control)

  • Noise penalty: random noise floor, supply-coupled noise, and crosstalk that reduces eye height.
  • ISI penalty: channel loss/reflection-driven inter-symbol interference that reduces eye width and can introduce burst errors.
  • Jitter penalty: sampling uncertainty; the same eye can fail when sampling shifts toward edges.
  • Threshold/baseline drift: AC-coupling/bias drift or decision-threshold movement that changes effective sensitivity over time.

Pass criteria (placeholders)

  • Margin ≥ X at TP3 under worst-case cable/temperature/power conditions.
  • BER ≤ X for duration X with stress pattern and payload A/B comparison.
  • No burst-error escalation when switching PRBS → payload (threshold X).

Minimum Rx fields to log (make PRBS vs payload differences actionable)

EQ state (bounded description)

CTLE level / DFE on-off / preset index (placeholders). Record the “allowed range” used, not algorithm details.

Sampling / lock indicators

Lock status, sampling phase bound indicator (placeholders), and any “state changes” correlated with burst errors.

Error shape

Random vs burst, burst length distribution (placeholder), and “error vs time” window length.

Environment & power

Temperature point, cable/port ID, and supply ripple summary (placeholders) for correlation.

Why PRBS can pass while payload fails (engineering causes)

  • Different spectral/transition statistics → ISI and baseline drift penalties change.
  • Payload triggers burst disturbances (power/crosstalk/transients) not represented by the PRBS setup.
  • A state boundary is crossed (Rx operating region changes) even if swing looks similar.

Sensitivity budget (Signal − penalties = Margin)

Sensitivity Budget Stacked budget showing usable signal reduced by penalties (Noise, ISI, Jitter, Threshold drift) leaving remaining margin, evaluated at TP3 with a pass badge Margin >= X. TP3 Margin ≥ X Signal Noise ISI Jitter pen. M Noise ISI Jitter penalty Threshold drift Signal − (Noise + ISI + Jitter + Threshold) = Margin

Eye Diagram & Jitter Budget: From Mask to BER (Engineering View)

Mask pass/fail is a checkpoint, not the full story. A robust electrical-layer deliverable connects: eye at TP3 → mask overlay → bathtub margin at target BER → BER over time under stress. Jitter budget (TJ/RJ/DJ) is used as an allocation and audit tool, not a statistical derivation exercise.

The 4 plots to deliver (placeholders, protocol-agnostic)

Plot #1 — Eye @ TP3

Include: TP, bandwidth/filtering, pattern, de-embed revision, temperature point (placeholders).

Plot #2 — Mask overlay

Include: mask version/reference field (placeholder) and pass/fail annotation.

Plot #3 — Bathtub @ target BER

Include: BER target = X, timing margin = X, and sampling point definition (placeholders).

Plot #4 — BER vs time (stress)

Include: duration X, temperature sweep points X, PRBS vs payload A/B, and burst notes (placeholders).

Jitter budget (engineering usage, no statistics)

  • TJ: the top-level budget to meet at TP3; used for acceptance alignment.
  • RJ: noise-driven spread; changes the “floor” of the bathtub center region.
  • DJ: deterministic sources (ISI/reflections/periodic coupling); distorts bathtub edges and can create asymmetry.
  • Action: allocate margin to concrete sources, then verify with the same measurement header.

Common misreads (instrument settings create “better/worse” illusions)

  • Bandwidth/filter mismatch: changes eye height and noise floor; comparisons become invalid.
  • Clock recovery/trigger mode: changes apparent eye width and jitter decomposition.
  • De-embed boundary mismatch: a different fixture/channel boundary produces different masks and bathtubs.
  • Time window mismatch: short captures hide drift and burst events; BER vs time must use defined duration X.

Mandatory measurement header (template fields)

TP / de-embed boundary / fixture ID / bandwidth & filtering / clock recovery mode / pattern / temperature / port & cable ID / revision control

Eye with mask overlay (minimal annotations)

Eye Diagram and Mask Overlay Stylized eye diagram with a mask box overlay and arrows indicating eye height and eye width, with a TP3 badge and pass/fail placeholder. TP3 Pass / Fail Mask Height Width Eye @ TP3

Channel Budget Workflow: Insertion Loss → Equalization Plan → Pass Criteria

This workflow connects channel inputs to a bounded equalization plan and a repeatable acceptance decision. The output is not a single “best setting,” but a verified safe window: candidate Tx presets/FFE ranges that keep TP3 margin positive under defined worst-case conditions (threshold placeholders: X).

Step-by-step workflow (Inputs → Decisions → Measurements → Pass/Fail)

Step 1 — Inputs (record fields)

IL / RL / Crosstalk (as inputs only) + TP boundary + fixture/de-embed revision + port/cable ID + temperature point (placeholders).

Exit criteria: reference plane is declared; inputs are comparable across runs.

Step 2 — Decisions (bounded plan)

Loss bin (low/medium/high, placeholders) → choose a small candidate preset set (3–5) + define guardrails (max emphasis, placeholders).

Exit criteria: candidate list is short; if RL indicates dominant reflection, fix termination/impedance first.

Step 3 — Measurements (same script)

For each candidate preset: Eye@TP3 → Mask overlay → Bathtub margin@BER=X → BER vs time under stress (placeholders).

Exit criteria: results share the same measurement header (TP, de-embed, bandwidth/trigger, pattern, temperature).

Step 4 — Outputs (freeze a safe window)

Select top candidates → refine bounded taps → define a safe preset/tap window that survives worst-case conditions.

Exit criteria: Margin ≥ X, BER ≤ X, training success rate ≥ X (placeholders) at TP3 for defined stress conditions.

Per-step logging fields (make results auditable)

Inputs

IL / RL / Crosstalk fields (placeholders) + TP boundary + fixture ID + de-embed revision + port/cable ID + temperature.

Decisions

Loss bin (placeholder) + candidate preset set + guardrails (max emphasis, max burst risk, placeholders).

Measurements

Eye/mask/bathtub/BER-time set + measurement header fields: TP, bandwidth & filtering, trigger/clock recovery, pattern, duration, temperature.

Outputs

Safe preset/tap window + pass criteria placeholders (margin ≥ X, BER ≤ X, training ≥ X) + rollback rule if credibility level is below decision grade.

Budget workflow map (key figure)

Budget Workflow Map Four-stage flow: Inputs, Decisions, Measurements, Pass/Fail with many small block elements and minimal text, tying insertion loss and return loss to preset selection and verification deliverables. Inputs Decisions Measurements Pass / Fail IL RL Crosstalk TP De-embed Temp/ID Loss bin Preset set Guardrails RL fail → Fix Z/term Top-2 refine Eye @ TP3 Mask Bathtub BER-time Header Compare Margin ≥ X BER ≤ X Train ≥ X Safe window freeze Rollback rule

Measurement & Pitfalls: Probing, Fixtures, De-Embedding, and Artifacts

Measurement errors can create two dangerous illusions: a link that “looks great” but fails in-system, or a link that “looks bad” but is punished by fixtures, settings, or boundary mistakes. Credibility levels and cross-checks (scope vs BERT/PRBS) prevent wrong decisions and make results auditable.

Measurement credibility levels (Level 0 → 3)

Level 0 — Not comparable

TP/boundary undefined, settings inconsistent, screenshots without a header.

Upgrade action: declare TP + de-embed boundary + write the measurement header.

Level 1 — Trend only

TP/settings fixed, but fixture/probe impact not declared; de-embed boundary unclear.

Upgrade action: fixture ID, loading notes, and de-embed revision control.

Level 2 — Decision grade

Fixture declared, de-embed boundary defined, scripts reproducible, same header across runs.

Upgrade action: add cross-check with BERT/PRBS and worst-case conditions.

Level 3 — Acceptance grade

Scope and BERT/PRBS cross-check agree; worst-case coverage; pass criteria placeholders met.

Output: auditable acceptance package (eye/mask/bathtub/BER-time + header).

8 common measurement pitfalls (fast checks + fixes)

Pitfall 1 — Probe loading

Illusion: eye shape changes because the probe becomes part of the termination.

Quick check: compare with/without probe; fix: use proper fixture and declare boundary.

Pitfall 2 — Return path / CM leakage

Illusion: common-mode paths convert into differential error, “randomly” shifting margins.

Quick check: move ground reference/fixture; fix: enforce reference plane continuity and symmetry.

Pitfall 3 — Fixture stubs

Illusion: extra ringing appears; mask fails, but the DUT path is not the root cause.

Quick check: TDR the fixture; fix: shorten/remove branches or re-define de-embed.

Pitfall 4 — Bandwidth/filter mismatch

Illusion: noise floor changes → eye height looks better/worse without real link change.

Quick check: lock settings across runs; fix: enforce a standard measurement header.

Pitfall 5 — Trigger / clock recovery

Illusion: eye width changes due to recovery mode differences, not the channel.

Quick check: document recovery/trigger; fix: keep mode consistent for comparisons.

Pitfall 6 — Over de-embedding

Illusion: results look “too good” because real channel loss is incorrectly removed.

Quick check: verify boundary objects; fix: state what is removed vs retained.

Pitfall 7 — Under de-embedding

Illusion: results look “too bad” because fixture artifacts remain in the measurement.

Quick check: A/B with a known-good fixture; fix: keep de-embed revision control.

Pitfall 8 — Time window too short

Illusion: drift and burst events are missed; the link “looks stable” until it fails later.

Quick check: run BER vs time with duration X; fix: define stress duration and log burst shape.

Mandatory measurement header (template)

TP / de-embed boundary / fixture ID / bandwidth & filtering / trigger or clock recovery / pattern / duration / temperature / port & cable ID / revision

Measurement setup (reference planes + de-embed boundary)

Measurement Setup with De-Embedding Block diagram: DUT connects through a fixture/probe to both scope and BERT paths. A de-embed block sits between fixture and instruments with a reference plane marked at TP2/TP3. DUT TP2 TP3 Fixture / Probe Load / CM path De-embed Boundary Scope Eye/Mask BERT BER-time Reference plane Cross-check: Scope vs BERT must agree at Level 3 Same header fields, same boundary, same stress duration (X)

Engineering Checklist: Design → Bring-up → Production (Electrical Layer)

This checklist is an execution layer that turns electrical specs into repeatable actions. Each item includes an auditable quick check and a pass-criteria placeholder (X). Material numbers are provided as concrete BOM examples; verify value/package/suffix/availability against the target data rate and reference plane definition.

Lane A — Design (freeze boundaries, impedance, return paths, coupling/bias)

A1 — Freeze reference planes and test points (TP2/TP3)

Quick check: TP location and de-embed boundary are declared in every plot header and build note (fixture ID + revision).

Pass criteria: boundary consistency = X% across runs; missing-header rate ≤ X%.

A2 — Termination & symmetry (Zdiff + component tolerance guardrails)

Quick check: differential termination is symmetric and placed to minimize stubs; tolerance and layout asymmetry are explicitly bounded.

Example BOM (termination resistors): Vishay CRCW0402100RFKED (100 Ω, 0402, 1%); Susumu RG1608P-101-D (100 Ω, 0603/1608 metric).

Pass criteria: return-loss / reflection metric ≤ X (at TP boundary).

A3 — Return path continuity (reference planes, vias, plane splits)

Quick check: no plane splits/neck-downs under critical differential segments; via transitions include a controlled return strategy.

Example BOM (stitch/return support): Murata GRM155R71H102KA01 (0402, 1 nF, X7R) as local HF stitching (verify placement and EMC policy).

Pass criteria: CM-to-DM sensitivity indicator ≤ X (placeholder), and layout review checklist sign-off = X%.

A4 — AC coupling and bias network (VOCM compatibility window)

Quick check: bias resistors and leakage paths are reviewed for baseline drift risk; VOCM min/max window is documented (placeholders).

Example BOM (AC coupling caps): Murata GRM155R71C104KA88 (0402, 0.1 µF, X7R, 16 V); Samsung CL05B104KA5NNNC (0402, 0.1 µF, X7R).

Example BOM (bias resistors): Panasonic ERJ-2RKF1003X (0402, 100 kΩ, 1%); Vishay CRCW040210K0FKED (0402, 10 kΩ, 1%).

Pass criteria: VOCM stays within [min,max]=X; baseline drift ≤ X under stress (placeholders).

A5 — Stub/branch guardrails (vias, connectors, debug pads)

Quick check: no un-terminated debug stubs; any test access is designed as controlled-impedance and measured at the declared TP.

Example BOM (series damping option, if allowed): Vishay CRCW040210R0FKED (0402, 10 Ω, 1%); Susumu RG1608P-22R0-D (0603/1608 metric, 22 Ω).

Pass criteria: TDR reflection peak ≤ X (placeholder) at each known discontinuity.

A6 — Preset/search space reserved (Tx swing + FFE window)

Quick check: at least three candidate presets exist (low/medium/high loss bins) with explicit guardrails to prevent over-emphasis.

Pass criteria: candidate preset count ≥ X; guardrails documented (max emphasis = X).

Lane B — Bring-up (fast triage: reflection vs loss vs noise/jitter)

B1 — Lock the measurement header template first (avoid Level 0)

Quick check: TP boundary, fixture ID, de-embed revision, bandwidth/filtering, recovery/trigger mode, pattern, duration, temperature are all present.

Pass criteria: header completeness ≥ X%; incomparable runs = 0.

B2 — Short channel OK, long channel fails: classify the dominant mechanism

Quick check: if RL/TDR indicates strong discontinuity, fix Z/termination first; if IL dominates, focus on bounded preset/FFE search.

Pass criteria: a single failure class is selected with a direct action path (reflection / loss / noise-jitter) and logged as a field.

B3 — Run a bounded candidate preset set (3–5) with a single script

Quick check: each candidate produces the same deliverables: Eye@TP3, Mask, Bathtub margin@BER=X, BER-time under stress.

Pass criteria: four-figure set exists for each candidate; best-2 are selected by margin (not by “prettiest eye”).

B4 — Guardrail check: avoid “over-emphasis makes it worse”

Quick check: if stronger emphasis raises noise floor / crosstalk sensitivity, step back and tighten the window; do not expand beyond guardrails.

Pass criteria: margin improves monotonically within the approved window; outside-window settings are disallowed by rule.

B5 — Temperature points: worst-case is the gate

Quick check: run at room + hot + cold (placeholders), keep the same header fields and boundary definition.

Pass criteria: worst-case margin ≥ X; BER ≤ X across all points.

B6 — Freeze a safe window (not a single “best” point)

Quick check: define a bounded preset/tap window that survives worst-case (margin + BER-time), plus rollback rules if credibility falls below decision grade.

Pass criteria: window width ≥ X steps; rollback trigger conditions are explicit.

Lane C — Production (script fields, fixture control, lot/temperature management)

C1 — Freeze production script fields (auditable by design)

Quick check: Inputs/Decisions/Measurements/Outputs fields are captured (IL/RL/XT placeholders + preset window + margin/BER-time placeholders).

Pass criteria: missing fields ≤ X%; station-to-station comparability = enabled.

C2 — Fixture consistency & revision control

Quick check: fixture ID/rev is part of the test header; any de-embed model is revision-locked and audited.

Example BOM (fixture resistor standards for calibration loads): Vishay CRCW040249R9FKED (49.9 Ω, 0402, 1%); Yageo RC0402FR-07100RL (100 Ω, 0402, 1%).

Pass criteria: known-load verification drift ≤ X; fixture swap delta ≤ X.

C3 — Lot/cable/connector variation managed as input fields

Quick check: cable/connector/port IDs are logged; IL/RL buckets explain variation rather than hiding it behind averaging.

Pass criteria: variation is explainable by recorded channel fields at ≥ X% rate (placeholder).

C4 — Guardband policy for temperature & aging

Quick check: acceptance uses a margin guardband (not just “pass at room”); worst-case becomes the production gate.

Pass criteria: guardband ≥ X; worst-case margin ≥ X across defined stress points.

C5 — Cross-check sampling (scope vs BERT/PRBS) as an audit hook

Quick check: a periodic cross-check run verifies that production metrics track lab metrics with the same boundary and header.

Pass criteria: correlation within X; discrepancy triggers rollback to credibility level upgrade actions.

Three-swimlane map (freeze → verify → production gate)

Engineering Checklist Swimlanes Three horizontal lanes: Design, Bring-up, Production. Each lane shows key block outputs and a freeze/gate progression. Design Freeze: TP / Z & return / Bias window Bring-up Verify: preset window / eye+mask / bathtub+BER-time Production Gate: script fields / fixture control / guardband TP boundary TP2 / TP3 Z + return symmetry Bias window VOCM Preset window bounded Eye + Mask TP3 Bathtub BER-time Script fields header Fixture ctrl ID / rev Guardband worst-case Design freeze Verification ready Production gate

Applications & IC Selection Notes (Electrical Layer Only)

Selection here is constrained to electrical-layer behavior only: swing range, VOCM compatibility, FFE/presets, sensitivity definition, and power/thermal derating. Scenarios are defined by channel type (not by protocol) to avoid cross-page overlap.

Scenario → parameter priority (by channel type)

Short on-board trace

Dominant risk: reflections / termination asymmetry / return-path details.

Priority: RL & termination tolerance → VOCM window → minimum necessary swing → power.

Long cable

Dominant risk: insertion loss + baseline drift + noise sensitivity.

Priority: FFE preset window → sensitivity definition (TP/BER/temp) → AC coupling/bias robustness → guardband at temperature.

Backplane

Dominant risk: frequency-dependent loss + multiple discontinuities + crosstalk.

Priority: tap count/presets/step granularity → guardrails (avoid over-emphasis) → RL input discipline → power/thermal.

Multi-connector / stub-prone

Dominant risk: reflection-dominant failure (eye-width collapse).

Priority: fix discontinuities first (Z/termination/return) → then bounded presets → finally validate margin.

Electrical-layer selection dimensions (what to shortlist)

Swing range

Required: min/max swing window (X), step granularity (X), and load sensitivity notes.

VOCM / CM range

Required: allowed VOCM range (X), AC-coupling/bias friendliness, and baseline drift sensitivity notes.

FFE / presets

Required: tap count/preset count (X), step size, and guardrails against over-emphasis (X).

Sensitivity definition (engineering)

Required: “at TP3, at BER=X, at temp points X” definition, plus the required margin X.

Power / thermal

Required: per-lane power budget (X) and derating rule at worst-case temperature (X).

Concrete BOM examples (supporting parts used in electrical-layer implementation)

AC coupling capacitors

Murata GRM155R71C104KA88 (0402, 0.1 µF, X7R, 16 V); Samsung CL05B104KA5NNNC (0402, 0.1 µF, X7R); Murata GRM033R71C104KE14 (0201, 0.1 µF, X7R) — for tight layouts (verify ESR/ESL impact).

Termination / damping resistors

Vishay CRCW0402100RFKED (0402, 100 Ω, 1%); Yageo RC0402FR-07100RL (0402, 100 Ω, 1%); Vishay CRCW040210R0FKED (0402, 10 Ω, 1%) — optional series damping (verify signal integrity budget).

Bias network resistors

Panasonic ERJ-2RKF1003X (0402, 100 kΩ, 1%); Vishay CRCW040210K0FKED (0402, 10 kΩ, 1%); Panasonic ERJ-2RKF4991X (0402, 4.99 kΩ, 1%) — for divider/bias shaping (verify VOCM target).

0 Ω configuration links (layout-friendly options)

Yageo RC0402JR-070RL (0402, 0 Ω); Panasonic ERJ-2GE0R00X (0402, 0 Ω) — use to enable/disable optional damping/bias branches (avoid adding stubs).

Note: Any active signal-conditioning ICs (redriver/retimer/CDR) are intentionally not expanded here to avoid overlap with dedicated subpages. If the decision tree indicates “retiming required,” route to the corresponding Retimer/CDR or Linear Redriver/Equalizer page.

Electrical-layer selection flow (decision tree)

Electrical-layer Selection Flow Flow diagram from channel inputs to three key needs (FFE, CM bias robustness, sensitivity) and outputs shortlist features. Inputs Channel loss Reflections CM bias Temp/Power Target margin Decisions Need FFE? Need CM robustness? Need higher sensitivity? Retiming? Shortlist features Swing range VOCM range Presets / taps Sensitivity def Power-thermal If retiming required → sibling page

What must be filled to make selection defensible (placeholders)

TP boundary (TP2/TP3) + de-embed revision + loss/reflection classification + required margin X + worst-case temperature points X + approved preset/tap window.

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FAQs (Electrical Layer): Fast Triage Without Expanding the Main Body

Each FAQ is intentionally constrained to the electrical layer: swing/common-mode/bias, termination & impedance, insertion/return loss inputs, Tx FFE presets, Rx sensitivity and eye/jitter budgets, and measurement credibility (reference planes + de-embedding). Each answer uses a fixed, data-first 4-line structure with pass/fail placeholders (X).

Short channel passes, long channel fails — reflection point or insufficient loss/EQ first? First classification: reflection-dominant vs loss-dominant, using minimal inputs.

Likely cause: Reflection-dominant discontinuity (stub/connector/via/termination) or loss-dominant attenuation (IL too high at Nyquist) collapsing eye width.

Quick check: Compare two inputs first: IL@Nyquist = X dB and RL(min) = X dB at the declared boundary (TP3/de-embed). If RL is poor or TDR shows a clear step/peak, treat as reflection-first.

Fix: If reflection-first: remove/shorten stub, enforce Zdiff continuity, re-place termination. If loss-first: keep topology fixed, then run a bounded Tx FFE preset set (3–5) and select by bathtub margin (not “prettiest eye”).

Pass criteria: At TP3 (or de-embedded Rx boundary), Eye width ≥ X UI and Eye height ≥ X mV; BER ≤ X over X s; training success ≥ X% (N=X runs).

Increasing swing makes BER worse — over-emphasis noise gain or termination/common-mode issue? Identify whether “bigger” raised crosstalk/noise or pushed CM/termination out of range.

Likely cause: Over-emphasis / higher swing increases noise/XT sensitivity (effective SNR drops) or termination/CM operating point shifts (VOCM range violation, baseline shift).

Quick check: Keep boundary fixed; compare (a) noise floor at sampler input (or eye-height dispersion) and (b) VOCM at the Rx bias node. Log ΔNoise = X mVrms and VOCM = X V against allowed [min,max]=[X,X] V.

Fix: If noise/XT rises: reduce emphasis/swing, tighten guardrails, fix aggressor coupling (routing/return). If VOCM shifts: correct bias network and termination symmetry before touching FFE.

Pass criteria: Worst-case BER improves monotonically within the approved swing/FFE window; VOCM stays within [X,X] V; RJrms ≤ X ps and TJ@BER=XX ps (same boundary).

Eye looks open, but CRC/frame errors occur — which jitter definition or sampling point first? “Good-looking eye” can be a measurement artifact or a wrong metric for the error mode.

Likely cause: Wrong boundary/TP (measuring before the dominant impairment) or jitter mode not captured by a static eye (periodic/DJ causing errors at specific phases).

Quick check: Freeze TP3/de-embed and capture bathtub margin at BER=X. Compare eye-only vs bathtub: if bathtub margin is small (X UI) despite “open eye,” prioritize jitter-at-BER metrics (TJ@BER, DJ components) over visual eye shape.

Fix: Move measurement to the declared Rx boundary; then adjust within approved FFE/termination window. If errors correlate to specific phases, tighten the allowable jitter budget and re-validate with BER-time (not only snapshot eye).

Pass criteria: Bathtub margin ≥ X UI at BER=X; TJ@BER=XX ps; BER-time ≤ X over X min under the same header/boundary.

Training fails when temperature changes — which bias/common-mode/swing fields should be logged first? Temperature issues are often baseline drift, VOCM window squeeze, or marginal margin turning negative.

Likely cause: VOCM/bias window shrink with temp (bias network + leakage) or margin collapses due to loss/ISI increase and jitter penalty.

Quick check: Log the minimum set: VOCM=X V, Vdiff-pp=X mVpp, baseline drift=X mV over X ms, and bathtub margin=X UI at BER=X for room/hot/cold.

Fix: If VOCM drifts or violates [min,max], correct bias resistors/leakage paths and coupling caps selection. If margin drops with temp but VOCM stays valid, tighten topology/termination first, then re-select a safe preset window for worst-case temp.

Pass criteria: Across temp points, VOCM within [X,X] V; baseline drift ≤ X mV/X ms; worst-case bathtub margin ≥ X UI; training success ≥ X%.

Swapping one cable flips pass→fail — which three channel parameters to compare first? Reduce debate: compare the minimum trio that explains most variability.

Likely cause: Cable differences shift IL/RL/XT enough to push a marginal link below the margin threshold.

Quick check: Compare: (1) IL@Nyquist=X dB, (2) RL(min)=X dB in-band, (3) XT proxy (NEXT/FEXT)=X dB (or a defined coupling metric) at the same boundary/fixture.

Fix: If RL worsens: treat as reflection-first (connector/termination compatibility). If IL worsens: choose a preset window sized for the “worst cable bin.” If XT worsens: reduce emphasis and strengthen layout/return constraints before widening the window.

Pass criteria: For the worst-bin cable, Eye width ≥ X UI, Eye height ≥ X mV, BER-time ≤ X over X min, and training success ≥ X%.

After adding AC coupling, intermittent baseline wander appears — RC time constant or leakage? Separate deterministic RC recovery from true leakage-driven drift.

Likely cause: RC baseline recovery (Ccouple × Rbias) too slow for the traffic pattern or leakage path shifts the bias point (temp/humidity dependent).

Quick check: Trigger on a long idle/low-transition interval and measure baseline drift ΔV=X mV over Δt=X ms. If drift follows a consistent exponential with τ≈X ms, it is RC; if it varies with temperature/humidity or board handling, suspect leakage.

Fix: For RC: adjust Rbias/Ccouple to set τ below the allowed limit, or constrain patterns via guardband. For leakage: eliminate contamination paths, revise bias network placement, and re-verify VOCM window stability.

Pass criteria: Baseline drift ≤ X mV within X ms; VOCM remains within [X,X] V; BER ≤ X for patterns including worst-case idle/bursty segments.

Pre-emphasis improved the eye, but EMI got worse — what is the first sanity check? “Better eye” may be achieved by more HF energy that violates EMI guardrails.

Likely cause: Over-emphasis increases high-frequency spectral content (and common-mode conversion sensitivity) beyond EMC margin, even if the eye snapshot improves.

Quick check: Verify emphasis stays within the approved window: main/pre/post taps do not exceed X steps and swing ≤ X mVpp. Then compare EMI peak change ΔEMI=X dBµV versus bathtub margin gain ΔMargin=X UI.

Fix: Reduce emphasis to the minimum that meets margin; prioritize termination/return-path fixes that improve margin without adding HF energy. If EMI is driven by CM conversion, tighten symmetry and return-path continuity before re-expanding the preset window.

Pass criteria: Bathtub margin ≥ X UI at BER=X while EMI peak ≤ limit−X dB (guardband); approved preset window documented and enforced.

Rx reports high margin, but the system still drops — verify reference plane or instrument settings first? “Margin” is only meaningful with a declared boundary and measurement credibility.

Likely cause: Margin was measured at the wrong point (pre-impairment) or instrument filtering/trigger/bandwidth settings created an optimistic artifact.

Quick check: Freeze and print the header fields: TP boundary, de-embed revision, bandwidth/RBW/VBW, trigger mode. Re-measure margin at TP3 (or de-embedded Rx boundary). If margin changes by ≥ X UI after boundary/header correction, treat prior margin as invalid.

Fix: Enforce a minimum credibility level: two-method confirmation (scope eye/bathtub + BERT/BER-time). Lock de-embed models and instrument settings by revision control before re-qualifying any preset window.

Pass criteria: Margin at declared boundary ≥ X UI (BER=X); BER-time ≤ X over X min; header completeness ≥ X%; method-to-method delta ≤ X.

Same board, different ports behave differently — impedance discontinuity or crosstalk coupling first? Use port-to-port delta signatures instead of guessing.

Likely cause: One port has a stronger discontinuity (connector/via/termination) or a stronger aggressor coupling path (XT).

Quick check: Compare the deltas: ΔRL(min)=X dB, ΔTDR peak=X, ΔXT=X dB between ports, at the same fixture/boundary. If ΔRL/ΔTDR dominates, treat as impedance-first.

Fix: Impedance-first: fix topology/termination symmetry and known discontinuity points; then re-run bounded presets. XT-first: reduce emphasis, improve return-path symmetry, and adjust routing aggressor spacing/return continuity (no algorithm discussion).

Pass criteria: Port-to-port margin delta ≤ X UI; worst port meets Eye width ≥ X UI, BER ≤ X, training success ≥ X%.

PRBS shows low BER, but specific payload patterns fail — which pattern/spectral correlation check first? Some failures are transition-density / baseline / spectral line interactions, invisible to generic PRBS.

Likely cause: Pattern-dependent baseline wander (AC coupling + bias) or spectral-line / periodic jitter interaction that hits a narrow vulnerability (sampling point sensitivity).

Quick check: Run A/B patterns: high-transition PRBS vs low-transition or bursty payload. Compare baseline drift ΔV=X mV/X ms and BER-time difference ΔBER=X. If BER moves with transition density, suspect baseline/RC; if periodic, correlate errors with jitter phase.

Fix: Baseline/RC: adjust τ (Ccouple/Rbias) and tighten VOCM stability; or restrict the operating window by guardband. Periodic correlation: tighten jitter budget at BER and re-validate the chosen preset window with the failing pattern.

Pass criteria: BER ≤ X for both PRBS and worst-case payload; baseline drift ≤ X mV/X ms; bathtub margin ≥ X UI at BER=X.

Eye width is insufficient but eye height is OK — sampling phase/FFE first or termination first? Eye-width collapse is often reflection/ISI or jitter; choose the first knob based on signatures.

Likely cause: ISI/reflection squeezes horizontal opening or jitter penalty dominates while vertical noise is acceptable.

Quick check: If RL/TDR indicates discontinuity (RL(min)=X dB or clear reflection peak), fix termination/impedance first. If RL is fine but TJ@BER=X is high (≤/≥ X ps), prioritize sampling phase/jitter-budget closure and bounded FFE tuning.

Fix: Reflection signature: remove stubs, correct termination placement, enforce symmetry. Jitter signature: re-center sampling (by measured bathtub), then tune within the approved FFE window; avoid expanding emphasis beyond guardrails.

Pass criteria: Eye width ≥ X UI at TP3; bathtub margin ≥ X UI at BER=X; RL(min) ≥ X dB; BER-time ≤ X over X min.

“Looks like common-mode noise” — how to quickly verify CM-to-DM conversion is causing differential errors? Prove conversion with a controlled A/B change, not by intuition.

Likely cause: Asymmetry in termination/return path converts common-mode disturbance into differential error; errors often scale with emphasis or layout imbalance.

Quick check: Run a controlled A/B: keep swing/FFE constant, then (A) add a small intentional symmetry improvement (e.g., restore return continuity or remove an asymmetric stub) or (B) reduce emphasis by X steps. If BER improves by ≥ X while VOCM remains within [X,X] V, CM-to-DM conversion is implicated.

Fix: Restore symmetry: termination match, equal path parasitics, continuous return plane, controlled via transitions. Then re-qualify the preset window within guardrails (avoid “fixing” CM conversion by over-emphasis).

Pass criteria: BER ≤ X over X min; TJ@BER=XX ps; port-to-port margin delta ≤ X UI; VOCM within [X,X] V at the declared boundary.