Video Format Bridges for HDMI↔MIPI, DP↔LVDS & CSI↔Parallel
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A Video Format Bridge is an engineering tool that makes two video interfaces interoperable by owning the control plane (EDID/HPD/AUX/DDC), the pixel/transport plane (format/packing/timing), and the clock/CDC plane (PLL/buffers/latency) so bring-up and mode-switching are repeatable.
Most “no image” failures are not raw link errors—success comes from validating these three planes with logs, counters, and pass/fail thresholds, then selecting the right bridge/buffer architecture for the required modes.
H2-1 · What is a Video Format Bridge
Page boundary (scope control)
This page covers format/protocol bridging (control handshakes, pixel transport/packing, and clock-domain decoupling). It does not deep-dive PHY eye/equalization/long-cable SI, ESD/TVS sizing, or retimer internals (handled in sibling pages).
Engineering definition
A video format bridge terminates the source-side control link, translates pixel transport/packing, and decouples clock/reset domains to present a different downstream interface with predictable latency and repeatable bring-up behavior.
What it solves (typical failure pattern)
- “Black screen” caused by control-plane mismatch (EDID/HPD/AUX/DDC), not raw signal integrity.
- Color/timing artifacts caused by packing/colorspace/bit-depth mismatch, not random bit errors.
- Periodic tear/drop caused by clock-domain drift and buffer under/overflow, not cable loss.
What it does NOT replace (boundary guard)
- Retimer/redriver tasks: cleaning an eye, recovering margin on long links, or compensating insertion loss.
- ESD/EMI compliance building blocks: TVS selection, CM choke tuning, surge/IEC robustness.
- Full PHY training theory: link equalization presets and deep electrical compliance (refer to interface-specific pages).
The 3-plane responsibility model (debug starts here)
1) Link / Control plane
Owns EDID/HPD, AUX/DDC transactions, sideband I²C proxying, and lane/mode announcements. Failures look like: EDID reads but no image; different sources behave differently; hot-plug causes endless retrain loops.
2) Pixel / Transport plane
Owns packing/unpacking, colorspace/bit-depth constraints, stream↔packet conversion, and lane mapping. Failures look like: color tint, snow/tiles, stable still image but unstable motion, “works at 720p but fails at 1080p”.
3) Clock / Reset plane
Owns PLL/gearbox, CDC isolation, elastic or frame buffering, and mode-set/reset sequencing. Failures look like: periodic tear, one-frame corruption, every-N-seconds blink, underflow/overflow counters incrementing.
Bridge vs retimer/redriver vs simple converter (quick discriminator)
- Bridge: input and output protocols differ (HDMI↔MIPI, DP↔LVDS, CSI↔Parallel) and control-plane proxying is required (EDID/HPD/AUX/DDC).
- Retimer/Redriver: protocol stays the same; the goal is margin recovery (training/BER/CRC that worsens with insertion loss or cable length).
- Simple converter: electrical/media conversion without terminating or emulating upstream control and capability negotiation (limited interoperability).
H2-2 · Use Cases & Mapping Matrix (within this page boundary)
The purpose of this section is strict scope control and fast routing: identify the bridge class (In→Out), attach the dominant risk labels, then jump to the first chapter that yields actionable probes and pass/fail criteria.
Mapping matrix (practical routing fields)
| In → Out | Control proxy | Transport / packing | CDC / buffer | Mode-set risk | Audio | Protection | Bring-up safe mode | Start here |
|---|---|---|---|---|---|---|---|---|
| HDMI → CSI-2 | EDID/HPD + DDC | TMDS/FRL → packetize (CSI) | Elastic FIFO (typ.) / optional frame buffer | Medium | Drop / extract | Mention-only (HDCP cases) | 1280×720@60, RGB 8b, no audio | H2-3 / H2-4 / H2-5 |
| HDMI → DSI | EDID/HPD + DDC | HDMI pixels → DSI video mode | Tight CDC + panel timing constraints | High | Usually drop | Mention-only | 800×480 or 1024×600 (panel-safe), RGB 8b | H2-6 / H2-5 |
| DP → LVDS | AUX training + EDID-like sink data | Main Link → panel stream timing | Often needs buffering for training/mode-set | Medium | Drop | Mention-only | 1280×720@60 or native panel timing, RGB 8b | H2-3 / H2-4 |
| CSI-2 → Parallel | Sensor sideband (I²C) proxy (optional) | Depacketize + DE/HS/VS synthesis | CDC to pixel clock domain | Medium | N/A | N/A | Match sensor native format first (8b), then expand | H2-4 / H2-5 |
| Parallel → CSI-2 (optional) | Upstream camera expectations (strict) | Packetize + timing compliance | Buffering required for deterministic framing | High | N/A | N/A | Lower rate first; lock frame markers before scaling up | H2-6 / H2-5 |
Tip: Start with the “Bring-up safe mode” row values to eliminate format and negotiation variables before increasing resolution, rate, or optional features.
Quick routing by symptom (first chapter to read)
- EDID reads OK but screen stays black → Control-plane (EDID/HPD/AUX/DDC) next.
- Image appears but shows tint/snow/tiles → Pixel/packing next.
- Periodic tear/blink every N seconds → Clock/CDC + buffer next.
- Fails only on mode switch or hot-plug → Mode-set sequencing next.
Quick routing by system requirement (buffer/scaler fork)
- Needs resolution/frame-rate conversion (or strong tolerance to input timing drift) → prefer frame buffer architecture (higher latency, higher interoperability).
- Needs low latency and fixed timing (format shift only) → prefer elastic/line buffer architecture (tight CDC and sequencing discipline).
- Interoperability must survive many sources/sinks → prioritize control-plane robustness (EDID fallbacks, HPD debounce, AUX retry policies).
H2-3 · Control-Plane: EDID / HPD / AUX / DDC Ownership
In video bridging, “no picture” is most often a control-plane mismatch, not corrupted pixel data. This section locks the ownership model (who generates, caches, and advertises capabilities) and the sequencing rules that make bring-up repeatable.
Scope guard (no cross-page expansion)
This section focuses on control ownership and transaction behavior (EDID/HPD/AUX/DDC). Physical signaling margins, eye diagrams, equalization tuning, and long-cable SI are treated as external prerequisites and belong to the interface-specific PHY pages.
Ownership matrix (who owns what, and when)
| Bridge role | What it must provide | Cache / update policy | “No picture” signature if wrong | First evidence to collect |
|---|---|---|---|---|
| HDMI input (bridge acts as sink) | EDID template or synthesized EDID, stable HPD behavior, DDC transaction handling | EDID must be ready before HPD assertion; updates only on explicit state transitions (hot-plug / mode profile change) | EDID read succeeds, but source selects an unsupported mode; black screen after mode-set or on hot-plug | DDC log: EDID blocks read, checksum, chosen mode, HPD transitions (timestamps) |
| DP input (bridge terminates AUX as sink) | AUX responses, capability mapping, training/parameter visibility (as implemented by the bridge) | Cache down-stream constraints and serve stable AUX reads; define retry/timeout behavior with counters | Training loops, periodic black screen on mode-set, different hosts show different lock behavior | AUX transcript: request/response, timeouts, retries, chosen link parameters (plus bridge counters) |
| Downstream panel (DSI/LVDS/Parallel) | A deterministic “capability contract” equivalent: supported timing set, pixel format constraints, and mode-change rules | Panel constraints must dominate the upstream advertisement; any EDID/capability merge must be reproducible across resets | Source selects a mode “allowed” upstream but not actually realizable downstream; black screen or unstable image after switching | Mode-set record: selected mode, downstream applied timing, and transition timing (reset/enable) |
Practical rule: upstream advertisement must never exceed what the downstream can actually render. If the merge policy is not deterministic, interoperability becomes source-dependent.
Control-plane state machine (events and triggers)
S0 · Power rails not stable
HPD forced low; DDC/AUX blocked. Trigger to exit: rails OK + ref clock stable (threshold X placeholder).
S1 · Capability ready (EDID/AUX data prepared)
EDID cached or synthesized; AUX mapping ready. Trigger to exit: HPD assert allowed (debounce X placeholder).
S2 · Negotiation (source reads EDID / performs AUX reads)
DDC/AUX transactions must be consistent and repeatable. Trigger to exit: mode selected + stable transactions (retry policy visible).
S3 · Mode-set transition
Bridge applies pixel/clock settings and transitions enable. Trigger to exit: pixel enable + stable counters (no under/over events).
S4 · Steady state + hot-plug handling
HPD pulses (if used) must be deliberate and debounced; EDID updates must precede any re-negotation. Trigger to re-enter: hot-plug / source reset / explicit mode change.
Packet capture / logging checklist (evidence-first)
- HPD transitions with timestamps (assert, deassert, pulse width; debounce status).
- EDID blocks read (including checksum status) and the selected mode derived by the source.
- DDC error counters: NACK/timeout/retry count; arbitration conflicts (if any).
- AUX transcript (DP): request/response codes, timeout/retry counts, and final parameter selection.
- Mode-set record inside the bridge: applied pixel format + timing profile ID + transition timestamp.
Routing rule (avoid dead ends)
If EDID/AUX transactions are stable and HPD behavior is clean, but black screen persists after mode-set, the dominant cause is likely in pixel packing/timing (H2-4) or clock/CDC buffering (H2-5), not the control plane.
H2-4 · Pixel/Transport Plane: Packing, Color, Timing, Audio
In bridging, artifacts are more often caused by format and timing mismatches than random bit errors. This section turns pixel transport into a deterministic check path: lock a minimum-viable link (MVP), validate packing and timing, then add complexity (colorspace, bit depth, audio).
Pixel-plane model (4 dimensions that must agree)
1) Colorspace
RGB vs YUV; 4:4:4 / 4:2:2 / 4:2:0. Mismatches typically show tint (purple/green) or incorrect luma/chroma separation.
2) Bit depth
8/10/12 bpc support must match both ends. Mismatches show contouring, banding, or “sparkle-like” artifacts that correlate with edges.
3) Timing model
Active/blanking, porch, sync polarity, and DE/HS/VS behavior (especially for CSI↔Parallel). Timing disagreement often shows unstable lock, tearing, or intermittent black frames.
4) Packing / transport
Stream↔packet conversion, lane mapping, and gearbox packing. Errors here show snow/tiles, line slips, or “still image OK but motion fails”.
MVP bring-up recipe (freeze variables first)
Step 1 · Lock a conservative mode
Start with 1280×720@60, RGB 8b (or a known panel-safe timing) to avoid bandwidth edges. Pass criteria: stable image for X minutes, no line slips, no periodic tear.
Step 2 · Disable optional features
Disable audio, high bit depth, complex colorspace conversions, and any non-essential overlays. Goal: validate packing and timing with minimal degrees of freedom.
Step 3 · Use golden patterns
Validate with color bars + moving checkerboard + a frame counter overlay (if supported). These separate “format errors” (tint/tiles) from “CDC errors” (periodic tear/skip).
Step 4 · Add one variable at a time
Change only one dimension per step: colorspace → bit depth → resolution/rate → audio. Pass criteria: no new artifacts and counters stay within threshold X placeholders.
Symptom → likely cause → first probe (evidence-driven)
| Symptom | Likely cause (dimension) | First probe / check |
|---|---|---|
| Purple/green tint or inverted colors | Colorspace / range / byte order | Read detected input format + configured output packing; verify RGB↔YUV mode matches the sink expectation |
| Snow/tiles or periodic “line slip” | Packing / gearbox / lane mapping | Check packet/line counters, mapping configuration, and “payload size per line” consistency (avoid dynamic changes during motion) |
| Works at 720p but fails at 1080p | Bandwidth edge or bit-depth/colorspace combination not supported | Reduce one axis: keep resolution, drop bit depth; or keep bit depth, drop colorspace complexity; verify sink constraints |
| Periodic tear or blink every N seconds | Timing drift + CDC buffer under/overflow | Read FIFO fill level trend + under/over counters; correlate with blink period (route to clock/CDC section) |
| Audio disappears after resolution switch | Mode-set sequencing resets the audio path | Confirm mode-change event order and audio enable gating; verify whether audio is pass/drop/extract per profile |
Note: if the control plane is clean (stable EDID/AUX and HPD), persistent pixel issues almost always reduce to a mismatched combination of the four dimensions above.
Audio handling (bridge boundary)
- Audio modes are typically drop, pass-through, or extract (e.g., to an external audio path).
- If audio fails only after mode switching, treat it as a sequencing issue (order of resets/enables), not a pixel packing issue.
- Audio protocol details and electrical transport belong to dedicated audio/interface pages; this page only covers bridging control interactions.
H2-5 · Clocking & Domain Crossing: PLL, Gearbox, Buffer Depth, Latency
Clock-domain crossing is the root of long-run bridge stability. If write and read clocks drift, FIFO fill will move, and failures appear as underflow/overflow, periodic tearing, or a black flash every N seconds. This section makes CDC behavior observable and controllable.
Scope guard (no cross-page expansion)
Focus: PLL/gearbox/elastic buffering, fill-level observability, and resync policy. Deep protocol/PHY training math and SI/eye margins are out of scope for this page and should be handled by interface-specific pages.
CDC architectures (trade-offs that matter in bridging)
| Architecture | Latency (typ / worst) | Robustness to drift/jitter | Failure signature | Best-fit scenarios | Must-have observability |
|---|---|---|---|---|---|
| Line buffer | Low / Low (lines) | Weak against ppm drift; limited jitter absorption | Periodic tear/flash every N seconds when clocks mismatch | Lowest-latency pipelines with controlled clocks or lock-to-reference systems | Line counters, occasional slip flags, timing drift indicator (placeholder) |
| Frame buffer | High / High (frames) | Strong compatibility; can hide drift and many transient behaviors | Longer blackout on mode switch; memory/bandwidth edge failures | Multi-source interoperability, timing mismatch tolerance, systems that allow end-to-end delay | Frame boundary markers, buffer occupancy, memory under/over events |
| Elastic buffer + PLL tracking | Medium / Medium (lines to sub-frames) | Balanced; absorbs short-term jitter and manages long-term drift via tracking | Fill-level hunting, rare resync flashes if thresholds/rates are poorly tuned | Low-latency systems needing robust multi-source support without full frame buffering | FIFO fill level + slope, high/low watermarks, resync counters, tracking status |
Engineering note: periodic artifacts strongly suggest deterministic drift. Measure fill-level slope and watermark hit frequency before changing pixel-format settings.
Buffer sizing checklist (from evidence → thresholds)
- Identify write clock and read clock sources (common reference vs free-run). Record expected drift drivers (temperature, supply, mode changes).
- Define whether the pipeline requires frame boundary alignment (packet/frame markers, DE/HS/VS) or only line continuity.
- Log FIFO fill level over time and compute a drift indicator (fill slope; placeholder).
- Choose headroom: set low watermark and high watermark with margin for worst-case drift (threshold X placeholders).
- Define resync policy: soft resync (adjust/read pacing in blanking) vs hard resync (clear/re-align boundaries).
- Pass criteria: zero under/over events for X minutes; watermark hits below threshold X; no periodic tear/flash across temperature sweep (placeholders).
Latency budget (placeholders for system constraints)
Static latency
Line-buffer style: latency ≈ (N_lines × line_time). Frame-buffer style: latency ≈ (N_frames × frame_time). Use placeholders: line_time = X µs, frame_time = X ms, N_lines / N_frames = X.
Dynamic latency (resync & recovery)
Any resync makes latency non-constant. Define worst-case: max blackout = X ms, max alignment time = X lines, and allowable frequency = X per hour (placeholders).
Symptom cue
If artifacts are periodic (every N seconds), prioritize fill-level slope and watermark hit logs before modifying format settings or assuming random errors.
H2-6 · Link Initialization & Mode-Set Sequencing (Reset/Training/Hot-Plug)
Bring-up must be executable, not “try-and-see”. This section defines a deterministic sequence from power-on to steady video, with a first probe point and pass criteria placeholders at every step. The same structure applies to hot-plug and re-training behavior.
Bring-up 12-step flow (each step: action → first probe → pass criteria)
Step 1 · Power rails
Probe: rail-good flags / brownout logs. Pass: stable for X ms (placeholder). If fail: power/PMIC domain.
Step 2 · Ref clock stable
Probe: refclk stable indicator / PLL pre-lock. Pass: stable within X ms (placeholder). If fail: clock tree.
Step 3 · Reset asserted
Probe: reset pin state + internal reset cause. Pass: asserted until rails/clock ok. If fail: reset wiring/polarity.
Step 4 · Reset deassert + settle
Probe: device ready flag / firmware boot log. Pass: ready within X ms (placeholder). If fail: boot/straps.
Step 5 · Prepare capability data
Probe: EDID cache valid / AUX mapping ready. Pass: valid before HPD assert. If fail: route to control-plane (H2-3).
Step 6 · HPD assert (gated)
Probe: HPD transition timestamp + debounce status. Pass: no jitter; debounce = X ms (placeholder). If fail: control-plane (H2-3).
Step 7 · Negotiation
Probe: DDC/AUX transactions (timeouts/retries). Pass: retry count < X (placeholder). If fail: control-plane (H2-3).
Step 8 · Apply mode profile
Probe: selected mode ID + output timing registers. Pass: exact match to profile. If fail: pixel/timing (H2-4).
Step 9 · Arm CDC/PLL
Probe: PLL lock + FIFO fill within window. Pass: fill stable; no under/over. If fail: CDC (H2-5).
Step 10 · Enable pixel output
Probe: pixel enable gate + line/frame counters. Pass: counters monotonic; no slips for X frames (placeholder). If fail: H2-4/H2-5.
Step 11 · Steady-state monitoring
Probe: FIFO watermark hits + error counters. Pass: < X per minute (placeholder). If fail: CDC thresholds/resync policy (H2-5).
Step 12 · Hot-plug / re-train handler
Probe: HPD pulse width + post-pulse settle. Pass: pulse width = X ms; settle = X ms (placeholders). If fail: H2-3 sequencing.
Failure localization rule
If negotiation is clean (EDID/AUX stable) but the image tears or flashes periodically, prioritize CDC logs: FIFO fill, watermark hits, and resync counters (H2-5).
H2-7 · Signal Integrity Boundary: What to Assume vs What to Push to PHY Pages
This page treats signal integrity as an input condition, not a tuning guide. The bridge scope keeps only capability constraints (lane count/rate/encoding class) and uses a routing rule to separate control-plane, pixel-plane, clock/CDC, and PHY-layer issues without expanding into HDMI/DP/MIPI/retimer SI theory.
Scope guard (SI boundary for the bridge page)
- Keep here: lane count, lane-rate range, encoding family class, and required “link health” flags/counters.
- Push out: eye/jitter decomposition, CTLE/DFE/FFE tuning, channel loss/reflection/crosstalk modeling, and compliance measurement procedures.
- Use the router below to decide whether the symptom is control-plane, pixel-plane, clock/CDC, or PHY-layer.
Boundary matrix: keep vs route out (no cross-page expansion)
| Category | Keep on bridge page | Route to PHY pages | First probe point (bridge scope) |
|---|---|---|---|
| Link constraints | Lane count (X), lane-rate range (X–Y), encoding family class, allowable pixel-clock range (X–Y placeholders) | Eye/jitter margin methodology, channel budget modeling, compliance test setup | Training/lock status + error counters + “link stable” flag |
| Equalization | EQ as requirements (e.g., “must train to a stable preset”, placeholder) and “known-good preset” artifacts | CTLE/DFE/FFE scan strategy and tuning loops | Retry/timeout counters; stability window X; preset ID captured |
| Symptom mapping | “Which plane?” routing: Control vs Pixel vs Clock/CDC vs PHY | Deep SI root-cause (cables, return paths, reflections, crosstalk) | Control logs (EDID/AUX), mode record, FIFO fill/watermarks, training result |
| Compliance mindset | Save artifacts and presets so issues are reproducible (see H2-8) | PHY compliance templates and measurement details | Artifacts: training logs + preset IDs + firmware/config snapshot |
Practical rule: if negotiation is clean but artifacts are periodic (every N seconds), treat it as CDC until proven otherwise (FIFO fill, watermarks, resync counters).
Troubleshooting router (symptom → first probe → primary chapter)
Black screen but EDID reads OK
First probe: mode-set record + output timing; then FIFO fill window. Primary: Pixel plane (H2-4) → Clock/CDC (H2-5).
Periodic tear/flash every N seconds
First probe: FIFO fill slope + watermark hits + under/over counters. Primary: Clock/CDC (H2-5).
Hot-plug works once, then fails to recover
First probe: HPD pulse width + debounce + EDID-ready gating order. Primary: Sequencing (H2-6) → Control plane (H2-3).
Color is wrong / image is stable but “looks off”
First probe: colorspace + packing + bit depth settings. Primary: Pixel plane (H2-4).
Training fails or link never locks
First probe: training/lock status + retry/timeout counters. Primary: PHY pages (HDMI / DP / MIPI / Retimer). This page keeps only “input condition” requirements.
H2-8 · Compliance Hooks & Artifacts (EDID/HDCP/PCI-SIG-like mindset)
Bridge projects fail late when interoperability artifacts are missing. This section defines the minimum reproducibility package: EDID governance, content-protection presence boundaries, and logs/presets that must be saved from bring-up through validation and production.
Artifacts checklist (copy-ready for project tracking)
Bring-up (field reproducibility)
- EDID dump (raw) + checksum OK + hash ID (placeholders)
- Fallback EDID profile + activation condition (placeholders)
- AUX/DDC transaction log (timeouts, retries, error codes)
- Mode-set record (resolution, color, bit depth, packing, output timing)
- CDC snapshot (FIFO fill, watermark hits, under/over counters)
- Firmware revision + config snapshot (must bind to artifact bundle ID)
Validation (EVT/DVT regression)
- Pass matrix: modes × sources × sinks (placeholder structure)
- Known-good presets: training preset IDs / EQ preset IDs (saved, not explained)
- Failure bundle: symptom + logs + dumps + exact FW/config ID
- Mode-switch black screen budget: max blackout X ms (placeholder)
Production (traceability)
- Release bundle ID → firmware revision → config checksum mapping (placeholders)
- Locked EDID set + policy (when/why fallback triggers)
- Manufacturing log schema: required fields and retention window (placeholders)
- Compatibility change note: what changed, why, and how verified
EDID governance rule
Any EDID update must happen before HPD pulse that triggers re-read. Store both raw and fallback dumps and bind them to the same artifact bundle ID (placeholders).
Content protection boundary (no crypto detail)
Treat HDCP/DRM as a presence constraint: supported/transparent/not supported (placeholders). Do not expand into key management or encryption flows on this page.
H2-9 · Debug & Instrumentation: Probes, Logs, and Golden Patterns
Debug must start with first probe points and consistent observability. Without a fixed probe order, parameter changes become infinite. This section defines a minimal instrumentation loop: where to probe (control/pixel/clock), which counters to expose, and golden patterns to separate tearing, color mismatch, and frame loss.
First 5 probes (fixed order)
Probe-1 (Control): DDC/AUX + HPD edges
- Observe: timeouts, retries, NACK/error codes, HPD rise/fall/glitch counts
- Pass criteria: no timeout in X consecutive reads; HPD glitches < X (placeholders)
- Route next: Control-plane ownership (H2-3) / Sequencing (H2-6)
Probe-2 (Config): Mode-set record snapshot
- Observe: resolution/refresh, colorspace, bit depth, packing, output timing ID
- Pass criteria: record hash remains stable across X attempts (placeholder)
- Route next: Pixel/transport packing & timing (H2-4)
Probe-3 (Pixel): After input unpack
- Observe: in-frame counter, in-line counter, DE/HS/VS presence, format tag
- Pass criteria: monotonic frame count; expected lines per frame (placeholder)
- Route next: Pixel plane mismatch (H2-4)
Probe-4 (Clock): PLL lock stability window
- Observe: lock flag, lock-loss count, relock timestamps
- Pass criteria: lock-loss = 0 over X seconds; relock count < X (placeholders)
- Route next: Clocking & CDC fundamentals (H2-5) / Sequencing (H2-6)
Probe-5 (CDC): FIFO fill + watermarks + under/over
- Observe: min/max fill, watermark hits, underflow/overflow, resync events
- Pass criteria: fill stays within safe band; under/over = 0 (placeholders)
- Route next: Buffer depth & resync strategy (H2-5)
Counters to expose in firmware (minimal schema)
Control-plane
edid_read_ok / edid_read_fail · aux_timeout / aux_retry · ddc_nack / ddc_timeout · hpd_rise_cnt / hpd_fall_cnt / hpd_glitch_cnt · last_error_code(enum)
Pixel/transport
in_frame_cnt / out_frame_cnt · in_line_cnt / out_line_cnt · format_tag_in / format_tag_out(enum) · drop_frame_cnt / repeat_frame_cnt (if buffering) · crc_or_packet_err_cnt (if available)
Clock/CDC
pll_lock_loss_cnt · fifo_underflow_cnt / fifo_overflow_cnt · fifo_wm_hi_cnt / fifo_wm_lo_cnt · resync_event_cnt · fill_min / fill_max (windowed) · fill_slope_est (optional)
Logging rule: every field above must be tied to an artifact bundle ID (H2-8) and a mode-set record hash (Probe-2).
Golden patterns (fast discrimination)
Color bars
Use to detect colorspace/range/bit-depth mismatch. Typical signatures: stable image but wrong hues, crushed blacks, banding. Next: Pixel plane (H2-4) + confirm format_tag_in/out.
Moving checkerboard
Use to separate tearing, packing disorder, lane mapping issues. Motion amplifies periodic artifacts; edges reveal packing mistakes. Next: Pixel plane (H2-4) then CDC if periodic.
Frame counter overlay
Use to detect drop/repeat/freeze. Counter discontinuity correlates with FIFO under/over or resync events. Next: Clock/CDC (H2-5) + check fifo_underflow/overflow and resync_event_cnt.
H2-10 · Design Checklist (Schematic → Layout → Firmware → Bring-up → Production)
A bridge is a system: electrical ownership, control-plane behavior, pixel formatting, and clock/CDC must be verified across the full lifecycle. The checklist below stays within bridge scope: layout focuses on partitioning and clock loops, while deep SI tuning is routed to PHY pages.
Schematic checklist
- Power rails sequencing: rails stable before releasing reset (X ms placeholder)
- Refclk ownership: source, gating, and “refclk-good” definition (placeholder)
- I²C pull-up ownership: which side provides pull-ups and when they are valid
- HPD level compatibility: default level, tolerance, and clamp policy (placeholders)
- Straps/config defaults: safe-mode fallback must be deterministic
- Pass criteria: EDID readable X times after HPD assert; no DDC timeout (placeholders)
Layout checklist (bridge-only)
- Clock loop partitioning: keep PLL/refclk loop compact and isolated
- Control-plane routing hygiene: DDC/AUX routing consistent with pull-up ownership
- I/O zoning: separate high-activity pixel logic from control rails/lines
- Return continuity rule: avoid split references around bridge I/O regions
- ESD return awareness: define return path policy for connector protection parts
- Pass criteria: no HPD glitches induced by local switching events (X placeholder)
Note: SI details (eye/jitter, equalization tuning, channel modeling) are routed to PHY pages to avoid cross-page overlap.
Firmware checklist
- EDID fallback policy: trigger condition, versioning, and checksum validation
- Hot-plug debounce: HPD pulse width X ms + glitch filter (placeholders)
- Safe defaults: minimal-known-good mode to start (e.g., 720p/60 RGB 8b placeholder)
- Expose counters: schema from H2-9 + bind to bundle ID (H2-8)
- Resync strategy: FIFO watermark thresholds and max resync rate (placeholders)
- Pass criteria: mode record hash stable; no lock-loss in X seconds (placeholders)
Bring-up checklist
- Verify Probe-1 to Probe-5 in order; do not tune before observability is clean
- Golden patterns: color bars + moving checkerboard + frame counter overlay
- Clock/CDC: fifo_under/over = 0 over X minutes; fill within safe band (placeholders)
- Mode switch: blackout < X ms; no permanent black after switch (placeholders)
- Artifacts: save dumps/logs as a bundle with FW/config ID (H2-8)
- Pass criteria: stable output for X minutes across hot-plug cycle X times (placeholders)
Production checklist
- Self-test/BIST: deterministic pattern path + counters snapshot
- Traceability fields: bundle ID, FW revision, config checksum, mode hash (placeholders)
- Locked EDID policy: approved EDID set + fallback mapping
- Regression gate: known-good presets cannot change without pass matrix update
- Retention: define artifact retention window X days (placeholder)
- Pass criteria: station-to-station mismatch < X; failure bundle reproducible (placeholders)
IC Selection Logic: Bridge vs Scaler vs Retimer (Boundaries + Key Metrics)
Selection is treated as an engineering decision tree plus verification gates. This section lists representative material numbers for bridge-class devices (and a few boundary examples for retimers) while avoiding product-page sprawl.
- Retimer/Redriver appears only as a routing result; SI/eye/equalization methods belong to PHY/retimer pages.
- Scaler is included only as a need-or-not branch (resolution/frame-rate change), not algorithm details.
- Material numbers are representative; verify package, suffix, licensing (HDCP), and availability.
A) Decision Tree (classify first, then compare)
No → continue to Gate-2.
No → continue to Gate-3.
No → continue to Gate-4.
No → minimal-control bridge may still be sufficient (MVP-first).
B) Key Metrics to Compare (bridge-class, within page boundary)
| Metric | Why it matters | Quick check | Pass criteria (placeholder) |
|---|---|---|---|
| Supported input/output mode set | Prevents late surprises (unsupported bit-depth/colorspace or blanking limits). | Enumerate modes; record any conditional limitations (e.g., 4:2:0 only at high rates). | Target modes covered ≥ X%; no silent fallback. |
| Buffer architecture (line / elastic / frame) | Determines latency and tolerance to clock mismatch / mode switching. | Confirm FIFO/frame store presence; verify counters: under/over, watermark events. | Under/over counters = 0 over X hours; no periodic tearing. |
| Control-plane ownership (EDID/HPD/AUX/DDC) | Black-screen is often a control-plane mismatch rather than data corruption. | Verify: EDID cache/fallback; HPD debounce/pulse; AUX/DDC proxy timeouts and retry. | EDID stable across reset; HPD pulse width within X ms; AUX/DDC error rate < X. |
| Mode-set behavior (blackout / recovery) | Prevents “works once, fails on switch” field issues. | Execute repeated mode switches; log transitions and any PLL/FIFO events. | Blackout < X ms; no latch-up; recovery success ≥ X%. |
| Debug counters / logs / dumps | Enables deterministic troubleshooting (first probe points). | Confirm exposure of: PLL lock, FIFO fill, under/over, EDID/AUX/DDC transactions. | Required counters present; trace export in < X minutes. |
C) Representative Material Numbers (examples, not exhaustive)
Use these as starting points for category-fit. Always verify: package/suffix, HDCP licensing requirements, lane/rate limits, and firmware tooling.
| Category | Material No. | Typical mapping | Notes (engineering) |
|---|---|---|---|
| HDMI → CSI-2 bridge | TC358743XBG | HDMI 1.4 → MIPI CSI-2 | Control-plane ownership + CSI packetization; validate EDID/HPD bring-up first. |
| HDMI → DSI bridge | TC358870XBG | HDMI 1.4b → MIPI DSI | Mode-set sequencing and clocking are frequent failure points; log PLL/FIFO events. |
| HDMI → DSI (with scaling) | TC358779XBG | HDMI → MIPI DSI (scaler/de-interlace) | Choose only when resolution/frame-rate conversion is required; latency budget must be explicit. |
| HDMI 2.0 → MIPI/LVDS converter | LT6911UXC | HDMI 2.0 → CSI/DSI/LVDS | Useful when higher HDMI bandwidth is needed; confirm firmware tooling and debug visibility. |
| DSI → LVDS bridge (single-link) | SN65DSI83 | MIPI DSI → LVDS | Confirm bpp support and pixel clock range; verify colorspace/packing expectations. |
| DSI → LVDS bridge (dual-link) | SN65DSI85 | MIPI DSI → LVDS (higher bandwidth) | Prefer when resolution/refresh pushes beyond single-link margin; validate mode-set repeatability. |
| (e)DP → LVDS bridge | PTN3460 / PTN3460I | (e)DP main link → LVDS panel | DP control-plane (AUX) ownership matters; treat training/mode-set as first-class logs. |
| CSI-2 ↔ Parallel bridge | TC358746AXBG | CSI-2 → Parallel (and reverse) | Useful for CSI↔Parallel bring-up; validate PCLK limits and timing polarity expectations. |
| CSI-2 ↔ Parallel bridge | TC358748XBG | CSI-2 ↔ Parallel (variant) | Same class as TC358746; confirm register map, interface options, and tool support. |
| Boundary examples (retimer/redriver) | TDP142 / TMDS181 | DP redriver / HDMI TMDS retimer | Listed only to clarify “same protocol reach-extension”; SI methodology belongs elsewhere. |
- U? Video format bridge IC (selected class + firmware/counters requirement)
- U? Optional scaler/frame-buffer IC (only if Gate-1 = YES)
- U? Optional retimer/redriver (only if Gate-3 = YES)
- R/C? DDC/AUX pull-ups / level considerations (ownership defined in H2-3)
D) Verification Use-Cases (turn selection into deliverables)
- Lock a conservative mode (e.g., 720p60 RGB 8b) and keep it stable.
- Pass criteria: EDID stable, no lock-loss, FIFO under/over = 0 for X minutes.
- Run target modes across bit-depth/colorspace boundaries used in the system.
- Pass criteria: blackout < X ms, recovery success ≥ X%, no periodic tearing.
- Run for X hours and perform hot-plug cycles (X times).
- Pass criteria: artifacts captured (EDID dump, AUX/DDC logs, mode-set record), and counters show no accumulating errors.
- Chosen class: Bridge / Bridge+Scaler / Retimer boundary
- Target modes list (input/output) + any conditional restrictions
- Latency budget and buffer architecture assumption
- Required counters/logs + how to retrieve them in X minutes
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FAQs (Troubleshooting, within this page boundary)
Each answer is intentionally short and executable, using a fixed four-line structure: Likely cause / Quick check / Fix / Pass criteria (threshold placeholders X).
