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Microwave Oven Inverter Drive, Sensing & Interlock Debug Guide

Microwave Oven Inverter Drive, Sensing & Interlock Debug Guide

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Key takeaway

Core idea: This page turns common microwave oven failures into a fast, evidence-based workflow—use primary-side current, multi-point temperature slope, interlock states, VDD droop, and fault counters to isolate inverter/magnetron drive, thermal, safety, PSU, and EMC issues with minimal probing.

Outcome: For each symptom, it shows the first two measurements and the one discriminator that proves the root cause, so fixes target the real failure path instead of guesswork.

H2-1 · What this page covers · Boundary + intent mapping

What this page covers: microwave inverter drive, sensing evidence, and safety cutoffs

This page is strictly scoped to microwave oven hardware evidence: the HV inverter → magnetron load path, current/temperature/airflow monitoring, door interlock safety chain, and reset/EMC immunity around high-dv/dt switching. It does not cover cooking recipes, other kitchen appliances, or cloud/app ecosystems.

How to use this page: start with the symptom that matches the field unit, then jump to the first evidence points (two measurements) to separate power integrity vs control-loop vs interlock vs thermal.

Four common engineering intents (each maps to a measurement-first path)

Intent AWeak heating / unstable microwave power

Focus: inverter→magnetron chain + current evidence.

First evidence: primary current waveform + drive enable timing.
Jump: H2-3 → H2-5 → H2-9

Intent BTrips / resets exactly at start

Focus: power tree, inrush, UVLO, EMI-injection into low-voltage rails.

First evidence: MCU VDD droop + inverter enable edge correlation.
Jump: H2-2 → H2-6 → H2-9

Intent CDoor closed but “won’t start” / interlock error

Focus: interlock state combination + contact bounce evidence.

First evidence: interlock GPIO states + bounce/time signature.
Jump: H2-7 → H2-9

Intent DThermal trips / fan anomalies / intermittent stop

Focus: NTC temperature slope vs fan tach vs airflow constraints.

First evidence: temperature rise slope + fan tach continuity.
Jump: H2-5 → H2-8 → H2-9

Evidence chain the content always “lands on”

  • Energy path: AC mains → EMI filter → (optional PFC) → HV inverter stage → HV network → magnetron load.
  • Low-voltage control: SMPS rails (3.3/5/12/24V) → MCU + drivers → inverter enable / relay / fan / turntable.
  • Safety cutoffs: door interlock chain + hard disable of HV enable (and fault latched behavior).
  • Telemetry: primary current sense, NTCs, fan tach, interlock states, brownout/reset flags, fault counters.
Figure F1. Microwave oven intent-to-evidence map Block diagram linking four common field intents to evidence points: current waveform, VDD droop, interlock states, temperature slope, and fan tach. Microwave Oven — Intent → Evidence → Jump Targets Use symptom cards to pick the first two measurements. Keep scope: inverter/magnetron + sensing + interlocks + PSU/EMC. Intent A Weak heating / power unstable Evidence: primary current waveform + drive enable timing Jump: H2-3 / H2-5 / H2-9 Intent B Trip / reset at start Evidence: MCU VDD droop + inverter enable correlation Jump: H2-2 / H2-6 / H2-9 Intent C Door closed but won’t start Evidence: interlock state combination + contact bounce Jump: H2-7 / H2-9 Intent D Thermal trip / intermittent stop Evidence: temperature rise slope + fan tach continuity Jump: H2-5 / H2-8 / H2-9 Core evidence points: I_primary MCU VDD Interlock states NTC slope Fan tach Fault log Three layers to keep reasoning clean: High-energy path AC → HV inverter → HV network → magnetron Low-voltage control SMPS rails → MCU → enable / relay / fan Evidence/telemetry I / T / tach / interlocks / reset flags / logs ICNavigator
Cite this figure Figure ID: F1 · ICNavigator
Figure F1. Intent-to-evidence map for microwave inverter systems. Each intent binds to two “first measurements” to reduce misdiagnosis.
Suggested citation (copy/paste): ICNavigator — Figure F1 (Microwave Oven Intent→Evidence Map), accessed YYYY-MM-DD.
H2-2 · System block map · power tree + control loops

System block map: power tree, control domains, and the two loops that matter

Microwave ovens with inverter magnetron drive combine a high-energy switching path and a low-voltage control path. Field symptoms often look “random” until the system is separated into domains and each domain is tied to its measurable evidence point.

Minimum viable block map (enough to identify the platform variant)

  • AC mains entry: line/fuse → EMI filter (CM choke + X/Y network) → optional PFC stage (platform dependent).
  • Low-voltage rails: offline SMPS generates 3.3/5/12/24V for MCU, UI, relays, fan drive, turntable motor, and auxiliary loads.
  • HV generation: inverter power stage converts from mains (or boosted bus) into HV applied to the magnetron through an HV network.
  • Sensors: primary current sense (fast), temperature NTCs (slow), fan tach (discrete), door interlocks (binary states).
  • Actuators: gate-drive enable, relays/SSR cutoffs, fan control, turntable motor, lamp, beeper.

Two closed loops that must be kept distinct (and each has a “first evidence”)

Loop 1 · Microwave power regulation

Goal: stable delivered power (as seen by current/energy behavior), despite mains variation and load changes.

First evidence: primary current waveform shape + timing vs enable.
Failure signature: hunting, dropouts, repeated OCP/UVLO events, inconsistent heating.

Loop 2 · Thermal + safety cutoffs

Goal: prevent unsafe conditions with hard disable paths that remain valid under EMI and brownout.

First evidence: NTC rise slope + fan tach continuity + interlock state stability.
Failure signature: OTP trips after a delay, intermittent stop, “door” errors that correlate with vibration/bounce.

Design/diagnosis rule: If a symptom coincides with the inverter enable edge, start by correlating MCU VDD with primary current. If the symptom appears with a delay, start with temperature slope and fan tach continuity.
Figure F2. Microwave oven system block map Left-to-right block diagram showing AC entry and EMI filter, optional PFC, low-voltage SMPS, control MCU and UI, HV inverter stage to magnetron, and sensor/actuator connections. Microwave Oven — Power Tree & Control Domains (Minimum Block Map) Separate high-energy path, low-voltage control, and evidence/telemetry to avoid false root causes. High-energy path AC mains Line / Fuse EMI filter CM + X/Y PFC (opt.) platform variant HV inverter switching stage OCP / UVLO HV network snubber/clamp Magnetron load Low-voltage control Offline SMPS 3.3V / 5V 12V / 24V Control board MCU + watchdog brownout flags fault counters/log UI panel key/touch display/beep Actuators relay/SSR, fan, turntable lamp, buzzer HV enable Evidence / telemetry Primary current sense (fast) NTCs (slow) Fan tach Door interlocks + reset flags + logs state stability / bounce / counters ICNavigator
Cite this figure Figure ID: F2 · ICNavigator
Figure F2. Minimum block map for inverter-based microwave ovens. Distinguish energy path, low-voltage control, and telemetry to guide the first measurements.
Suggested citation (copy/paste): ICNavigator — Figure F2 (Microwave Oven Power Tree & Domains), accessed YYYY-MM-DD.
H2-3 · Inverter & magnetron drive architectures · variants → evidence

Inverter & magnetron drive architectures: identify the variant and predict the first evidence

This chapter is not a topology lecture. The purpose is to help engineering teams quickly classify the platform and form a correct expectation for what the first waveforms and state signals should look like. Each variant below is described using: why it exists, common failure signatures, and the first two measurements.

Safety note: high-voltage sections require qualified handling. Diagnosis should start with non-invasive proxies (primary current sense, low-voltage rails, enable timing, fault counters, temperature slope) before any deeper investigation.

Variant summary (architecture → symptoms → first evidence)

Architecture family Typical field symptoms First evidence (two quickest checks)
Legacy HV transformer + diode/cap Heating is weak but control board remains stable; fewer high-frequency EMI side effects; symptoms correlate more with mains sag than with switching activity. (1) AC input current shows mostly line-frequency behavior.
(2) MCU VDD is usually quiet at “heat start” compared to inverter platforms.
Inverter Hard-switched HV supply (PWM-like) Unstable heating (“hunts”), intermittent dropouts, start-up resets, or repeated protection events that line up with enable edges. UI glitches may appear only during heating. (1) Primary current waveform: pulse shape + periodic dropouts.
(2) Enable timing vs MCU VDD droop / reset flags (brownout correlation).
Inverter Resonant / soft-switch HV supply (frequency/burst control) Power “breathing” at certain duty windows, thermal trips after a delay, higher sensitivity to component drift (snubber/clamp, magnetics). Some units behave normally cold but degrade hot. (1) Primary current envelope and burst cadence (cold vs hot comparison).
(2) Temperature rise slope vs time (NTC) + fault counter pattern.
Load Magnetron interface (filament + anode HV behavior) Weak heating, delayed “power build-up”, or intermittent stops that follow thermal coupling. Abnormal current behavior may appear at start phase vs sustain phase. (1) Start→sustain transition in primary current waveform (continuity and stability).
(2) NTC slope under load (real overheating vs sensing chain error).

What to write (and what to avoid) for each variant

Write

Only measurable expectations and first probes.

• Expected current waveform style (envelope, dropouts, bursts)
• Enable timing relationships (HV enable vs VDD vs reset flags)
• Protection signatures (OCP/UVLO/OTP counters) and “when they trigger”

Avoid

Deep derivations and cross-topic expansion.

• Full converter math / resonance derivations
• Cooking behavior, recipes, or generic appliance comparisons
• Cloud/app integration and hub ecosystems

Figure F3. Architecture families → first evidence points Three microwave HV supply families and the recommended first two evidence checks for each: primary current waveform, enable timing, MCU VDD, and temperature slope. Architecture Families → First Evidence Points Classify the platform first. Then measure I_primary + enable timing before chasing secondary symptoms. Legacy HV Transformer Hard-Switched Inverter Resonant / Soft-Switch AC HV transformer Diode/Cap Magnetron Expected I(in) style First evidence • AC input current shape • MCU VDD quiet at start AC HV inverter (PWM) Gate driver Magnetron Expected I_primary First evidence • I_primary pulse + dropout • Enable vs VDD/reset flags AC Resonant stage Clamp/snubber Magnetron Expected envelope First evidence • Burst cadence (cold vs hot) • NTC slope + fault pattern Common evidence points (safe first) I_primary HV enable MCU VDD Reset flags NTC slope Fault counters ICNavigator
Cite this figure Figure ID: F3 · ICNavigator
Figure F3. Platform classification map. The first probes are kept on safe evidence points (current sense, enable timing, rails, temperature slope) to prevent false root causes.
Suggested citation (copy/paste): ICNavigator — Figure F3 (Microwave Architecture Families → Evidence), accessed YYYY-MM-DD.
H2-4 · HV power stage · components → stress → proof

HV power stage: key components, stress points, and what proves a failure

The HV section is best explained as a set of stress concentrators. When symptoms occur, diagnosis should focus on whether the evidence indicates electrical stress (dv/dt, surge, overcurrent), thermal stress (temperature slope), or insulation/leakage sensitivity (humidity/contamination correlation).

Goal of this chapter: make each component block diagnosable using Role → Main stress → What proves it failed. Avoid long derivations and keep evidence measurable (current waveform, rail droop, fault counters, temperature slope, correlation with heating events).

Component cards (Role / Main stress / What proves it failed)

Switch devices (MOSFET/IGBT)

Role: convert bus energy into controlled HV power.

Main stress: dv/dt ringing, surge energy, overcurrent spikes, thermal rise.
Proof: I_primary shows repetitive spikes/dropouts aligned to enable, OCP/UVLO events increase, heating becomes unstable under load.

Gate driver + drive loop

Role: ensure clean switching timing and noise immunity.

Main stress: ground bounce, EMI injection, undervoltage on driver rail.
Proof: instability appears only during heating; enable timing correlates with MCU VDD droop/reset flags; fault pattern depends on layout/return path.

Magnetics / transformer

Role: energy transfer and isolation boundary.

Main stress: leakage-induced overshoot, insulation aging, temperature/humidity sensitivity.
Proof: behavior degrades hot (cold OK, hot unstable); ringing-related symptoms increase; failures correlate with environment (humidity/contamination).

Snubber / clamp network

Role: limit overshoot/ringing and reduce EMI stress.

Main stress: pulse energy, self-heating, parameter drift.
Proof: EMI-linked UI issues and resets increase under power; current waveform becomes noisier; units vary strongly across component tolerances/batches.

HV network (rectification/filtering)

Role: shape HV delivery to the magnetron load.

Main stress: ripple current, peak voltage stress, thermal rise.
Proof: weak heating with abnormal start→sustain current transition; intermittent stops under load; fault counters show repeated attempts.

Insulation / creepage / leakage paths

Role: prevent leakage under contamination and humidity.

Main stress: surface contamination, moisture, carbon tracking risk.
Proof: failures correlate with humidity/grease/dust; cleaning yields temporary recovery; abnormal events happen at HV enable edges without clear low-voltage rail collapse.

Practical stress-to-evidence pairing (keeps troubleshooting vertical)

  • dv/dt / ringing stress → look for UI glitches/resets that occur only during heating + I_primary becoming noisier (correlate with enable timing).
  • surge / inrush stress → look for start-up trips and rail droop patterns (MCU VDD vs enable edge).
  • thermal stress → look for delayed trips and abnormal NTC rise slope vs time (fan tach continuity as a discriminator).
  • leakage sensitivity → look for humidity/contamination correlation and intermittent behavior that does not match clean rail droop signatures.
Figure F4. HV stage stress map → safe evidence points Block diagram highlighting stress hotspots in the HV inverter path and the recommended safe evidence points: I_primary, driver/MCU rails, enable timing, NTC slope, and fault counters. HV Power Stage — Stress Hotspots → Evidence Points Use safe proxies first: current sense, rails, enable timing, NTC slope, fault counters. High-energy HV chain (stress concentrates here) AC / Bus inrush/surge Switch devices dv/dt / OCP thermal rise Gate driver noise immunity Magnetics leakage overshoot Snubber/Clamp ringing / EMI HV network filter/shape Magnetron load + heat dv/dt heat surge isolation / leakage boundary Safe evidence points (recommended first) I_primary Pulse shape / dropouts Cold vs hot comparison Enable + rails HV enable timing MCU VDD droop / reset flags Thermal + logs NTC rise slope fault counters pattern ICNavigator
Cite this figure Figure ID: F4 · ICNavigator
Figure F4. HV stage stress map. Each hotspot is tied to a safe evidence point (current, rails, enable timing, temperature slope, fault counters) to keep troubleshooting vertical and repeatable.
Suggested citation (copy/paste): ICNavigator — Figure F4 (Microwave HV Stress Map → Evidence Points), accessed YYYY-MM-DD.
H2-5 · Sensing & telemetry · current + temperature + airflow

Sensing & telemetry evidence chain: current, temperature, airflow, and fault memory

This chapter turns common field complaints (weak heating, power hunting, thermal trips, intermittent stops) into a repeatable evidence chain. The evidence set is intentionally limited to signals that can be correlated in time: I_primary, temperature slope (NTC), fan tach, rail droop, and last-trip reason.

Rule: symptoms are not root causes. Root causes require at least two correlated evidence points (example: I_primary dropout aligned with fault counter increment, or NTC slope jump aligned with tach loss).

Current evidence (primary-current first)

Primary current sense (preferred)

What it answers: energy delivery behavior (burst, limiting, dropout).

Use it to separate: control-limited power vs protection cut vs brownout resets.
Look for: start→sustain continuity, periodic dropouts, envelope “breathing”.

Sense methods (shunt / CT / Hall)

What matters: not the part name, but the evidence quality.

Shunt: direct, good for correlation with enable edges.
CT/Hall: easier isolation but can hide low-frequency envelope details if conditioning is limited.

Bandwidth (defined by discrimination)

Requirement: enough to capture the enable-edge transient and the burst cadence.

Need transient detail: distinguish inrush spike vs steady limiting.
Need envelope detail: distinguish burst control vs unintended dropouts.

Temperature evidence (multi-point NTC as a consistency check)

Magnetron-area NTC

Role: closest proxy of load-coupled heating.

Proof patterns: delayed trip after sustained load; slope accelerates when airflow is insufficient.

Duct / cavity NTC

Role: airflow effectiveness and blockage sensitivity.

Proof patterns: tach normal but duct slope steep → airflow restriction; tach loss → slope jump + rapid trip.

Power-device NTC

Role: switching-loss and heatsink coupling evidence.

Proof patterns: slope increases only at higher power windows; drift shows as systematic offset under identical load.

Airflow evidence (tach integrity vs airflow effectiveness)

Tach signal integrity

Role: confirm fan rotation and detect stalls/dropouts.

Proof patterns: tach missing/unstable aligned to thermal events; repeated “fan fail” flags if available.

Airflow restriction fingerprint

Role: detect blockage even when tach looks normal.

Proof patterns: duct/cavity NTC slope rises faster than historical baseline; trips occur later but predictably.

Discriminator rule

Goal: distinguish “sensor chain” from “real overheating”.

Tach lost + slope jump: real airflow event.
Tach OK + impossible temperature steps: sensor/contact/ADC chain issue.

Telemetry strategy (make H2-9 diagnosable)

Fault counters + timestamps

Minimum set: UVLO/BOR, OCP/OVP, OTP, interlock events.

Value: counters convert intermittent complaints into measurable recurrence patterns.

Last-trip reason (single source of truth)

Store: most recent protection cause + time index.

Value: prevents mis-attribution when multiple protections exist (example: OTP after UVLO oscillation).

Ring buffer (recent N events)

Record per event: enable edge, I_peak, VDD_min, NTC_max, tach_valid.

Value: enables evidence correlation without lab equipment in field returns.

Evidence matrix (symptom × evidence)

Symptom I_primary Temperature (NTC slope) Fan tach Rail droop (VDD) Interlock / logs
Weak heating Start→sustain transition abnormal; average OK but envelope unstable. Slope lower than expected under commanded power (if power is truly reduced). Usually normal; use as “not airflow” baseline. Typically stable (unless dropouts align to VDD). Check last-trip: repeated OCP/limit events imply control/protection limiting.
Power hunting Breathing envelope, periodic dropouts, burst cadence shifts. Slope oscillates or plateaus matching cadence. May be stable; tach loss implies a different root cause. If VDD droops align to hunting, suspect LV margin or injection. Fault counters increment in sync; “last-trip reason” reveals dominant protection.
Thermal trip May remain normal until trip; sudden cut aligns to protection. NTC slope steepens; compare magnetron vs duct to locate bottleneck. Loss/stall aligns to slope jump; normal tach but steep slope implies restriction. Usually stable; VDD anomalies suggest secondary symptom (reset). OTP counter increments; store trip timestamp to correlate with tach and slope.
Stops at start Inrush spike then cutoff; no sustained region. Little temperature rise (too short); ignore absolute T. May not spin up yet; not primary evidence. VDD droop at enable edge is decisive for brownout path. UVLO/BOR counters and reset flags distinguish true undervoltage vs injection.
Figure F5. Evidence chain map (I, T, tach, VDD, logs) Block diagram showing where current, temperature, airflow, rail droop, and interlock evidence is observed, plus a compact matrix mapping symptoms to evidence. Evidence Chain Map — Current + Temperature + Airflow + Logs The same 5 evidence points can explain weak heating, hunting, thermal trips, and start-stop events. System context (evidence taps) AC / EMI HV inverter HV network Magnetron Control + LV PSU VDD / logs I_primary VDD NTC-MG NTC-duct NTC-PWR fault log fan tach interlock Compact symptom × evidence matrix (use as first checklist) Symptom I_primary NTC slope tach VDD logs weak hunt thermal start-stop ICNavigator
Cite this figure Figure ID: F5 · ICNavigator
Figure F5. Evidence-chain map plus a compact symptom-evidence checklist. The design goal is time correlation, not maximum sensor count.
Suggested citation (copy/paste): ICNavigator — Figure F5 (Microwave Evidence Chain Map + Matrix), accessed YYYY-MM-DD.
H2-6 · Low-voltage PSU & reset immunity · reboot / trip

Low-voltage PSU & reset immunity: why start-up causes reboots and trips

One of the most common field failures is “stops or reboots right at start”. This chapter isolates that class of issues using only two waveforms and one correlation rule: MCU VDD droop and I_primary at inverter enable. The goal is to separate true undervoltage from EMI/ground-bounce injection and avoid false root causes.

Core concept: many “HV-stage suspects” never get a chance to operate. A brownout reset can disable the inverter before sustained power delivery exists. Always prove whether VDD crossed BOR/UVLO first.

Start-up reset path (field-realistic chain)

Path A — true undervoltage

Mechanism: inrush / relay step → LV rail droop → BOR/UVLO.

Proof: VDD crosses BOR/UVLO threshold for a measurable duration; brownout/reset counters increase.

Path B — injection / ground bounce

Mechanism: switching noise couples into reset/IO even if average VDD looks OK.

Proof: resets align to enable/relay edges without a clear VDD threshold crossing; reset flags lack BOR signature.

Path C — UVLO mis-trigger

Mechanism: threshold too tight, insufficient hysteresis/debounce.

Proof: borderline events occur at specific mains/load combinations; repeated start attempts show the same timing.

Two mandatory measurements (keep diagnosis vertical)

Measure 1 — MCU VDD waveform

How: trigger on inverter enable or relay edge; capture VDD minimum and droop width.

Decision: crossing BOR/UVLO → undervoltage path; no crossing → injection/logic path.

Measure 2 — I_primary at start

How: observe inrush spike and whether a sustained region exists.

Decision: spike + immediate cutoff suggests protection/brownout; sustained region supports deeper HV-stage analysis.

Aux evidence — reset flags / counters

Use if available: BOR reason, watchdog reason, last-trip record.

Decision: flags convert ambiguous “reboot” into a definite cause class.

3-step fast discriminator (droop → alignment → cause)

  • Step 1 — capture VDD droop: confirm whether VDD crosses BOR/UVLO (and for how long).
  • Step 2 — align to enable edge: determine if droop/reset aligns with inverter enable / relay switching.
  • Step 3 — split injection vs true undervoltage: BOR signature/counters imply true undervoltage; absence implies injection/RESET/WD path.
Figure F6. Start-up reset discriminator (enable vs VDD vs I_primary) Waveform-style diagram showing HV enable edge, VDD droop relative to BOR/UVLO threshold, and primary current behavior, paired with a 3-step decision block. Start-up Reboot / Trip — Time-Aligned Evidence Trigger on enable edge. Then inspect VDD threshold crossing and I_primary sustain region. Waveforms (not to scale) t0 time → HV enable enable edge (trigger) MCU VDD BOR/UVLO threshold VDD min I_primary inrush spike sustain region? 3-step discriminator Step 1 VDD crosses BOR? width + minimum Step 2 Align to enable relay edge? Step 3 BOR signature? true UVLO vs injection use reset flags ICNavigator
Cite this figure Figure ID: F6 · ICNavigator
Figure F6. Start-up discriminator based on time correlation. The same symptom (“reboot at start”) can be true undervoltage or injected resets; the VDD threshold crossing is decisive.
Suggested citation (copy/paste): ICNavigator — Figure F6 (Microwave Start-up Evidence: enable/VDD/I_primary), accessed YYYY-MM-DD.
H2-7 · Safety & interlocks · door chain + hard cutoffs

Safety interlocks: door switch chain, hard cutoffs, and evidence-based isolation

This chapter focuses on the hardware door-interlock chain and hard cutoffs only. The goal is fast isolation of “won’t start”, “door error”, and intermittent stop events using switch-state evidence, time signatures (bounce), and the cutoff actuator evidence (relay/SSR coil drive and HV enable).

Non-negotiable: diagnosis must rely on observable low-voltage evidence (switch states, relay coil voltage, logs). No high-voltage probing is required to close the evidence loop.

Door chain roles (generic naming, evidence-centric)

Primary latch switch

Role: main “door closed” permit for heating.

Evidence: stable closed state before HV enable. Any dropout aligned to vibration is suspect.

Secondary interlock switch

Role: redundancy; must be consistent with primary.

Evidence: disagreement with primary is a first-order fault signature (misalignment or contact issue).

Monitor switch

Role: detects invalid combinations; triggers fault/cutoff path.

Evidence: “impossible” state combination aligns to hard cutoff and last-trip record.

Failure modes (proof fingerprints)

Contact bounce / chatter

Fingerprint: multiple toggles in a short time window.

Proof: GPIO interrupt bursts; event timestamps align to door vibration or relay actuation edges.

Misalignment (mechanical)

Fingerprint: one switch never reaches stable “closed” even when door appears shut.

Proof: repeatable bad static combination across attempts; minimal randomness.

Stuck / welded contacts

Fingerprint: state does not follow door motion.

Proof: door open yet still “closed”; monitor path is triggered when combinations become impossible.

Intermittent harness / connector

Fingerprint: random toggles during operation, often vibration/temperature correlated.

Proof: timestamps cluster at specific phases (fan spin-up, heat expansion); counters increase without a consistent static pattern.

Hard cutoffs (what actually removes heating permission)

Cutoff actuator

Mechanism: relay/SSR removes HV enable or its upstream supply.

Proof: relay coil drive edge + HV enable drop are time-aligned with a door chain event.

Fault latch path

Mechanism: monitor-triggered invalid state → latched fault / lockout.

Proof: last-trip reason shows interlock/monitor; repeats until a reset condition is met.

Minimum log fields

Record: switch snapshot, bounce counter, cutoff reason.

Proof: “snapshot + timestamp” allows field returns to be categorized without ambiguity.

Door-only decision tree (won’t start → isolate cause class)

State / symptom First check Discriminator evidence First fix direction
Won’t start
door error		 Read primary + secondary static states. If inconsistent → misalignment/contact/harness class.
If consistent → check monitor + cutoff record. 		Inconsistent: inspect alignment / switch health / connector seating.
Consistent: check monitor-trigger and cutoff actuator chain.
Starts then stops
intermittent		 Enable timestamped logging of switch toggles. Bounce bursts in short windows → contact chatter.
Random toggles with vibration/heat phase clustering → harness intermittent. 		Chatter: debounce/time filtering + mechanical damping.
Harness: strain relief, connector retention, routing away from vibration hot spots.
Door open/close mismatch
stuck		 Compare switch state vs door motion. State does not change with door motion → stuck/welded contact or broken actuator. Replace switch/actuator; verify monitor logic does not mask a stuck fault.
Monitor-trigger lockout
latched		 Check last-trip reason + monitor state. Invalid combination recorded; relay/SSR cutoff edge aligns to monitor trigger. Fix mechanical alignment first; then clear latch conditions; verify repeatability.
Figure F7. Door interlock chain and hard cutoff evidence Diagram showing three door switches feeding GPIO sampling and fault logic, then controlling relay/SSR cutoff and HV enable. Includes bounce counter and last-trip record blocks. Door Interlocks — Switch Chain + Hard Cutoff Evidence Use low-voltage state, bounce time signatures, and cutoff actuator evidence. Door / latch Latch motion Vibration / misalign Connector stress Door switches Primary latch switch Secondary interlock Monitor switch Sampling + fault memory GPIO snapshot + debounce state at enable edge Bounce counter interrupt bursts Last-trip reason monitor/interlock Hard cutoff path (observable evidence) Cutoff logic invalid combination Relay / SSR coil drive evidence HV enable permit removed Inverter stage blocked TP: coil V TP: HV enable log: last-trip ICNavigator
Cite this figure Figure ID: F7 · ICNavigator
Figure F7. Door interlock chain with three-switch roles, sampling/debounce evidence, and the hard cutoff path (relay/SSR → HV enable).
Suggested citation (copy/paste): ICNavigator — Figure F7 (Microwave Door Interlock Chain + Hard Cutoff), accessed YYYY-MM-DD.
H2-8 · EMC / surge / ESD · rugged power around inverter

EMC robustness around the inverter: entry filtering, return paths, and executable checks

The inverter stage combines high dv/dt switching edges and pulsed currents, making it a prime source of conducted and radiated interference. This chapter is written as an executable checklist: map symptoms to suspects, pick the first measurement, and apply the first fix direction. Validation focuses on reset counters under EFT/surge and UI disturbance/self-recovery under ESD.

Key rule: EMC is diagnosed by time alignment. If UI glitches or resets align to HV enable edges or power windows, the noise path is inside the inverter coupling network (return paths, loops, partitions), not “random UI firmware”.

Entry filtering and chassis bonding (mains-side)

CM choke + X/Y capacitors

Purpose: limit conducted CM/DM noise and stabilize return paths.

Field clue: touch/display anomalies scale with heating power; reset counters rise during EFT/surge stress.

Bleeder / discharge path

Purpose: prevent residual charge and repeated start anomalies.

Field clue: failures depend on time between power cycles; “second start” behaves differently than “cold start”.

Chassis bonding control

Purpose: provide predictable high-frequency return and reduce floating nodes.

Field clue: ESD causes UI disturbance; outcome splits into self-recovery vs requires power cycle.

High-frequency return paths (inverter-side coupling)

Power loop area (di/dt loop)

Risk: loop area turns switching current into broad EMI injection.

First measurement: VDD transient or reset flags aligned to enable edges.

Gate-drive loop and reference

Risk: noisy drive return couples into logic and sensing references.

First measurement: I_primary spike/ringing alignment to UI glitch windows.

Sensing ground partition (ADC integrity)

Risk: ADC/NTC/current sense corruption looks like “random control”.

First measurement: sensor jumps aligned to switching windows; compare to tach/VDD for consistency.

Symptom → suspect → first measurement → first fix (action table)

Phenomenon First suspect First measurement First fix direction
Touch glitches / false triggers HF return path coupling into touch reference; chassis bonding ambiguity. Time-align glitch to HV enable / heating window; check VDD transients and reset flags. Improve return path control near inverter; reinforce touch reference integrity; tighten bonding consistency.
Display flicker / UI freeze Conducted noise on LV rails; ground partition weakness near inverter. Log reset counters; measure VDD droop/impulses at enable edge. Strengthen LV decoupling and rail impedance; isolate noisy returns from UI/MCU domain.
Random resets during heating True brownout vs injected reset/WD path; inrush/relay edge coupling. BOR/UVLO signature + VDD waveform; align with I_primary envelope events. Increase LV margin/hysteresis; reduce enable-edge injection; separate relay/drive returns from MCU reset path.
Buzzer anomalies Noise coupling into low-current actuators and audio drive references. Align anomaly with switching edges; verify actuator rail stability. Improve local return path and decoupling; reduce shared impedance with inverter returns.
EFT/surge sensitivity Entry filter capacity and bonding; UVLO threshold too tight. Stress event → reset counter increments + last-trip reason; check VDD crossing. Rebalance entry filter and discharge paths; add margin and debounce on UVLO/BOR reporting.
ESD causes UI confusion ESD return path and interface robustness; latch-up-like behavior. Observe self-recovery vs needs power cycle; log UI error flags if available. Improve ESD return routing; reduce floating nodes; ensure deterministic reset and recovery behavior.

Validation mindset (two buckets only)

EFT / surge

Metric: reset counters + last-trip reason under stress events.

Pass intent: no unexpected resets; if a trip occurs, it is correctly classified and logged.

ESD

Metric: UI disturbance and self-recovery behavior.

Pass intent: deterministic recovery; no persistent UI corruption without a logged reason.

Time correlation

Rule: symptoms must be mapped to enable edges or power windows.

Outcome: eliminates “random glitch” narratives and forces a physical coupling hypothesis.

Figure F8. EMC coupling map and verification hooks Block diagram showing mains entry filter and chassis bonding, inverter switching and return loops, coupling arrows into UI/MCU/touch/display domain, and two verification blocks: EFT/surge reset counters and ESD UI recovery. EMC Map — Entry Filter + Return Paths + UI Coupling Translate symptoms into a coupling hypothesis, then verify with counters and recovery behavior. Mains entry CM choke + X/Y Bleeder discharge Bonding chassis return Inverter region Switching node high dv/dt Power loop di/dt area Gate loop drive return UI / MCU domain MCU + VDD Touch glitch Display flicker coupling Verification hooks (two buckets) EFT / surge reset counters + last-trip TP: VDD transient log: BOR/WD ESD UI disturbance + self-recovery touch glitch recover? ICNavigator
Cite this figure Figure ID: F8 · ICNavigator
Figure F8. EMC coupling map with two verification buckets: EFT/surge (reset counters + last-trip) and ESD (UI disturbance + self-recovery).
Suggested citation (copy/paste): ICNavigator — Figure F8 (Microwave EMC Coupling Map + Verification Hooks), accessed YYYY-MM-DD.
H2-9 · Field debug playbook · SOP: symptom → evidence → isolate → fix

Field debug SOP: fastest path from symptoms to proof, isolation, and first fixes

This SOP is built for field triage: start with the two fastest measurements, use one discriminator to avoid misclassification, keep root causes to a maximum of three, and apply the first fix direction that can be verified by returning to evidence.

Operating rule: every conclusion must be anchored to a timestamped evidence item (waveform edge alignment, counter increment, or state snapshot). “Random” is not a diagnosis category.

Evidence pool (keep it low-voltage, time-aligned)

VDD (MCU supply)

Use: prove brownout vs injected reset/WD.

TP: VDDBOR/WD flags

I_primary (inverter primary current)

Use: separate weak heating vs control-limited burst vs protection cycling.

envelopeburst cadence

Temperature (NTCs)

Use: distinguish real overheat vs sensing chain drift/stiction.

dT/dtsensor consistency

Fan tach / airflow proxy

Use: detect tach loss, stall, or airflow restriction signatures.

tach dropphase correlation

Door interlock states

Use: isolate misalignment vs bounce vs harness intermittent.

state snapshotbounce counter

Counters & last-trip reason

Use: classify resets, trips, and lockouts consistently.

timestampreason code

High-frequency symptoms (expand each SOP card)

1) Reboots / trips at start (enable edge) VDD · I_primary

First 2 measurements

(1) Capture MCU VDD with trigger aligned to inverter enable edge.
(2) Capture I_primary envelope around the same edge.

Discriminator

VDD crosses BOR/UVLO threshold exactly at enable edge → true brownout.
VDD stays above threshold but reset happens → injected reset/WD/EMI path.

Likely root causes (≤3)

LV rail impedance / inrush event too aggressive · relay edge ground bounce · EMI injection into reset/watchdog path.

First fix

Increase LV margin (decoupling/impedance) · align enable sequencing to avoid worst-case inrush · harden reset path and return routing.

Return-to-proof: after changes, verify BOR/WD counters stay stable and VDD minimum no longer coincides with enable edge.
2) Heating is weak but UI looks normal I_primary · NTC

First 2 measurements

(1) Measure I_primary envelope across a full power window.
(2) Track magnetron-area NTC slope (dT/dt) during the same window.

Discriminator

I_primary low and steady + dT/dt low → power not delivered.
I_primary shows periodic cut/restore → protection/limit cycling or control burst gating.

Likely root causes (≤3)

Power-stage limiting/protection cycling · sensing chain under-reads/over-reads causing conservative control · airflow restriction causing early derate.

First fix

Confirm current/temperature telemetry integrity · check airflow restriction indicators · adjust limit thresholds/hysteresis only after evidence confirms a false trip.

Return-to-proof: I_primary envelope becomes continuous at target power and dT/dt matches expected trend without derate toggling.
3) Power oscillates (strong/weak cycling) I_primary · counters

First 2 measurements

(1) Capture I_primary for several cycles to see cadence.
(2) Read last-trip reason / counters (OCP/OTP/UVLO if available) with timestamps.

Discriminator

Cadence matches trip counters increment → protection cycling.
No counters but cadence stable → control burst modulation or telemetry-driven limiting.

Likely root causes (≤3)

Borderline protection threshold · noisy telemetry causing false limit · thermal coupling causes periodic derate.

First fix

Improve measurement integrity (filtering/reference) · add hysteresis/time qualification to trips · validate thermal slope vs cadence.

Return-to-proof: cadence disappears or is explained by intentional burst schedule without trip reason increments.
4) Overheat shutdown after 30–90 seconds NTC · fan tach

First 2 measurements

(1) Log multiple NTCs and compute dT/dt (magnetron / duct / power device).
(2) Capture fan tach continuity and speed trend.

Discriminator

Tach stable but dT/dt steep → airflow restriction/thermal path issue.
Tach drops/glitches before OTP → fan/tach chain fault.

Likely root causes (≤3)

Blocked duct / rising flow resistance · NTC contact or location bias · tach signal integrity or fan driver dropouts.

First fix

Remove airflow restrictions and verify dT/dt improvement · validate NTC consistency across sensors · harden tach capture (pullups/filtering) if glitches appear.

Return-to-proof: dT/dt normalizes and OTP counters stop increasing under the same load profile.
5) Door error / intermittent no-start with door closed interlocks · bounce

First 2 measurements

(1) Record primary + secondary static states at start attempt.
(2) Enable bounce counter or interrupt timestamp log during door motion and start edge.

Discriminator

Inconsistent static combination → misalignment/switch failure.
Consistent static but bursty toggles → contact chatter or harness intermittent.

Likely root causes (≤3)

Mechanical misalignment · contact bounce/chatter · intermittent harness/connector.

First fix

Restore alignment and stable actuation first · add time qualification (debounce) after evidence confirms chatter · improve harness retention and strain relief if phase-correlated toggles exist.

Return-to-proof: stable states persist through the enable window; bounce bursts disappear from logs.
6) Touch/key glitches aligned to start or power changes time align · reset flags

First 2 measurements

(1) Time-align glitch events to HV enable and power windows.
(2) Check VDD transient and reset flags/counters around the same moments.

Discriminator

Strict alignment to enable/power window → inverter coupling path.
No alignment + stable VDD → UI domain integrity issue outside inverter coupling.

Likely root causes (≤3)

Return path coupling into UI reference · conducted noise on LV rails · ESD-induced UI corruption without deterministic recovery.

First fix

Improve return path control and partition integrity · strengthen LV decoupling near UI/MCU · ensure deterministic recovery behavior and reason logging.

Return-to-proof: UI events no longer align to enable edges; reset counters remain unchanged under the same power profile.
7) Fan runs but temperature rises too fast dT/dt · tach

First 2 measurements

(1) Compare dT/dt across duct NTC vs magnetron-area NTC.
(2) Verify tach speed trend (not only presence).

Discriminator

Tach speed normal but duct NTC heats rapidly → airflow path restriction.
Tach speed low/unstable → fan drive or mechanical load issue.

Likely root causes (≤3)

Rising flow resistance (dust/duct) · fan speed degradation under load · NTC mounting/contact bias.

First fix

Clear airflow path and re-verify duct dT/dt · ensure fan speed margin under worst-case load · correct NTC contact and placement if inconsistent.

Return-to-proof: duct dT/dt decreases at the same power; tach speed stability improves if it was a cause.
8) Relay sounds abnormal / intermittent pulling coil V · VDD

First 2 measurements

(1) Measure relay coil voltage during pull-in and hold phases.
(2) Capture VDD and reset flags to see shared impedance events.

Discriminator

Coil voltage dips at the same time as chatter → drive supply/return issue.
Coil voltage stable but chatter persists → mechanical/relay wear or control qualification logic.

Likely root causes (≤3)

Shared impedance and ground bounce · coil driver clamp/backfeed interaction · mechanical relay degradation.

First fix

Stabilize coil drive path and return · add time qualification to control edge if needed · replace relay only after evidence rules out drive collapse.

Return-to-proof: coil V remains above pull-in/hold thresholds with no chatter under the same enable sequence.
9) Works in one outlet but fails in another (grid sensitivity) counters · VDD

First 2 measurements

(1) Compare reset/trip counters and last-trip reason across environments.
(2) Capture VDD minimum at enable edge under both conditions.

Discriminator

Counter signature changes (surge/EFT-like) → entry/robustness margin issue.
Only VDD min shifts → LV supply margin vs inrush timing sensitivity.

Likely root causes (≤3)

Entry filtering/bonding sensitivity · UVLO/BOR margins tight · enable sequencing triggers worst-case inrush under certain mains impedance.

First fix

Increase immunity margin using evidence (counters + VDD min) · make enable timing less sensitive to mains impedance · ensure deterministic logging for each failure class.

Return-to-proof: environment change no longer produces counter spikes or VDD threshold crossings under identical start profiles.
Figure F9. Field debug SOP map (symptom → evidence → isolate → fix) Diagram showing common microwave symptoms, mapping to a small evidence pool, passing through a discriminator decision gate, and ending in first-fix buckets. Includes time alignment axis for enable edge and power window. Field Debug SOP — Symptom → Evidence → Isolate → Fix Two fast probes, one discriminator, then first fix buckets with return-to-proof. Symptoms (pick one) Start reboot / trip Weak heating (UI normal) Power oscillation / cycling OTP after 30–90 s Door error / no-start UI glitch at power window Fan runs, dT/dt too steep Relay chatter / abnormal sound Evidence pool VDD BOR/WD flags I_primary envelope NTC dT/dt tach fan speed interlock bounce counters last-trip Discriminator One proof that splits threshold cross? counter increments? phase alignment? First fix buckets LV margin / sequencing telemetry integrity airflow / thermal path interlock / harness Time alignment enable edge power window ICNavigator
Cite this figure Figure ID: F9 · ICNavigator
Figure F9. Debug SOP map: pick symptom → use a small evidence pool → apply one discriminator → execute first fix and return-to-proof.
Suggested citation (copy/paste): ICNavigator — Figure F9 (Microwave Field Debug SOP Map), accessed YYYY-MM-DD.
H2-10 · IC selection (MPN 방향) · replaceable families per block

IC selection: replaceable families by functional block (conversion-oriented, not a part-number dump)

Selection is organized by functional blocks to preserve replaceability. Each block follows the same 4-line format: Selection goals → Must-have protections → Typical specs → Example MPN families. Part numbers are intentionally not expanded here.

Rule: choose families that protect the evidence chain (stable VDD classification, clean sensing references, deterministic cutoffs, and robust I/O recovery).

Replaceable families per block (standardized 4-line cards)

Gate driver (half-/full-bridge)

Selection goals: stable switching under high dv/dt; predictable enable/disable edges.

Must-have protections: UVLO, strong dv/dt immunity, controlled Miller behavior.

Typical specs: drive current class, propagation symmetry, CMTI/immune behavior.

Example families: high-side/low-side driver families; isolated gate-driver families (rugged variants).

Current sense (primary / telemetry)

Selection goals: preserve I_primary envelope and trip signatures with minimal corruption.

Must-have protections: input protection, robust common-mode behavior, stable reference path.

Typical specs: bandwidth class, gain/offset stability, input CM range and transient immunity.

Example families: shunt amplifiers; isolated current-sense amplifiers; Hall-interface front-end families.

MCU / housekeeping

Selection goals: deterministic reset classification and reliable logging under disturbance.

Must-have protections: BOR/UVLO flags, watchdog, event counters/timestamps, safe fault record.

Typical specs: BOR threshold options, robust GPIO sampling, low-noise ADC references.

Example families: appliance-grade MCUs with strong BOR/WD + fault log support.

Offline AC-DC (LV PSU)

Selection goals: avoid VDD droop at enable edges; stable standby behavior.

Must-have protections: soft-start, predictable UVLO, robust transient response.

Typical specs: start/hold behavior, dynamic response class, protection mode determinism.

Example families: offline flyback controller families; secondary regulation families; standby-optimized variants.

Relay / SSR driver

Selection goals: stable coil drive without backfeed disturbance into MCU domain.

Must-have protections: clamp strategy, reverse/backfeed protection, deterministic off-state.

Typical specs: coil current class, voltage headroom, switching edge control.

Example families: low-side coil drivers; protected high-side switch families; SSR driver families.

Touch / display interface protection

Selection goals: UI stable during power windows; ESD events self-recover deterministically.

Must-have protections: low-cap ESD arrays, controlled return, CM filtering where needed.

Typical specs: ESD level family, capacitance class, leakage and recovery behavior.

Example families: low-cap ESD protection arrays; common-mode choke families; interface filter families.

Selection logic ladder (baseline → rugged → high-margin)

Baseline

Meets functional requirements.

Use only when counters and evidence chain remain stable across enable edges.

Rugged

Improved immunity and protection.

Preferred for dv/dt coupling environments and field variability.

High-margin

Strongest immunity / determinism.

Use when resets or UI issues correlate to power windows despite baseline fixes.

Figure F10. IC selection map by block (families, not part-number dump) Block map for replaceable IC selection families in microwave oven control: gate driver, current sensing, MCU housekeeping, low-voltage AC-DC, relay/SSR drive, and UI interface protection, with must-have protection tags. IC Selection Map — Replaceable Families per Block Choose families that protect the evidence chain (VDD classification, clean sensing, deterministic cutoffs, UI recovery). Gate driver dv/dt immunity · UVLO Current sense CM robustness · bandwidth MCU housekeeping BOR/WD · counters/log Offline AC-DC (LV) UVLO behavior · transient margin Relay / SSR driver clamp/backfeed · deterministic off Touch / display I/O ESD array · CM filter Must-have protections (tags) UVLO / BOR dv/dt immunity ESD Counters / last-trip Deterministic cutoff behavior ICNavigator
Cite this figure Figure ID: F10 · ICNavigator
Figure F10. Functional-block IC selection map with must-have protection tags to preserve the evidence chain and field robustness.
Suggested citation (copy/paste): ICNavigator — Figure F10 (Microwave IC Selection Map by Block), accessed YYYY-MM-DD.

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H2-12 · FAQs ×12 · Answerable · Evidence-based · Scoped

FAQs: fastest evidence checks for common microwave failures

Each answer is constrained to this page’s evidence chain: drive / current / temperature / interlocks / LV PSU / EMC. For safety and speed, prioritize primary-side and low-voltage measurements (VDD, I_primary, NTCs, tach, interlock states, counters).

I_primary VDD droop NTC dT/dt fan tach interlock states reason codes surge/EFT/ESD
1) Heating is weaker: check current first or “high voltage” first? What are the two fastest test points? → H2-5/H2-9I_primary+NTC

Answer: Start with primary-side evidence. It separates “power not delivered” from “derate/trip cycling” without touching HV nodes.

First 2 measurements

(1) Capture I_primary envelope across a full power window.
(2) Log magnetron-area NTC dT/dt during the same window.

Discriminator

I_primary low & steady + dT/dt low → power not delivered.
I_primary periodic cut/restore → protection/limit cycling.

Go deeper

Use the SOP discriminator in H2-9; validate telemetry integrity in H2-5.

2) Reboots exactly at start: which two waveforms separate undervoltage from EMI-injected reset? → H2-6/H2-9VDD+flags

Answer: Time-align VDD and reset classification to the inverter enable edge. The timing relationship is the fastest truth source.

First 2 measurements

(1) Capture MCU VDD minimum with trigger at enable edge.
(2) Read BOR/WD/reset reason and counters (timestamped if possible).

Discriminator

VDD crosses BOR/UVLO + BOR increments → real undervoltage.
VDD stays above threshold but reset occurs → injection/WD/reset path coupling.

Go deeper

Fix sequencing and rail margin in H2-6, then verify via SOP in H2-9.

3) Stops only after running: how does the temperature curve separate airflow restriction from NTC drift? → H2-5/H2-8dT/dt+tach

Answer: Compare multi-point slopes (dT/dt), not just absolute temperature. Airflow issues reshape slope and sensor-to-sensor consistency.

First 2 measurements

(1) Log duct NTC and magnetron NTC and compute dT/dt.
(2) Capture fan tach trend (speed stability, not only presence).

Discriminator

Tach OK + both slopes steep (or duct slope leads) → airflow restriction/thermal path issue.
One NTC non-physical (stuck/jumps) → sensing drift/contact/harness.

Go deeper

Use the evidence matrix in H2-5; relate to disturbance coupling in H2-8.

4) Door closed but error persists: how can one state snapshot isolate misalignment vs switch failure vs harness intermittent? → H2-7/H2-9states+bounce

Answer: Use the 3-switch combination plus bounce timing. Static legality and dynamic chatter are different failure classes.

First 2 measurements

(1) Record primary/secondary/monitor states at start attempt (snapshot).
(2) Enable bounce counter or interrupt timestamps during door motion and enable edge.

Discriminator

Illegal static combination → misalignment or switch failure.
Static legal but bursts of toggles → contact chatter or harness intermittent.

Go deeper

Follow the door decision tree in H2-7 and the SOP card in H2-9.

5) Power goes up and down: how does I_primary separate unstable control from load abnormality? → H2-3/H2-5I_primary+counters

Answer: Look for cadence and whether it aligns to trip reasons. Protection cycling leaves a signature in counters and waveform gating.

First 2 measurements

(1) Capture I_primary cadence for several cycles (envelope + period).
(2) Read last-trip reason and counters (OCP/OTP/UVLO if available).

Discriminator

Cadence matches counter increments → protection cycling or limit toggling.
No counter changes but periodic modulation → control burst strategy or telemetry noise driving derate.

Go deeper

Map expected variants in H2-3 and validate sensing integrity in H2-5.

6) Touch glitches only during heating: return path or shielding first, and what evidence decides? → H2-8/H2-9time-align

Answer: Decide by time alignment to power windows. If glitches lock to enable edges, coupling/return integrity is the first suspect.

First 2 measurements

(1) Log glitch timestamps and align to enable edge / power window.
(2) Check VDD transient and reset flags/counters around the same moments.

Discriminator

Strict alignment to heating window → return/coupling path priority.
No alignment with stable VDD → UI domain integrity or ESD recovery issue.

Go deeper

Apply the “phenomenon → suspect → first probe → first fix” table in H2-8.

7) OTP triggers often but fan looks normal: what are the most common “temperature point distortion” sources? → H2-5/H2-8NTC consistency

Answer: “Fan OK” does not guarantee “temperature truth.” Distortion is usually sensor contact/placement, harness intermittency, or reference/ADC corruption during dv/dt events.

First 2 measurements

(1) Compare multiple NTCs for consistency vs power window.
(2) Verify tach speed trend and correlate with dT/dt.

Discriminator

One NTC non-physical (stuck/jumps) → contact/harness/ADC/reference issue.
All NTCs rise coherently → real thermal/airflow path problem.

Go deeper

Use the evidence matrix in H2-5 and coupling checklist in H2-8.

8) Relay occasionally sticks or pulls abnormally: how to verify driver issue vs contact wear using safe evidence? → H2-4/H2-7coil V

Answer: Use low-voltage coil-drive evidence. Coil voltage stability and timing explain most “abnormal pull” reports without unsafe probing.

First 2 measurements

(1) Measure relay coil voltage during pull-in and hold.
(2) Time-align coil voltage to enable edge, VDD min, and reset counters.

Discriminator

Coil V dips coincide with chatter → driver/supply/return issue.
Coil V stable but behavior persists → mechanical wear or contact pathology.

Go deeper

See stress points in H2-4 and hard cutoff logic in H2-7.

9) Trips immediately when plugged in: input inrush/filter issue or HV-side short? What two steps separate them? → H2-2/H2-6/H2-9timing

Answer: Use event timing: “at plug-in” vs “at enable.” Then confirm whether the low-voltage board ever reaches stable housekeeping.

First 2 measurements

(1) Record whether failure occurs before or only after inverter enable.
(2) Observe LV rail startup (VDD reaches steady state or collapses).

Discriminator

Fails before enable and LV never stabilizes → entry inrush/filter/line event sensitivity.
Fails only at enable → power-stage/load-side event; follow SOP isolation.

Go deeper

Use the system map in H2-2 and reset immunity checks in H2-6.

10) Fails more often in specific mains environments: what logging proves a surge/EFT trigger? → H2-8/H2-5reason+timestamp

Answer: Proof requires repeatable counters and timestamps. The goal is a signature: a specific reason code rate increases under a specific environment and aligns to input disturbance events.

First 2 measurements

(1) Log reset/trip reason code + timestamp (and increment counters).
(2) Correlate events to enable edge vs idle (separate conducted vs coupling paths).

Discriminator

Reason code frequency changes drastically with environment and clusters in time → disturbance-driven.
No signature and only random UI anomalies → likely local coupling/return path.

Go deeper

Apply the rugged EMC checklist in H2-8 and telemetry strategy in H2-5.

11) How to choose current-sense bandwidth and filtering without false trips or missed faults? → H2-5bandwidth

Answer: Bandwidth is defined by which fault classes must be separated in the waveform, and how much detection latency can be tolerated. Over-filtering erases fault signatures; under-filtering makes noise look like events.

First 2 measurements

(1) Identify which features are needed: envelope, burst edges, and trip precursor spikes in I_primary.
(2) Validate filter impact by comparing event timing vs counter/reason logging.

Discriminator

Filter delay causes “late” detection and wrong classification → too aggressive filtering.
Noise triggers without correlated thermal/enable evidence → bandwidth too wide / insufficient conditioning.

Go deeper

Use the evidence-chain design rules in H2-5 and lock a minimal discriminator set.

12) What minimal OVP/OCP/OTP/UVLO set most effectively reduces returns, and how to keep it diagnosable? → H2-4/H2-6reason codes

Answer: A protection set reduces returns only if it is deterministic and leaves evidence. Minimal coverage is: LV undervoltage (UVLO/BOR), overcurrent (OCP), overtemperature (OTP), and a controlled overvoltage boundary (OVP) where applicable—each mapped to a reason code and counter.

First 2 measurements

(1) Record last-trip reason + counter on every shutdown/lockout.
(2) Correlate reason to VDD min and I_primary envelope to prove conditions are real, not injected.

Discriminator

Trips without consistent evidence → false triggers (thresholds/noise/return).
Trips with consistent evidence → protection doing its job; then optimize margins and recovery behavior.

Go deeper

Use stress-point planning in H2-4 and reset immunity strategy in H2-6.

Figure F12. FAQ Evidence Compass (drive/current/temp/interlock/PSU/EMC) Diagram showing an evidence compass with six core evidence items and a time-alignment bar, indicating that each FAQ answer maps to low-voltage, primary-side, timestamped proof points. FAQ Evidence Compass Each FAQ answer maps to primary-side evidence + timestamps (no HV probing required). Evidence Chain drive · current · temp · interlock · PSU · EMC VDD droop BOR/WD flags I_primary envelope / cadence NTC dT/dt multi-point slope fan tach speed trend interlocks states / bounce counters last-trip reason Time alignment Always correlate evidence to enable edge and power window. enable edge power window ICNavigator
Cite this figure Figure ID: F12 · ICNavigator
Figure F12. Evidence compass for the 12 FAQs: all answers map to low-voltage, timestamped proof points (VDD, I_primary, NTC dT/dt, tach, interlocks, counters).
Suggested citation (copy/paste): ICNavigator — Figure F12 (Microwave FAQ Evidence Compass), accessed YYYY-MM-DD.
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