Induction Cooktop: Inverter Power, Pot ID, Touch/EMI Protections
← Back to: Smart Home & Appliances
Induction cooktop reliability comes from an evidence-first design loop: choose an inverter + sensing chain that stays stable under high dv/dt, then make pot-ID, UI coexistence, and OC/OV/OT protections depend on windowed measurements and clear discriminators. Most “mystery” faults (false pot detect, low-power squeal, nuisance trips, touch jitter, EMI fails) can be isolated with two probe points and fixed by a small set of knobs: sampling window/blanking, hysteresis, gate edge/snubber, and ground/rail isolation.
H2-1 · How to Split the Real Engineering Intent (Editorial Blueprint)
An induction cooktop page should not re-explain electromagnetic heating. The hard part is making high-power inverter switching, pot identification (pot ID), and touch/display UI coexist on one board while staying stable, verifiable, and mass-producible. This page is written as an engineering decision + evidence chain: every claim must tie back to measurable signals and repeatable operating conditions.
Four real engineering intents (each must map to measurable evidence):
-
Topology & device selection: Make explicit tradeoffs among power density, efficiency, thermal margin, and EMI
(MOSFET/IGBT, gate driver, snubber, current sensing).
Evidence anchors: switch-node overshoot/ringing, dv/dt, bus ripple, temperature ramp rate, nuisance-trip rate.
-
Pot ID / no-pot protection / low-power stability: Convert “cookware as a variable load” into observables
(amplitude/phase/impedance/Q trends), and keep decision logic robust under switching noise.
Evidence anchors: sampling-window placement, phase discriminator stability, decision repeatability during load steps, low-power ripple spectrum.
-
Touch/display coexistence under strong noise: Turn “false touch / UI flicker / resets” into coupling paths
(supply, ground return, E-field injection) and isolate them with minimal experiments.
Evidence anchors: UI-rail ripple, touch-raw baseline drift, correlation with switching events (time-aligned capture).
-
Protections & compliance: Balance fast protection (to prevent damage) with anti-nuisance design
(blanking/windowing), and make failures reproducible with a minimal fault snapshot.
Evidence anchors: OCP blanking boundary waveforms, bus spike origin, pre-trip snapshot (power level, phase metric, peaks, temperature).
Layout logic (aligned to search intent layers):
- First 2 chapters (H2-1/H2-2): establish a system map + key variables + test points so readers know what to probe.
- Middle chapters (later H2-3~H2-9): stay evidence-driven (waveforms, thresholds, discriminators, validation matrix).
- Tail (H2-10 + FAQs): capture long-tail queries with a repeatable debug format (low-power wobble, pot shift, false touch, trips, audible whine, EMI fails).
H2-2 · System Decomposition: 6 Blocks with Inputs/Outputs/Test Evidence
The purpose of decomposition is not a module list. It is a probe map: when a symptom happens, which two measurements come first, and what does each measurement prove. The six blocks below define the scope ownership of later chapters. Each block is described with the same three items: responsibility, must-measure points, and what it proves.
A) DC Link & Bus (DC link / bus voltage / inrush)
- Responsibility: energy buffering and a stable bus; controlled inrush; predictable behavior under dips/brownouts.
- Must measure: bus ripple, inrush current profile, bus recovery time under line dips/brownout tests.
- What it proves: whether resets/trips are power-boundary issues; whether OVP is triggered by bus spikes; whether power steps cause bus tailing.
Engineering note: bus issues often masquerade as “overcurrent” or “false pot ID.” Capture bus evidence first to avoid wrong root-cause.
B) Inverter Power Stage (half/full bridge + gate driver + snubber)
- Responsibility: translate the DC bus into controlled high-frequency energy; set the dv/dt “knob” against EMI and loss.
- Must measure: gate waveforms (amplitude/edge/dead-time), switch-node overshoot/ringing, temperature ramp vs power level.
- What it proves: whether nuisance trips come from spikes/ringing; whether EMI scales with dv/dt; whether low-power wobble ties to timing windows.
Engineering note: “it heats” is not enough. Switch-node overshoot and ringing usually define the ceiling for EMI, false detection, and false touch.
C) Resonant Tank & Coil Load (work coil + resonant tank + load change)
- Responsibility: present cookware loading as a controllable equivalent impedance; keep control stable under load changes.
- Must measure: coil-current amplitude trend, phase trend, frequency-scan response under controlled cookware/placement variations.
- What it proves: whether power wobble is real load movement vs sensing contamination; whether low-power instability is resonance detuning.
Engineering note: cookware shift is a dominant disturbance. Phase/impedance trends are typically more robust evidence than power feedback alone.
D) Pot Detection AFE (current/voltage/phase/impedance features)
- Responsibility: output decision-grade features (phase/impedance/Q trends) that remain valid under high dv/dt switching.
- Must measure: sampling-window placement, sensing noise floor, discriminator stability during load steps and low-power operation.
- What it proves: whether false “no-pot/pot-present” comes from algorithm weakness or sampling corruption; whether edge cookware cases are repeatable.
Engineering note: bind discriminators to a defined sampling window so ringing spikes cannot masquerade as real signals.
E) UI: Touch/Display/Backlight (capacitive touch + display driver)
- Responsibility: keep touch stable and display flicker-free under inverter noise; make false touch reproducible and diagnosable.
- Must measure: touch raw baseline (pre-filter), UI-rail ripple, correlation between touch noise and switching events (time-aligned capture).
- What it proves: whether false touch is driven by supply coupling, ground return, or E-field injection; whether backlight steps shift touch baselines.
Engineering note: capturing switching events and touch raw on the same timeline is often the fastest discriminator.
F) Protections / EMI / Fault Snapshot (OCP/OVP/OTP + emissions + logging)
- Responsibility: prevent damage with fast shutdown while avoiding nuisance triggers; turn failures into reproducible events.
- Must measure: pre/post-trip snapshots (peaks/integrals/temperature), fault codes/counters, EMI “knobs” with observable effects.
- What it proves: nuisance vs real over-limit; which minimal change (snubber/driver strength/layout/windowing) is the best first fix.
Engineering note: define a minimal fault snapshot: power level, phase metric, peak values over N cycles, and temperature at trigger time.
Key test-point map (so the reader can probe immediately):
- TP-BUS: DC bus voltage and ripple (power boundary, OVP origin).
- TP-SW: switch node (dv/dt, overshoot/ringing, EMI correlation).
- TP-GATE: gate waveform (dead-time, driver behavior, abnormal conduction evidence).
- TP-SENSE: current/voltage/phase sensing nodes (pot ID + OCP discriminator root).
- TP-UI: UI rail + touch raw (false touch / flicker / reset root).
H2-3 · Inverter Power: How to Choose Topology & Control (and What Fails When It’s Wrong)
In an induction cooktop, the inverter is not “just power.” It sets the ceiling for EMI margin, nuisance-trip rate, low-power stability, and pot-detection reliability. The right choice is best made by reversing from three inputs: power level, coil/tank parameters, and EMI/audible-noise targets. The result must be validated with three waveforms: bus, gate, and switch node.
Half-Bridge (Decision Focus)
- Value: fewer switches/drivers, simpler cost and layout loops.
- Typical risk: narrower control/measurement windows can make low-power operation more sensitive to noise spikes.
- Evidence to demand: clean switch-node ringing and a stable OCP discriminator under load steps.
Full-Bridge (Decision Focus)
- Value: more control headroom across load variation; can help stabilize certain operating zones.
- Typical risk: higher complexity increases the chance of loop inductance and timing mistakes that inflate EMI and nuisance trips.
- Evidence to demand: consistent dead-time across legs and controlled dv/dt without excessive snubber loss.
Three waveforms that should decide the design (not opinions)
- TP-BUS (DC bus): ripple and step response. Proves whether trips/resets are power-boundary issues and whether OVP is spike-driven.
- TP-GATE (gate): dead-time, edge quality, and bounce. Proves whether ZVS/ZCS windows are respected and whether cross-conduction risk exists.
- TP-SW (switch node): dv/dt, overshoot, ringing amplitude/frequency. Proves EMI risk, false sensing risk, and spike-driven nuisance OCP.
Symptom-driven hooks (make failures reproducible)
Symptom A: High power OK, low power wobbles / audible whine
- First 2 measurements: TP-SW (ringing + frequency zone) and TP-SENSE window noise (SNR at low power).
- Discriminator: does the phase/amplitude metric oscillate around a threshold (window edge) while the bus stays stable?
- First fix knobs: timing window placement, dead-time, driver strength / gate resistor, and resonance operating zone planning.
Symptom B: Trips immediately when cookware is placed
- First 2 measurements: TP-BUS (inrush/step sag) and TP-SW/TP-SENSE alignment (spike vs true current).
- Discriminator: does OCP correlate with switch-node ringing peaks rather than with a stable current increase?
- First fix knobs: soft-start slope, OCP blanking/windowing, snubber tuning, and loop-inductance reduction.
H2-4 · Resonant Tank & Coil: Quantify “Cookware as a Variable Load” into 3 Measurable Variables
Pot identification and stable power control become reliable only when cookware variation is expressed as measurable electrical variables. In practice, three variables are sufficient to structure robust discriminators without complex algorithms: Req (loss term), Leq (effective inductance / coupling), and Q (sharpness/sensitivity). These variables are not abstract theory; they are reflected in phase, amplitude, and frequency-scan evidence.
Req (Equivalent Loss / Damping)
- What it influences: energy transfer effectiveness and current peak for a given power command.
- What to observe: amplitude trends (coil current / tank voltage) under controlled steps.
- Typical failure signature: “same setting, different heating” across cookware; false overload if spikes dominate the amplitude metric.
Leq (Effective Inductance / Coupling)
- What it influences: resonance detuning and phase shift under cookware placement/material changes.
- What to observe: phase trend vs frequency and how it drifts during pot shift (misalignment).
- Typical failure signature: low-power wobble as the phase discriminator repeatedly crosses a threshold.
Q (Quality Factor / Sensitivity)
- What it influences: how sharp the response is—stable when well-managed, unstable when noise dominates.
- What to observe: scan-curve shape; sensitivity of phase and amplitude metrics to small disturbances.
- Typical failure signature: audible whine and control jitter amplified at low power.
Load-change “fingerprints” (in electrical terms)
- Pot shift / misalignment: rapid Leq drift → phase and amplitude jump together.
- Bottom area change: stronger Req impact → amplitude trend dominates.
- Material difference: Q and scan-curve shape change → phase-vs-frequency signature differs.
Minimal Viable Discriminator Set (MVDS) — mass-production friendly
A minimal discriminator set should be robust to switching noise and should not require heavy computation. The goal is repeatable decisions under controlled windows, not perfect classification.
MVDS-1: No-pot / Open-load Guard
- Evidence: phase/impedance trend consistency (avoid amplitude-only checks at low power).
- Windowing: sample inside a defined quiet window away from ringing peaks.
- Why it matters: prevents heating attempts on invalid loads and reduces false “pot present.”
MVDS-2: Pot-present Stable
- Evidence: phase metric stable + amplitude trend plausible (two-factor confirmation).
- Windowing: align metrics with consistent switching phase; keep thresholds away from noise edges.
- Why it matters: improves stability across cookware variation without complex modeling.
MVDS-3: Misalignment / Edge Cookware
- Evidence: scan-curve shape shift or phase drift rate beyond expected bounds.
- Windowing: detect trends over multiple cycles; avoid single-spike decisions.
- Why it matters: reduces power oscillation and nuisance trips during pot movement.
MVDS-4: Low-power Stability Guard
- Evidence: stability of metrics under low energy (SNR-aware thresholds).
- Windowing: use a low-power mode window/threshold set to avoid threshold “chatter.”
- Why it matters: fixes the most common user-visible defect: low-power wobble and audible whine.
H2-5 · Pot ID AFE: Designing the Sensing Chain (Without Being Fooled by Power Noise)
Pot identification is only as trustworthy as the analog front end and the sampling rules. In an induction cooktop, switch-node dv/dt and ringing can inject spikes into sensing paths and create false “pot present”, false overcurrent, or unstable low-power behavior. A production-grade Pot ID AFE is built by starting from the decisions it must make, then reverse-designing the signals, sensor type, windowing, and filters so that noise cannot masquerade as load change.
What to sample (signals that map to real load variation)
Coil current (Icoil)
- Used for: amplitude trend, power consistency checks, and rapid load-change detection.
- Noise risk: dv/dt spikes can appear as current peaks if the sense chain shares a noisy reference.
Tank/coil voltage (Vtank)
- Used for: resonance behavior, scan-curve shape, and detecting detuning/misalignment trends.
- Noise risk: ringing can inflate amplitude metrics if sampling lands on transient peaks.
Phase metric (V–I phase)
- Used for: robust discriminators for no-pot / present / detuned states.
- Noise risk: phase computed on contaminated windows can chatter around thresholds.
Power estimate (Pest)
- Used for: plausibility checks (two-factor confirmation) rather than precision metering.
- Noise risk: spike-driven Pest can hide true low-power instability if not windowed.
How to sense (shunt vs Hall vs Rogowski) — choose by bandwidth, isolation, and common-mode reality
Shunt + Amplifier
- Strength: linear, cost-effective, controllable bandwidth.
- Primary failure mode: common-mode/ground-bounce injection if Kelvin routing and reference are not enforced.
- Best when: the sense loop can be kept short, Kelvin-correct, and referenced to a clean domain.
Hall Current Sensor
- Strength: better isolation against common-mode stress and noisy returns.
- Primary failure mode: limited bandwidth/latency and offset drift can distort low-power decisions.
- Best when: robustness to layout variability is prioritized over maximum speed.
Rogowski / HF Pickup
- Strength: captures fast transients and spike signatures well.
- Primary failure mode: can over-emphasize switching spikes, causing false “events” unless windowed.
- Best when: used for transient evidence and protection support, not as a sole stable discriminator.
AFE placement & layout rules (non-negotiable)
- Kelvin first: sense points must not share high di/dt return paths.
- Common-mode awareness: the AFE input must survive dv/dt and ground bounce without saturating.
- Loop control: reduce loop inductance to prevent ringing from becoming “fake load change.”
Noise immunity: windowing, filtering tradeoffs, and “false evidence” prevention
- Sampling window: capture phase/amplitude inside a consistent quiet interval, away from dv/dt edges and ringing peaks.
- Blanking: ignore a short region around switching edges to avoid spike-driven false peaks.
- RC vs digital filtering: RC suppresses HF spikes but adds delay; digital filtering stabilizes trends but must not erase real pot-shift transients.
- Two-factor confirmation: combine phase stability + amplitude plausibility so one contaminated metric cannot decide alone.
Discriminators (with required counterexamples)
Each discriminator below is defined by a trend, not a single sample. For every decision, a counterexample is included to show what a dv/dt-contaminated sample can impersonate. The fastest way to prove contamination is to check correlation between TP-SW ringing peaks and the “decision spike” in the metric.
No-pot / Open-load Guard
- Expected trend: phase/impedance evidence stays in a stable no-load region across multiple cycles.
- Counterexample: sampling during ringing peaks can pull the phase metric and falsely indicate “pot present.”
- Prove it: the false transition aligns in time with TP-SW ringing maxima.
- First fix knob: move the sampling window + add edge blanking before adjusting thresholds.
Small/Edge Pot Detection
- Expected trend: weaker amplitude trend but phase remains stable within the pot-present region.
- Counterexample: dv/dt injection inflates amplitude briefly, impersonating a “normal large pot.”
- Prove it: amplitude spikes show strong cycle-to-cycle coincidence with switching edges.
- First fix knob: two-factor decision (phase + amplitude plausibility) + SNR-aware thresholds.
Misalignment / Pot Shift
- Expected trend: phase drift rate and scan-curve shape change over multiple cycles, not as single spikes.
- Counterexample: a single ringing burst can look like a “shift event” if the decision uses a one-shot peak detector.
- Prove it: the “event” disappears when averaging across a short windowed history.
- First fix knob: trend-based discriminator + multi-cycle confirmation.
Invalid / Non-magnetic Load
- Expected trend: scan/phase evidence never enters the stable pot-present region, even with controlled excitation.
- Counterexample: contaminated phase computed on noisy windows can momentarily cross the threshold.
- Prove it: crossing is not repeatable under fixed frequency/power when windowed correctly.
- First fix knob: enforce window consistency + hysteresis/hold time before declaring “present.”
H2-6 · Touch/Display Coexistence: Why Touch Jitters (and How Evidence Separates Light vs Power vs Ground)
An induction cooktop is a high-noise environment: the inverter produces strong dv/dt and large current loops, while capacitive touch measures high-impedance micro-signals. When touch “jumps,” the fastest path to a fix is to avoid guesswork and use an evidence chain that separates three coupling mechanisms: supply coupling, ground return mixing, and E-field injection.
Two-step evidence method (minimal tools, maximum discriminating power)
- Step 1 — Baseline: inverter OFF, display/backlight ON. Record touch raw counts and baseline noise floor under UI-only conditions.
- Step 2 — Controlled injection: inverter ON with fixed frequency/power. Compare touch raw deviation with TP-SW dv/dt events and UI rail ripple.
Symptom → Evidence → Isolation → Change (card-style, repeatable)
Case 1: Touch jitters only when inverter runs
- Evidence: touch raw spikes align with switching edges or ringing bursts (TP-SW correlation).
- Isolation: reduce edge rate (gate R / driver strength) or shift sampling timing; check if touch improves.
- Change: manage dv/dt and return paths; add shielding/guarding where E-field coupling dominates.
Case 2: Touch baseline drifts with backlight PWM
- Evidence: touch baseline tracks UI rail ripple and backlight PWM state even with inverter OFF.
- Isolation: freeze backlight PWM (fixed brightness) and compare touch noise floor.
- Change: separate UI rails, improve LDO/DC-DC PSRR in the relevant band, reduce shared impedance.
Case 3: Certain cookware/position causes more false touches
- Evidence: touch deviation changes with pot placement even when UI rails remain clean.
- Isolation: lock inverter to constant power, move cookware, and compare touch raw trends.
- Change: mitigate E-field injection (guard electrodes, routing, shielding, mechanical stack-up adjustments).
Case 4: Display flicker and touch errors occur together
- Evidence: UI rail ripple and reset counters rise during inverter load steps.
- Isolation: log brownout/UVLO events while capturing UI rail under step load.
- Change: tighten UI supply isolation, add hold-up/decoupling near UI rails, control power-step slew.
H2-7 · OC/OV/OT Protection: Balancing Nuisance Trips vs Missed Faults
Protection on an induction cooktop is not a threshold table. It is a set of decision layers that must protect silicon and the appliance while avoiding false trips caused by dv/dt, ringing, and normal load transients. A production-ready design defines: (1) what is measured, (2) when it is valid (windowing/blanking), (3) what action is taken (fast hardware cut vs software limiting), and (4) what is logged so field failures are reproducible.
OCP: switching spikes vs true overcurrent (windowing + blanking are mandatory)
What causes false OCP
- dv/dt injection: switching edges and ringing contaminate the current sense path and create fake peaks.
- normal transients: pot placement, resonance build-up, and controlled inrush can briefly raise current.
Decision layering (recommended)
- Level 1 — HW fast cut: cycle-by-cycle limiter for device survival (minimal blanking to avoid edge spikes).
- Level 2 — SW fast limit: ms-level confirmation using windowed metrics (avoid one-shot peak triggers).
- Level 3 — SW integral: 10–100ms energy/time accumulation for sustained overload and thermal risk.
OVP: where DC-bus spikes really come from (cause attribution beats threshold tuning)
Spike sources to separate
- Load step rebound: sudden coupling change (pot shift) returns energy to the bus.
- Resonant energy return: commutation and timing push energy back to DC link.
- Layout parasitics: loop inductance and recovery behavior create sharper overshoot.
Proof-first workflow
- Time align: bus peak vs switching phase and vs load-change evidence (phase/amplitude shift).
- Repeatability: reproduce with controlled pot motion or controlled power steps.
- Knob test: gate edge rate / snubber / loop layout changes should shift peak shape if parasitics dominate.
OTP: three temperature domains with different responsibilities
Coil / magnetic area temperature
- Purpose: long-term reliability of coil/magnetic stack-up (slow thermal dynamics).
- Best action: software integral limiting and derating rather than instant shutdown.
Power device temperature
- Purpose: prevent device thermal runaway during high loss or poor cooling.
- Best action: fast derating + shutdown for extreme events; avoid oscillatory “on/off” behavior.
Panel / surface temperature
- Purpose: user safety and surface limits (large thermal inertia but non-negotiable).
- Best action: staged derating and shutdown, validated against realistic cooking profiles.
Key engineering rule
- Domain boundaries: coil, power device, and panel sensors exist for different risks and must not share one threshold strategy.
- Thermal lag: confirm OTP with time/integral logic so sensor placement delays do not cause missed faults or nuisance trips.
What must be hardware-fast vs what can be software-confirmed
Must be hardware-fast
- Device survival events: extreme overcurrent, hard commutation failures, abnormal gate drive states.
- Bus absolute-limit risk: sharp DC-link overshoot that can exceed component ratings quickly.
Can be software-confirmed
- Sustained overload: multi-cycle confirmation + integral to reduce false trips.
- Thermal limits: time/integral derating and staged shutdown aligned to sensor dynamics.
- Load disturbances: pot shift/noise-related chatter handled via hysteresis and hold time.
Minimum Fault Record (MFR): the smallest log that makes field issues reproducible
- Fault type: OCP / OVP / OTP / UVLO / no-pot.
- Context: power level, operating mode (soft-start / heating / identification), frequency/phase region.
- Peaks in a short pre-fault window: I_peak, Vbus_peak, latest temperatures (coil/device/panel).
- Counters: occurrence count, last-occurrence time, retry attempt count and outcome.
- Decision flags: which discriminator triggered (windowed metric vs HW fast path).
H2-8 · EMC/EMI: Turn “Pass the Test” into an Executable Design Checklist
EMC success on an induction cooktop is driven by controllable physics: where switching energy is generated, how it returns (DM/CM paths), and which knobs trade dv/dt and ringing against efficiency. This chapter avoids certification workflow and focuses on a practical checklist with measurable observables.
Conducted EMI (DM/CM): the controllable points and what to observe
DM focus (ripple and return)
- Control: DC-bus ripple peaks, input filter loop closure, and return path impedance.
- Observe: Vbus ripple trend under power steps and the density of current spikes at input.
- Common failure: “good schematic, bad loop” — the filter exists but the loop area radiates and injects.
CM focus (parasitic capacitance paths)
- Control: SW-node-to-chassis/panel parasitic paths and single-point grounding strategy for shields.
- Observe: CM trend changes when shielding/ground reference is moved (dominant-path identification).
- Common failure: multiple ground bonds create unintended CM return loops.
Radiated EMI: the two radiators to treat first
Radiator 1 — Switch node (high dv/dt)
- Observe: dv/dt slope, overshoot amplitude, ringing duration and frequency.
- Control: edge rate (gate resistor/driver strength), snubber, and loop inductance reduction.
Radiator 2 — Coil current loop (high current)
- Observe: sensitivity to loop geometry changes and to return-path routing modifications.
- Control: minimize loop area and enforce a predictable return path; apply shielding with a clear grounding strategy.
Efficiency vs EMI knobs (each with its observable and side effect)
Gate resistor / driver strength
- Observable: dv/dt decreases; ringing amplitude and burst duration change.
- Side effect: higher switching loss and device temperature; may alter soft-switching margin.
- Safe iteration: tune edge rate before adding lossy snubbers.
Snubber (RC/RCD)
- Observable: overshoot reduction and shorter ringing tail.
- Side effect: direct power loss and thermal load; may reduce efficiency at high power.
- Safe iteration: apply after loop inductance and edge rate are under control.
Loop inductance reduction (layout knob)
- Observable: ringing frequency and peak shape shift dramatically; spike energy reduces.
- Side effect: usually positive; cost may appear as mechanical/assembly constraints.
- Safe iteration: always first — it changes the physics rather than masking it.
Shielding & grounding strategy
- Observable: CM trend changes; certain frequency bands reduce when the dominant path is cut.
- Side effect: bad grounding can worsen CM by creating new loops.
- Safe iteration: define a single intentional return point before adding more metal.
Top-3 actions (highest impact, in recommended order)
- Close and shrink high di/dt loops: minimize loop area and enforce a clean return.
- Tune the edge rate: gate resistor/driver strength to reduce dv/dt and ringing energy.
- Apply targeted damping: snubber for residual overshoot and ringing tail, validated against thermal cost.
Executable design checklist (use as a pre-test gate)
Conducted (DM/CM)
- TP-BUS: bus ripple stays controlled during power steps (no sharp rebound spikes).
- Input filter: capacitor-to-inductor-to-return loops are tight and unambiguous.
- Return path: avoid shared impedance between power return and sensitive domains.
- CM path: identify major parasitic capacitance (SW→chassis/panel) and cut/route intentionally.
- Knob test: edge-rate change must move an observable (dv/dt or ringing) if the right path is targeted.
Radiated
- TP-SW: overshoot and ringing tail are controlled; no long burst trains.
- Coil loop: loop area is minimized and stable; return path is predictable.
- Shielding: apply only with an intentional single-point grounding strategy.
- Near-field sanity: a simple probe should show clear improvement when loop/edge knobs are adjusted.
- UI coexistence: confirm touch/display stability after EMI tuning (avoid “fix EMI, break UI”).
H2-9 · Validation Test Plan: The Minimal Production-Ready Verification Matrix
A production validation plan must avoid “test everything” while still catching the failure combinations that cause field returns: pot variability, low-power instability, power-step stress, supply disturbances, thermal boundaries, and UI susceptibility. The most efficient approach is a matrix with (1) a Base Case, (2) each dimension’s Worst Case, and (3) a small set of Cross-Points (two worst dimensions combined).
Required measurement points and records (apply to every test row)
Minimal instrument set
- TP-BUS: Vbus ripple/peaks during steady state and steps.
- TP-SW: dv/dt and ringing tail shape (trend-based).
- TP-SENSE: windowed current/phase metrics used by control and protection.
- UI probe: touch raw baseline/noise and UI rail ripple (only when UI is in scope for that row).
Minimum record set (MFR-compatible)
- Context: power level, operating mode, frequency/phase region.
- Peaks: I_peak and Vbus_peak in a short pre-event window.
- Temperatures: coil / device / panel (latest sample + time/integral state if used).
- Counters: fault counts, retry counts, mis-detect counts, touch error counts.
- Trigger path: HW fast vs SW confirm/integral (for any protection event).
Minimal verification matrix (dimensions → representative points → metrics → records)
| Dimension | Representative points | Pass/Fail metrics | Required records (what to log) |
|---|---|---|---|
| Load Pot variability | Magnetic standard pot · Small pot · Non-magnetic (reject) · Off-center placement · Empty / half contact | Pot detect latency stable · Low-power output does not chatter · Mis-detect rate controlled (no-pot vs pot) · No nuisance OCP on placement | Pot-ID summary (phase/amplitude trend) · no-pot / small-pot / misalign counters · I_peak/Vbus_peak when detect fails · Trigger path flags |
| Power Low ↔ High | Low power stability · High power efficiency zone · Step 0→50→100% · Fast drop 100→20% | No low-power oscillation/whine triggers · Step does not cause OCP/OVP chatter · Vbus peaks remain controlled · Recovery behavior consistent | Operating region (freq/phase band) · Pre-event peaks (I_peak, Vbus_peak) · Window violations count · Power-step timing markers |
| Supply Disturbances | Low-line · High-line · Brownout sag · Plug/unplug transient · Surge behavior (event-driven) | No uncontrolled reset loop · UVLO/OVP/OCP events are correctly classified · Restart policy is deterministic (retry/lockout) | UVLO/brownout events + timestamps · Restart attempts/outcomes · Context snapshot (power level/mode) · Vbus summary around disturbance |
| Thermal Boundaries | High panel temperature · Restricted cooling boundary · Fan stall (only if fan exists) | OTP triggers are predictable (no chatter) · Derating follows intended domain (coil/device/panel) · No missed protection under sustained load | Coil/device/panel temperature samples · Derating level changes · OTP integral/time states · OTP counter with cause code |
| UI Touch & display | Touch rapid taps · Wet finger / water drops · Backlight PWM changes · Inverter fixed-frequency comparison | Touch baseline remains stable · False touch rate controlled · Backlight changes do not inject measurable UI noise or mis-triggers | Touch raw baseline + noise summary · Touch error counter · UI rail ripple summary · Correlation flag vs TP-SW event timing |
| Cross Worst × Worst | Small pot + low power · Off-center + power step · Brownout + high power · High panel temp + power step · Backlight change + inverter edge tuning | No new failure modes appear only in combinations · Protection classification remains consistent · Observables move as expected when knobs change | Same MFR format as above + “Cross-Point ID” · Peak snapshots on transitions · Any nuisance trip must include discriminator flags |
How to use the matrix as a release gate
- Run Base Case to validate measurement integrity (TP-BUS/TP-SW/TP-SENSE alignment and logging).
- Run Worst Case per dimension to validate robustness boundaries (pot, steps, brownout, thermal, UI).
- Run Cross-Points to catch interaction failures (mis-detect + protection chatter + UI noise).
- Freeze knob mappings (edge/loop/snubber/shield) with observables recorded for traceability.
H2-10 · Field Debug Playbook: Symptom → 2 Measurements → Branch → First Fix
Field debugging must be fast and repeatable. Each symptom below is written as a compact decision card: two measurements only, a single discriminator, a minimal first fix, a confirmation observable, and two logging patches that prevent the same blind spot next time.
Symptom: Low-power oscillation / audible whine
- First 2 measurements: TP-SENSE (windowed metric trend) + TP-SW (ringing tail shape).
- Discriminator: if oscillation aligns with TP-SW ringing bursts, the sense chain/window is polluted; if it aligns with threshold crossings, hysteresis/confirm logic is too tight.
- First fix: shift sampling window + add multi-cycle confirm/hysteresis; then reduce edge rate (gate strength) if ringing dominates.
- Confirm: fewer threshold crossings per second and a shorter ringing tail under the same pot/load.
- Log to add: threshold-cross counter + window-violation counter.
Symptom: Pot detect slow / false “no pot”
- First 2 measurements: Pot-ID metric summary (phase/amplitude trend) + TP-BUS (Vbus ripple).
- Discriminator: if failures appear only with high ripple or step events, detection is being disturbed by supply/noise; if only certain pots fail, the discriminators are under-separated for that load class.
- First fix: re-order scan/window timing and add debounce; if noise-coupled, reduce edge rate or tighten the sense reference path.
- Confirm: detect latency shrinks and mis-detect rate falls across small/off-center pots.
- Log to add: detect-state duration + misalign/no-pot event counter.
Symptom: Trips immediately at high power
- First 2 measurements: TP-BUS peak + TP-SENSE I_peak (windowed, not edge spikes).
- Discriminator: if I_peak persists across multiple windows, it is true overcurrent; if “peaks” are single-cycle and align with TP-SW ringing maxima, it is nuisance OCP from dv/dt injection.
- First fix: adjust OCP blanking/windowing and keep HW fast cut only for survival; add a controlled ramp (limit slope) for power steps.
- Confirm: I_peak/Vbus_peak reduce or become predictable under the same step profile; trigger path should move from nuisance to consistent classification.
- Log to add: pre-fault peaks (I_peak/Vbus_peak) + trigger-path flag (HW vs SW).
Symptom: Heating fluctuates when pot moves
- First 2 measurements: TP-SENSE phase trend + output power level (internal estimate/counter).
- Discriminator: if phase crosses decision thresholds repeatedly during motion, the control is too sensitive; if the phase metric itself becomes noisy only during switching bursts, the sensing window/reference is contaminated.
- First fix: add motion-tolerant hysteresis/hold time and widen the valid window; tighten the sense reference return if noise-coupled.
- Confirm: fewer phase-threshold toggles during controlled off-center sweeps.
- Log to add: phase-threshold toggle counter + misalign counter.
Symptom: Frequent over-temperature protection
- First 2 measurements: temperature domain readings (coil/device/panel) + power level vs time.
- Discriminator: if device temperature spikes quickly with small power changes, switching loss/edge tuning is likely; if panel temperature lags but triggers, sensor placement/derating policy is misaligned with thermal inertia.
- First fix: enforce staged derating (integral/time) per domain; reduce switching loss if device temp is dominant; avoid chatter by adding hold time.
- Confirm: OTP events become predictable with fewer on/off cycles under the same load profile.
- Log to add: OTP domain cause code + derating level history.
Symptom: Touch jitter / false touches
- First 2 measurements: touch raw baseline/noise + UI rail ripple.
- Discriminator: if touch noise follows UI rail ripple, it is supply coupling; if touch noise follows TP-SW event timing, it is return-path/E-field injection.
- First fix: isolate UI power/return and add filtering; if E-field/return-driven, enforce separation and a clean return reference for the touch front end.
- Confirm: raw-noise amplitude drops and touch error counter decreases with inverter on.
- Log to add: touch error counter + UI rail brownout counter.
Symptom: Display flicker / backlight interference
- First 2 measurements: backlight PWM node/rail ripple + TP-SW dv/dt trend.
- Discriminator: if flicker coincides with inverter edge-rate changes or bus ripple, the backlight supply is being modulated by power-path disturbances; if flicker tracks PWM only, it is a local backlight drive issue.
- First fix: decouple and isolate backlight supply; reduce conducted ripple coupling from power path; avoid sharing return impedance with switching currents.
- Confirm: backlight ripple becomes stable when power steps are repeated.
- Log to add: backlight ripple alarm counter + power-step event markers.
Symptom: EMI pre-scan fails / nearby devices disturbed
- First 2 measurements: TP-SW dv/dt + ringing tail + near-field trend (simple probe comparison).
- Discriminator: if edge-rate knob does not change dv/dt/ringing, the dominant path is elsewhere (loop/CM path); if loop changes shift ringing frequency/shape, layout is the first-order fix.
- First fix: apply the Top-3 order: close loops → tune edge → add snubber; define a single intentional shield/ground return point.
- Confirm: ringing tail shortens and near-field trend reduces in the same frequency bands.
- Log to add: knob-setting snapshot (edge/loop/snubber/shield) + “EMI issue” counter.
Shared discriminator branches (fast classification)
Branch A — Supply coupling
- Signature: UI and/or Pot-ID errors correlate with UI rail ripple or Vbus ripple peaks.
- First action: isolate supply/return, tighten loops, and confirm ripple observables move.
Branch B — Sense chain pollution (dv/dt injection)
- Signature: “peaks” align with TP-SW ringing maxima and disappear when windowing shifts.
- First action: shift window + add blanking/multi-cycle confirm, then slow the edge rate if needed.
Branch C — True electrical/thermal fault
- Signature: windowed metrics remain high across multiple cycles; temperatures rise predictably with load.
- First action: keep HW fast cut for survival; use SW limiting/integral and fix the physical cause (loss, cooling, loop).
Branch D — Decision thresholds too tight
- Signature: toggling around a boundary with clean signals; frequent chatter without matching noise observables.
- First action: add hysteresis/hold time and confirm reduced toggle count.
H2-11 · IC Selection (MPN Guidance): Swappable IC Families per Functional Block
IC selection for an induction cooktop should be organized by functional blocks and noise-immunity knobs, not by vendor lists. Each block below defines selection dimensions, “what goes wrong if chosen incorrectly”, two evidence points, and representative MPN examples that are commonly used in high dv/dt, high di/dt power environments.
Selection map (block → knobs → evidence → symptoms)
| Functional block | Key selection knobs | 2 evidence points | Representative MPN examples (3–5) |
|---|---|---|---|
| DriverGate driver | CMTI/dv-dt immunity · UVLO behavior · output drive strength · Miller clamp · DESAT/fast protection · isolation vs bootstrap | Gate waveform integrity · TP-SW dv/dt ↔ nuisance triggers correlation |
TI UCC21520 TI UCC21750 Infineon 1EDC60I12AH Infineon 1EDI60N12AF ADI ADuM4135
|
| SwitchPower switch | Rds_on vs Vce(sat) trade · switching loss vs EMI · thermal resistance/packaging · reverse conduction behavior · ruggedness margin | TP-SW overshoot/ringing shape · temperature rise vs power steps |
Infineon IKW40N120H3 onsemi FGH60N60SFD ST STGW40V60DF Infineon IPW60R041P7 onsemi NVMFS5C628NL
|
| SenseCurrent sensing | bandwidth vs delay · isolation/common-mode · layout injection risk · shunt amp vs Hall vs Rogowski | Windowed I metric stability · “peak” alignment with TP-SW ringing |
TI INA240 TI INA282 ADI AD8418A Allegro ACS758 LEM HO 25-NP
|
| TouchTouch controller | noise immunity algorithms · baseline recovery · configurable scan rate/window · moisture tolerance | touch raw noise vs UI rail ripple · touch raw vs TP-SW event timing |
Microchip AT42QT2120 Microchip ATMXT336T Renesas CTSU (RA MCU) Cypress/Infineon CAPSENSE (PSoC) ST STMPE811
|
| PowerAux power (PMIC) | PSRR (relevant bands) · load-transient response · UVLO hysteresis · EMI-friendly switching/packaging | UI rail ripple vs mis-touch/mis-detect · resets/retries vs brownout events |
TI TPS54202 TI TPS62130A Analog Devices LTC3646 ST L7987 TI TLV755
|
Gate driver ICs (high dv/dt immunity + predictable protection)
Selection knobs (what matters most)
- dv/dt immunity / CMTI: prevents false turn-on/false fault during fast switch-node transitions.
- Output drive strength: enables a controllable edge-rate knob (efficiency vs EMI).
- UVLO behavior: output state must be predictable during rail sag and restart.
- Miller clamp / soft turn-off: reduces dv/dt induced turn-on and improves survivability.
- DESAT / fast protection hooks: required when the power stage can enter destructive overcurrent quickly.
Evidence chain (2 quick checks)
- Gate waveform integrity: no spurious pulses or re-triggering during high dv/dt events.
- Correlation test: nuisance trips must track TP-SW ringing/dv/dt if injection is the cause; after window/blanking changes, the correlation should weaken.
Representative MPN examples (and why they fit noisy power stages)
TI UCC21520— isolated dual-channel gate driver, commonly used where CMTI and clean switching behavior are priorities.TI UCC21750— isolated driver family with protection-oriented features (DESAT-capable variants), useful for fast fault handling.Infineon 1EDC60I12AH— isolated driver family designed for robust high dv/dt environments.Infineon 1EDI60N12AF— robust isolated driver family, often used when predictable behavior under noisy switching is required.ADI ADuM4135— isolated gate driver with strong isolation emphasis; suitable when common-mode disturbance is a primary risk.
Replacement rule: keep the same isolation class and verify that changing gate resistance shifts TP-SW dv/dt without creating new spurious gate activity.
Power switches (IGBT vs MOSFET): thermal margin and switching behavior
Selection knobs
- Conduction vs switching loss: pick a loss balance that matches operating frequency and power-step behavior.
- Package thermal path: RθJC/RθJA and mounting interface determine OTP headroom.
- Reverse conduction behavior: affects overshoot, ringing, and protection chatter.
- Ruggedness margin: choose devices that tolerate overshoot/di/dt within the expected stray inductance.
Evidence chain
- TP-SW shape: overshoot + ringing tail must be controllable with edge tuning and snubber adjustments.
- Thermal slope: temperature rise vs step profile must remain consistent across pot variations and airflow boundaries.
Representative MPN examples
Infineon IKW40N120H3— IGBT class often used in robust mains-powered inverter designs where voltage margin is required.onsemi FGH60N60SFD— IGBT family used for power stages that need strong ruggedness and predictable switching.ST STGW40V60DF— IGBT family used in inverter applications; verify switching loss vs EMI in the target frequency band.Infineon IPW60R041P7— high-voltage MOSFET family often used when MOSFET-based stages are preferred for switching behavior.onsemi NVMFS5C628NL— power MOSFET example (useful in lower-voltage sub-stages or auxiliary switching needs).
Replacement rule: do not substitute across package/thermal class without re-running the H2-9 thermal boundary rows and verifying OTP headroom.
Current sensing (shunt amp vs Hall vs Rogowski): bandwidth, isolation, and injection risk
Selection knobs
- Windowed measurement integrity: prioritize stability inside the sampling window, not edge spikes.
- Common-mode and isolation: Hall/Rogowski reduce common-mode injection risks in high dv/dt environments.
- Bandwidth vs delay: too slow increases control lag; too fast can amplify switching artifacts.
- Layout sensitivity: shunt + amp can be excellent but is sensitive to return impedance and kelvin routing.
Evidence chain
- Stability test: windowed I metric repeatability across repeated steps (same pot/position).
- Injection test: “peaks” that align with TP-SW ringing indicate dv/dt injection rather than true overcurrent.
Representative MPN examples
TI INA240— current-sense amplifier family known for PWM/fast-edge environments (good for windowed measurements when layout is correct).TI INA282— high-side current-sense amplifier family suitable for robust current monitoring.ADI AD8418A— current-sense amplifier family commonly used where dynamic behavior and robustness are important.Allegro ACS758— Hall-effect current sensor family providing galvanic isolation and reduced common-mode injection risk.LEM HO 25-NP— closed-loop Hall sensor family used when isolation and linearity are priorities.
Replacement rule: re-run the H2-9 “step 0→50→100%” rows and confirm that OCP classification remains stable (no new nuisance trips).
Touch controllers (coexistence with strong E-fields and conducted noise)
Selection knobs
- Noise immunity and baseline recovery: must tolerate strong electric fields and moisture/water drops.
- Configurable scanning: scan rate/window controls help avoid coupling with inverter noise events.
- Diagnostics hooks: access to raw baseline/noise metrics enables evidence-driven debug.
Evidence chain
- Two-step test: inverter off (backlight on) to establish baseline; inverter on (fixed power) to correlate noise with TP-SW events.
- Supply coupling check: touch raw noise tracking UI rail ripple indicates power coupling, not algorithm weakness.
Representative MPN examples
Microchip AT42QT2120— capacitive touch controller family used in appliance HMIs for stable key sensing.Microchip ATMXT336T— maXTouch controller family used where robust multi-touch and noisy environments are expected.Renesas RA (CTSU)— RA MCU family with capacitive touch sensing unit, enabling tight integration and control over scan timing.Infineon/Cypress PSoC 4/6 (CapSense)— MCU family with CapSense for configurable scan and strong firmware control of diagnostics.ST STMPE811— touch controller example (useful when integrating with certain display/touch stacks; verify immunity with inverter on).
Replacement rule: verify that touch raw noise does not increase when gate edge strength is adjusted (cross-check with TP-SW dv/dt).
Aux power: DC-DC / LDO (PSRR and transient response as the coexistence foundation)
Selection knobs
- PSRR in relevant bands: prioritize rejection where the system is most sensitive (UI rails, sensing references).
- Load transient response: backlight/touch/display activity must not pull rails into brownout-like behavior.
- UVLO + restart behavior: predictable recovery avoids repeated mis-detect cycles and phantom faults.
Evidence chain
- UI rail ripple: correlate rail ripple with touch errors and pot mis-detect counts.
- Brownout markers: confirm resets/retries align with real sag events (not false flags).
Representative MPN examples
TI TPS54202— buck converter family for auxiliary rails; validate ripple coupling to touch raw.TI TPS62130A— high-efficiency buck family often used for low-noise rails with good transient behavior.ADI LTC3646— buck regulator family used where stability and predictable behavior under noise are important.ST L7987— buck converter family suitable for appliance auxiliary rails; validate EMI knob interactions.TI TLV755— LDO family often used for clean UI/sensing rails (confirm PSRR adequacy for the sensitive path).
Replacement rule: for any PMIC change, re-run H2-9 UI rows (wet finger/backlight change) and confirm touch error counters remain controlled.
Procurement-friendly replacement rules (how to avoid lock-in)
- Lock the knobs, not the brand: specify CMTI/UVLO behavior/drive strength class for drivers, and windowed measurement stability for sensing.
- Keep thermal class consistent: package and thermal interface must match, or OTP margins change and validation must be repeated.
- Validate by observables: a valid replacement must move TP-SW dv/dt and ringing in the expected direction when edge tuning is adjusted.
- Re-run minimal rows: if the block changes, rerun only the relevant Base + Worst + Cross-Points rows from H2-9, using the same log format.
Request a Quote
H2-12 · FAQs (12 Evidence-Based Questions)
Each FAQ is written to land back on this page’s evidence chain: TP-SW (switch node), TP-BUS (DC link / bus), TP-SENSE (windowed metrics), and (when UI is involved) touch raw and UI rail ripple. Answers use a fixed format: two checks → discriminator → first fix.
1 Why does “no pot” sometimes get detected as “pot present”?
Most intermittent no-pot errors come from dv/dt injection rather than a truly wrong threshold. Run two checks: (1) capture TP-SW ringing tail timing; (2) inspect the windowed phase/amplitude metric for spikes exactly at the ringing peak. If correlation is strong, fix by shifting the sampling window and adding blanking/hysteresis.
2 Low-power squeal is worse than high power—resonance drift or control resolution?
Low-power squeal usually means the operating point keeps crossing a stability boundary. Two checks: (1) track the phase trajectory (does it bounce around a decision edge?); (2) observe TP-BUS ripple or power estimate periodicity. If phase repeatedly crosses a boundary, prioritize resonance/criteria hysteresis; if phase is stable but power steps are coarse, increase low-power resolution and clamp transitions.
3 Power surges up/down with off-center pots—real load change or dv/dt-polluted sensing?
Off-center placement can change coupling, but dv/dt pollution can fake the same trend. Two checks: (1) verify the windowed TP-SENSE metric changes smoothly and repeatably with pot position; (2) compare metric jumps to TP-SW ringing peaks. Smooth, repeatable drift points to real load change; sharp jumps aligned to ringing indicate injection. First fix: re-align window/blanking, then tighten sense routing (Kelvin/return loop).
4 Trips immediately at high power—tight OCP threshold or bus spike triggering OVP?
Classify the trip by what peaks first. Two checks: (1) pre-fault TP-BUS peak; (2) pre-fault windowed current metric. If VBUS spikes first and crosses the OVP boundary, fix the bus spike path (layout parasitics, absorption, controlled ramp). If current stays high inside the window, treat as real OCP. If “current” is only a narrow spike aligned to TP-SW ringing, it is a nuisance OCP—use blanking and stronger discrimination.
5 Touch jumps during heating—fastest 2-step method to separate supply coupling vs ground return?
Use a controlled A/B test. Step 1: inverter OFF, backlight/display ON—log touch raw baseline and UI rail ripple. Step 2: inverter ON with fixed power/frequency—compare touch raw against TP-SW event timing. If touch noise tracks UI ripple, fix supply isolation/PSRR and transient response. If rails are clean but touch noise tracks TP-SW events, fix ground return partitioning and field coupling paths.
6 Touch drifts when backlight brightens—LED driver noise or common-mode injection?
Treat the backlight as a controlled noise injector. Two checks: (1) measure UI rail ripple while toggling PWM duty/frequency; (2) observe whether touch raw shows a component synchronous with PWM. PWM-synchronous drift suggests LED driver coupling (filtering and return isolation). If drift does not track PWM but spikes align with TP-SW events, it is common-mode/ground return injection. First fix: isolate backlight power/returns and adjust scan timing.
7 EMI fails—tune gate resistor first or add snubber first? What evidence sets priority?
Decide using two observables on TP-SW: (1) dv/dt steepness; (2) ringing tail length (frequency and decay time). If dv/dt is too steep but the tail is short, start with gate edge control (gate resistor/drive strength). If the tail is long or overshoot is large, start with snubber/loop area reduction. After each change, confirm the same metric moves predictably before layering more fixes.
8 Power drops after minutes—real OTP or temperature sensing lifted by noise?
True thermal protection follows thermal inertia; noise-lifted sensing often looks like abrupt jumps. Two checks: (1) compare slopes across coil/device/panel temperature channels; (2) snapshot TP-SW/TP-BUS around the drop event. If one sensor jumps sharply or correlates with switching events, improve sensing window/filtering and add “sensor plausibility” logging. If all channels rise coherently and the drop matches thermal boundaries, treat as real OTP and adjust thermal path or derating thresholds.
9 Efficiency varies widely across pots—how to explain via Req/Q trends without guesswork?
Explain pot behavior using measurable trends. Two checks: (1) during a controlled scan, extract the trend of Req (effective resistive loading); (2) track the width of the stable phase region as a proxy for Q and control margin. Lower Req can enable stronger coupling but may narrow control margin; higher Req often forces higher current for the same power setpoint, raising losses and EMI stress. Tune scan steps/hysteresis per pot family.
10 TP-SW ringing is large but thermal looks fine—why can it still cause mis-detect or nuisance trips?
Thermal margin does not guarantee signal integrity. Large ringing can inject false peaks into sensing and protection paths. Two checks: (1) align Pot-ID / OCP metric spikes against the ringing peak timing; (2) compare “good vs bad” TP-SW snapshots to see if ringing tail length changes. If spikes are time-aligned with ringing, treat it as injection: move windows, add blanking/hysteresis, and shorten the ringing tail using loop reduction or snubber.
11 Field occasional freeze/reset—what are the first two power evidences to capture?
Start with two rails that bracket the failure: (1) the MCU/logic rail (plus reset/UVLO marker); (2) the driver/aux rail that experiences inverter start/stop stress. If both sag together, suspect upstream supply or shared return impedance. If only logic sags, suspect local PMIC transient response or coupling from UI loads. If only driver rail sags, suspect UVLO behavior or protection chatter. First fix: improve rail isolation and add “last-reset reason” plus brownout counters.
12 Same unit trips more on different household mains—brownout first or surge first?
Classify the mains stress by voltage shape, not by guess. Two checks: (1) capture TP-BUS for sag (brownout) vs spike (surge); (2) record which protection path triggers first (UVLO/OVP/OCP). Sag plus resets points to brownout handling: UVLO hysteresis, controlled ramp, energy buffering. Spikes with OVP points to surge/backfeed and parasitic inductance: input filtering, loop reduction, absorption. If neither is visible but OCP is frequent, revisit windowing and injection discrimination.
