Home Backup PSU / UPS: Charging, Inverter, Transfer, Metering
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A home backup PSU/UPS is only “reliable” when transfer, inverter output, charging/balancing, metering, and logs are designed as one evidence-driven system. The fastest way to fix real-field failures is to capture two evidence points (one waveform + one log field), isolate the root cause, then verify a single first fix.
H2-1. Scope, Use Cases & System Boundary (Home UPS vs Backup PSU)
This chapter is a boundary contract: it covers only the hardware evidence chain for home/small-site backup continuity (charge/balancing → battery protection → inverter → transfer → metering → faults & logs). It does not expand into HEMS strategy, grid-tied PV/MPPT, whole-home wiring/code tutorials, utility metering standards, or data-center UPS architecture.
A home backup PSU/UPS is a battery-based continuity system. The engineering core is not “battery size” alone, but whether transfer is fast enough, inverter output stays load-friendly, charging/balancing is controllable, metering is trustworthy, and fault causes are traceable via logs.
Typical forms (only what changes the evidence)
- Desktop AC UPS: designed to avoid resets. Evidence focus: transfer time, Vout dip, overload tolerance, THD/transients.
- Wall-plug / compact backup PSU: tighter thermal budget. Evidence focus: surge/inrush robustness and derating behavior.
- Dedicated DC UPS (router/security/gateway): DC output continuity. Evidence focus: seamless power-path, low noise, light-load metering & self-consumption.
- Home backup box (device-level): emphasizes runtime, noise, logs. Evidence focus: event recorder, latch reasons, capacity/health drift over time.
Note: “ATS/transfer” here means device-level or load-level switching, not whole-home distribution wiring.
Key metrics → minimum evidence set (what to measure first)
| Metric | Common symptom | Minimum evidence (2–3 items) | How to decide (engineering logic) |
|---|---|---|---|
| Transfer time | Brownout/brief outage causes reboots (router/NAS/security) | Vac_sense, Vout, Transfer_ctrl (relay coil / SSR gate) | Align reboot moment with Vout dip duration; separate slow transfer from slow inverter ramp. |
| Hold-up / Runtime | “Shows 60%” yet suddenly shuts down | Vpack, Ipack, SoC register/log, UVLO/fault flags | Differentiate pack IR sag (transient) vs SoC estimation drift (model/offset). |
| Surge tolerance | After storms / repeated plug-ins: charging becomes unstable | Inrush peak, rectified bus, protection part temperature/inspection | Look for protection stack overstress vs control lockout (latched fault). |
| Vout quality (THD/transient) | On battery mode: some SMPS loads buzz, drop link, or reset | Vout waveform, load step response, current-limit behavior | Decide if the issue is waveform compatibility, transient droop, or EMI coupling. |
| Noise / Thermal | Fan gets loud at modest power; enclosure feels hot | Hotspot NTCs/thermal map, airflow status, derating threshold | Confirm real hotspot location; then trace whether control is over-conservative or sensors are misplaced. |
| Metering accuracy | Energy/runtimes look inconsistent across temperature or light loads | Shunt/Hall raw readings, offset/zero logs, temperature vs drift | Prove whether drift is sensor/AFE offset, bandwidth limits, or switching noise injection. |
| Fault traceability | Random lockout; “works after unplugging” | Event log timeline, latch reason code, retry counter | Reconstruct the sequence: state → evidence → action → protection → latch. |
Deep here: charge/balancing PMICs, inverter, transfer switching, metering, fault logs, validation evidence. Link only: HEMS strategy, utility meter standards, grid-tied PV/MPPT, whole-home distribution wiring.
Figure H2-1 — Scope boundary & evidence map
The page stays strictly vertical: continuity hardware evidence only. Cite this figure ID: SHA-UPS-F01
H2-2. Architecture Overview: Power Path States & Energy Flow
This chapter builds the “system spine”: energy flow + state machine. Every later section references a node on this diagram and a small set of signals that must be observable in that state.
Three parallel chains are shown: (1) power path (energy flow), (2) telemetry (what gets measured), and (3) actuation (what gets switched). Logs must correlate all three: state → measurements → actions.
State machine (each state binds a minimum signal set)
- Line Mode: Vac present, Vout regulated, charger idle/limited.
- Charge / Recharge: Icharge phase (CC/CV), Vpack rising, Tcell within window.
- Battery Mode: inverter enabled, Vbus managed, Vout quality + current limit monitored.
- Transfer Event: transfer control edges; verify Vout dip duration and bounce/commutation behavior.
- Fault Lockout: latched reason code, retry counter, cool-down timer, event log snapshot.
Figure H2-2 (F1) — Power path + telemetry + actuation + state machine
Use this as the page spine: every later section must map to a node and a measurable signal set. Cite this figure ID: SHA-UPS-F02
H2-3. AC Input Front-End: Surge/Inrush/EMI & Charger Interface
This chapter focuses only on reliability-critical AC entry behavior: surge/ESD-like overstress signatures, inrush and hot-restart behavior, and EMI constraints that can destabilize the charger interface. It avoids PFC/topology derivations and stays evidence-first.
AC-entry issues rarely look like “AC-entry issues” in the field. Common symptoms include: intermittent charge refusal after plug-in, repeated failures on hot restart, unexplained latch faults, or EMI hot-bands that appear only during charge transitions.
- Layer 1 — Surge clamp: MOV/TVS (and related clamps) to absorb line spikes and prevent soft-breakdown in downstream parts.
- Layer 2 — Inrush control: NTC or active inrush control to manage plug-in peak current and repeated hot restart stress.
- Layer 3 — Fusing / disconnection: fuse/breaker/disconnect logic to prevent “half-damaged but still running” unsafe states.
- Layer 4 — EMI filter: common-mode + differential-mode filtering (X/Y capacitors, CM choke, DM inductors) to keep noise contained.
- Layer 5 — Rectifier / bus: rectified bus behavior determines whether the charger sees a clean ramp or a bouncing supply.
- Surge robustness vs leakage/EMI: stronger clamps and filters can increase leakage paths and change EMI behavior; verify with evidence, not assumptions.
- NTC vs active inrush: NTC is simple but can fail on hot restart (still warm). Active inrush is controllable but timing-critical; prove bus ramp stability.
- Inrush peak and waveform: confirms hot-restart stress and whether inrush control behaves as intended.
- Rectified bus ramp (Vrect/Vbus): proves whether the charger input is stable or bouncing into UV/OV comparators.
- Clamp/leakage signature: post-surge leakage or abnormal heating indicates soft-damage that often becomes intermittent faults.
- EMI hot-bands: locate frequency “hot spots” and correlate with state transitions (charge start, CC→CV, load steps).
Logging hooks: capture bus ramp time, peak inrush indicator, and the first latch reason after plug-in to keep field debug reproducible.
Figure H2-3 (F2) — AC entry protection stack (plug → charger)
A compact view of surge/inrush/EMI layers and the minimum evidence set for fast field debug.
Cite this figure
ID SHA-UPS-F03
H2-4. Battery Pack & Protection: Chemistry, Sensing, Cutoff, Thermal
This chapter defines the hard boundary of the battery pack + BMS: what must be measured (cell/pack voltage, pack current, temperatures), what must be protected (OV/UV/OCP/OTP/short/reverse), and how temperature extremes and aging translate into transient sag and false trips.
- 1–4S Li-ion: higher energy density; aging and cold temperature can increase internal resistance, making transient sag more pronounced.
- 1–4S LiFePO4: different voltage window; often behaves differently under cold conditions and load steps; verify UVLO thresholds with evidence.
- Cell taps (Vcell): detect imbalance and weak cells; verify connector integrity and sampling response (filtering vs events).
- Pack current (Ipack): shunt or Hall; watch offset drift, bandwidth limits, and switching-noise injection into the sense path.
- Temperature points (Tcell / Tcase / Thotspot): place NTCs where protection decisions are meaningful; wrong placement causes false OTP or missed hotspots.
- Hard cutoff (short/severe OCP): immediate disconnect; logs must capture “which flag first” to avoid ambiguous root cause.
- Soft limit / derating (thermal/overload): reduces output or current; often seen as runtime drop or noisy operation rather than a clean shutdown.
- Temperature window gating: cold/hot windows can limit charge/discharge; without clear logs this looks like “battery failure”.
Cold temperature or aging increases pack internal resistance, creating larger transient sag during load steps. Evidence should separate: (1) Vpack step sag & recovery (IR signature) versus (2) abnormal ΔV across cells and ΔT hotspots (cell/thermal issues).
Figure H2-4 (F3) — Battery sensing & protection signals
Shows the minimum sensing points and protection cutoffs needed to separate transient sag from false trips and thermal risks.
Cite this figure
ID SHA-UPS-F04
H2-5. Charge & Balance PMICs: Selection Matrix and Practical Limits
This chapter goes deep on charge/balance PMIC selection and validation without topology derivations. It treats charging as an interface-controlled process (adapter/DC bus input, uni-/bi-directional capability, power-band and thermal limits), then makes every requirement testable via phase markers, temperature evidence, and termination reason codes.
A charge/balance PMIC must make three things provable: (1) the correct phase transitions (CC→CV→Top-off), (2) safe behavior across temperature windows (JEITA-style gating and derating), and (3) traceable outcomes via termination and fault reason codes that survive field conditions.
| Decision axis | What to require | Minimum evidence | Common field pitfall |
|---|---|---|---|
| Input interface | Adapter DC vs rectified DC bus; expected brownouts; hot-restart tolerance | Input voltage ramp, input current limit, fault pin behavior on plug-in | Charge refusal after plug-in due to unstable ramp or latched fault |
| Uni-/bi-directional | Power-path constraints; whether load and charge overlap is allowed | Phase markers + system load correlation; “why CV oscillates” evidence | CV “bounce” caused by load steps during end-of-charge |
| CC/CV control | Accurate CC setpoint; stable CV regulation; top-off configurability | Icharge curve shape; Vpack settling; CC→CV transition marker | Premature termination → fake “100%” but short runtime |
| Termination logic | Clear termination modes: Iterm, timer, temperature window, fault | Termination reason code + final Icharge + Vcell_max snapshot | Mis-termination → heating, swelling risk, or capacity inflation |
| JEITA / windows | Charge enable/derating across T ranges; low-temp inhibit | Tcell + window state + derating factor logged | Low-temp charge blocked but looks like a “broken charger” |
| Protection set | Pack OVP/OCP, short, reverse, safety timers, latch behavior | Fault ordering + latched reason + retry counter | Intermittent latch without root cause due to missing reason codes |
| Telemetry | I²C visibility into phase, flags, counters; fault pins for fast capture | Readable phase + flags; interrupt line capture; timestamped snapshot | Field debug impossible: “works after reboot” with no evidence |
| Balance method | Passive vs active; balance current; thermal path; trigger conditions | Balance enable marker + hotspot ΔT during balance | Balance never executes due to thermal derating or too-small current |
| NVM params | Param versioning, lock/CRC, safe defaults, rollback strategy | Param ID/version + CRC in logs; mismatch detection | Batch issues: wrong profile silently applied; capacity/heat anomalies |
Practical limit rule: power-band is often thermal-limited first; treat “max charge power” as a derating curve, not a single number.
- CC→CV transition: verify the turning point is consistent across input voltage and temperature.
- Top-off behavior: confirm it does not oscillate with background loads (power-path overlap evidence).
- Balance thermal: record hotspot ΔT while balancing; prove balance current is real, not “enabled but derated to zero”.
- Termination reasons: log termination codes (Iterm / Twindow / Timer / Fault) with Vcell_max snapshot.
Figure H2-5 (F4) — CC→CV→Top-off→Balance timeline (I/V/T)
A phase-centric view to validate phase markers, thermal behavior during balancing, and termination reason codes.
Cite this figure
ID SHA-UPS-F05
H2-6. Inverter Stage: DC-AC Quality, Transients, Audible Noise, Efficiency
This chapter makes inverter performance measurable: output compatibility (waveform types only as load-facing differences), transient behavior and overload response, audible noise tied to control-mode transitions, and efficiency/thermal derating that must be traceable by protection ordering and logs.
- Square / Modified sine: can stress some SMPS inputs and increase audible artifacts; verify compatibility by load reset probability and waveform evidence.
- Pure sine: typically best compatibility; still must prove load step behavior and overload strategy.
Compatibility should be decided by evidence: Vout distortion during events, load reset rate, and current-limit behavior.
- Vbus sag margin: Vbus minimum during load steps must stay above UVLO with adequate margin across temperature and aging.
- Overload strategy: decide (and log) whether behavior is constant-current, foldback, or shutdown; avoid ambiguous resets.
- Audible noise cause: correlate noise with control-mode transitions (burst/skip/limit), not with “mystery hardware”.
- Thermal derating: verify that derating is gradual and traceable via reason codes, not a sudden unexplained drop.
For any disturbance (mains loss, transfer event, load step), record: state marker → Vbus minimum → Vout dip duration → current-limit mode → fault code (if any). Without ordering, “random shutdown” cannot be isolated.
Figure H2-6 (F5) — Load step response (Vout/Vbus/limit mode)
A minimal but testable view for compatibility, transient stability, and protection ordering.
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ID SHA-UPS-F06
H2-7. Transfer / ATS: Seamless Switching, Relay vs Solid-State, Safety Interlocks
This chapter turns “seamless switching” into a measurable timing chain: mains-sense → decision → actuation (coil/gate) → Vout recovery → post-check → event record. It compares relay and solid-state transfer by the failure modes that matter in home UPS products.
- Transfer time: Vout dip duration below a reset threshold must be measured, not guessed.
- Ordering: prove whether the cause is slow decision, slow actuation, bounce, or inverter takeover delay.
- Safety interlocks: prevent backfeed and momentary paralleling; log interlock state during transfer.
| Switch type | Strength | Risk that shows up in field | Evidence to capture |
|---|---|---|---|
| Relay | Low leakage; clear isolation when open | Contact bounce; wear; timing drift; arcing/EMI if not controlled | Coil drive vs Vout dip; bounce signature; zero-cross marker alignment |
| Solid-state | Fast actuation; can enable controlled switching | Leakage current; heat; surge/SOA limit; dv/dt false turn-on | Gate timing; thermal rise; surge transient; dv/dt correlated anomalies |
Practical rule: switching choice must be validated by the transfer timing chain and safety interlocks, not by component specs alone.
Record four traces on every suspected “blink/reboot”: mains-sense, decision marker, relay/SSR actuation, and Vout. Compute t_decision, t_actuation, and Vout_dip_ms, then attach the event with a reason code.
Figure H2-7 — Transfer timing chain (mains→decision→actuation→Vout)
A waveform-first view to isolate “blink/reboot” root causes by timing and ordering.
Cite this figure
ID SHA-UPS-F07
H2-8. Metering & Runtime Estimation: Accuracy, Drift, and Tamper-Resistance (Home Context)
This chapter treats metering as a UPS-specific value: credible runtime minutes, load power, cycle statistics, and health hints. It avoids smart-meter standards and focuses on the signal chain, drift sources, two-point calibration, and light-load error amplification.
- Current sensing: offset and temperature drift must be bounded; bandwidth must catch load steps.
- Conversion: sampling and filtering must not alias inverter ripple into “fake power”.
- Coulomb counting: integration drift must be corrected by calibration anchors and sanity checks.
- Runtime estimator: must react to load changes and temperature; minutes must remain explainable.
- Zero-point: record offset at near-zero current; store per temperature bucket if needed.
- Gain-point: calibrate with a known load; verify across battery and line modes.
- Temp sweep: capture drift curve (at least two temperature regions); apply compensation or derating flags.
- Light-load: quantify error amplification; show how minutes can swing without offset control.
Expose SoC%, remaining minutes, load power, and temperature/fan states with internal traceability: offset/gain version, estimator state, and anomaly flags must be available in logs for disputes and service.
Figure H2-8 — Metering chain + error map + two-point calibration
A UPS-focused metering view: prove drift control, light-load credibility, and estimator traceability.
Cite this figure
ID SHA-UPS-F08
H2-9. Fault Handling, Event Recorder & Logs: What to Log so Field Debug is Fast
Faults and logs are a product moat: the goal is fast root-cause reconstruction (what happened first, who triggered, and whether it was a false alarm), using a minimum field set and power-loss-safe writes.
| Group | Fields (minimum) | Why it matters |
|---|---|---|
| Header | ts, event_id, state, seq |
Reconstruct time ordering; detect missing/partial entries; avoid “same timestamp” ambiguity. |
| Snapshot | V_in, V_bus, V_out, I_pack, I_out, T_hot, T_batt |
Proves sag, overload, and thermal conditions at the moment of a trip. |
| Decision | fault_code, trip_source, action, retry_count |
Shows who triggered (OVP/OCP/OTP/UVLO/interlock) and what protection did first. |
| Context | mode (line/battery/recharge), est_state, soc, minutes |
Connects the event to transfer, metering, and runtime estimation without adding cloud/HEMS scope. |
Keep logs short but decisive: store “ordering + reason + snapshot”, not long prose.
- Mains loss / restore: add
t_decision,t_actuation,Vout_dip_ms,transfer_type. - Overload / inrush: add
I_peak,limit_mode,limit_ms,Vbus_min. - Over-temp / derating: add
T_hot_peak,derate_level,fan_state,threshold_id. - Comms anomaly (local interface): add
iface_id,err_count,last_ok_ts(no cloud details).
Write payload first, then CRC, then a final commit marker (or valid flag). On boot, scan for the highest seq with a valid commit.
If commit is missing, the record is ignored.
Figure H2-9 — Ring buffer + power-loss-safe commit ordering
The commit marker is written last; incomplete entries are ignored after reboot.
Cite this figure
ID SHA-UPS-F09
H2-10. Protection & Compliance: Leakage/Isolation, RCD/GFCI Interaction, Thermal Derating
Safety must be engineered with evidence, not legal text. This chapter focuses on leakage and isolation paths, how transfer and EMI components can interact with RCD/GFCI devices, and how thermal derating is made measurable via hotspot sensing and logged thresholds.
- Leakage / isolation: quantify leakage under relevant states (line, battery, transfer); record isolation check results.
- RCD/GFCI interaction: correlate trip timing to transfer or inverter start/stop events; capture the event window in logs.
- Thermal derating: define hotspot sensor placement; log threshold crossings and derate levels.
| Level | Trigger (examples) | Action | Log fields |
|---|---|---|---|
| L0 | Below warning threshold | Normal operation | threshold_id, T_hot |
| L1 | Hotspot rising; airflow margin shrinking | Fan up / power cap | derate_level, fan_state |
| L2 | Near thermal limit or repeated overload heating | Current limit / reduced output | limit_mode, T_hot_peak |
| L3 | Over-temperature or unsafe condition | Shutdown + lockout | fault_code, action |
When a trip is reported, correlate it to the transfer event window: capture Vout dip, switch actuation, and leakage-related conditions in the same log sequence so “mis-trip vs real fault” can be separated.
Figure H2-10 — Thermal path, hotspot sensors, and leakage/RCD evidence points
Keep safety explainable: correlate trips and derating to logged thresholds and measured paths.
Cite this figure
ID SHA-UPS-F10
H2-11. Validation & Field Debug Playbook (Symptom → Evidence → Isolate → Fix)
A fast triage format for home UPS failures. Each symptom is reduced to two measurements, a binary discriminator, and a first fix that can be verified quickly. MPNs are examples (ratings must match the design).
Capture Vout plus one of Vbus/Vpack/Ipack, and export the last 20 events (fields: event_id state seq fault_code trip_source action retry_count).
Symptom 1 — After a mains outage, the load still reboots
Symptom Load resets during “backup takeover” despite a healthy battery.
First 2 Measurements (1) Vout dip depth + duration; (2) event window: t_decision, t_actuation, Vout_dip_ms.
Discriminator If Vout “hard-gaps” aligned to actuation → transfer delay/bounce (H2-7). If Vout stays continuous but ramps/distorts → inverter takeover/limit (H2-6).
First Fix Tighten transfer timing (zero-cross + debounced decision) or reduce bounce; alternatively speed inverter ramp. Example MPNs: H11AA1 (AC zero-cross), MOC3063 + BTA16-600 (zero-cross triac path), OMRON G2RL-1A (relay class), UCC21520 (isolated gate driver).
Symptom 2 — Light-load runtime is overstated (minutes “look good”, reality drops fast)
Symptom At small loads, the remaining-time estimate is optimistic and collapses later.
First 2 Measurements (1) Ipack near-zero offset vs temperature; (2) battery-mode self-consumption (Ppack vs Pout).
Discriminator If Ipack does not return to ~0 A and drifts with temperature → metering offset/drift (H2-8). If metering is stable but Ppack is high at light load → light-load efficiency/self-power (H2-6/H2-10).
First Fix Apply two-point calibration + temp binning for offset; reduce always-on rails/fan at light load. Example MPNs: INA240A1 (current sense amp), TPS25940 (eFuse / inrush control), B57236S0100 (NTC inrush), V14E275 (MOV class), BQ25713 (buck-boost charger interface), FM24CL64B (I²C FRAM for lockout logs).
Symptom 6 — Output derates or shuts down after running for a while
Symptom Power capability drops (fan ramps) or a late shutdown occurs after sustained use.
First 2 Measurements (1) T_hot + derate_level + threshold_id in logs; (2) airflow margin: T_amb at intake vs hotspot rise rate.
Discriminator If T_hot rises smoothly and correlates with load and airflow → real thermal limit (H2-10). If T_hot jumps/glitches or contradicts other points → sensor placement/noise injection (H2-10/H2-9).
First Fix Re-anchor hotspot sensing and implement a derating ladder that is fully logged; stabilize fan control. Example MPNs: TMP117 (accurate temp sensor) or NCP18XH103 (NTC), MAX31760 (fan controller), MCP7940N (RTC for timestamps), W25Q32JV (SPI flash for extended logs).
Figure H2-11 — Symptom → 2 evidence points → root cause (chapter-mapped)
Use the same evidence fields across devices to shorten triage time. Cite this figure ID SHA-UPS-F11
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H2-12. FAQs (12) — Evidence-First, Chapter-Mapped
Each answer stays inside this page’s evidence chain (charge/balance, inverter, transfer, metering, logs, safety, validation). No cloud/HEMS deep dive. MPNs are examples; match ratings and safety requirements to the design.
For any question, collect two evidence points first (one waveform + one log field). Then use the binary discriminator to isolate the cause and apply one “first fix” that can be verified immediately.
1) “A short mains blink still reboots my load” — check transfer time or inverter ramp first?
Start with Vout_dip_ms and whether the dip aligns with actuation (relay coil / SSR gate). A hard gap aligned to actuation points to transfer delay or contact bounce; a continuous but slow/warped recovery points to inverter soft-start or current limiting. First fixes: add zero-cross decision and reduce bounce (H11AA1, G2RL-1A) or tighten SSR switching (MOC3063).
2) “It shows 60% battery, but it suddenly shuts down” — what two evidence points first?
Capture a load-step ΔVpack (sag at the same load) and the log’s trip_source/fault_code. Large sag with cold sensitivity indicates rising internal resistance or weak cells; small sag but UV trips suggests a threshold/estimator issue. First fixes: temperature-bin UV thresholds and log them, and validate fuel-gauge/pack-protector settings (MAX17055, BQ77915, INA240A1).
3) “It UV-shuts down more often in winter” — ESR rise or threshold temp drift?
Compare ΔVpack@step across temperatures and check whether threshold_id changes with temp bins. If sag grows strongly with cold at the same load, it is a battery ESR effect; if sag is modest but the UV trigger shifts, it is logic/measurement drift. First fixes: add temp-aware derating and confirm NTC placement and compensation (NCP18XH103, MAX17055, BQ77915).
4) “It won’t fully charge / charges very slowly” — input front-end limiting or charger stage logic?
Check Vbus behavior under charge (droop or current clamp) and the charger’s stage/retry_count logs. If Vbus collapses or inrush triggers protection, it is front-end power limiting; if Vbus is stable but stages flap, it is stage/JEITA/termination logic. First fixes: stabilize inrush/limits and verify stage thresholds (TPS25940, BQ25713, B57236S0100).
5) “Balancing runs forever and never converges” — cell mismatch or balance current/thermal limit?
Measure cell delta (max–min) and log balance_state with T_hot during balancing. If delta barely moves while balance is throttled by temperature, the limit is thermal/current; if delta rebounds after rest, the cells are mismatched. First fixes: increase balance headroom and log throttling causes; consider monitor/balancer choices (BQ76952, LTC3300-1).
6) “On battery, the router/NAS drops or gets noisy” — output waveform or EMI/ground coupling?
First capture Vout distortion/step response and correlate dropouts with event timing (fan/ATS/inverter transitions). If dropouts track Vout ripple/warping, it is output quality or limiting; if Vout looks clean but issues align to switching events, suspect coupling paths. First fixes: improve output transient filtering and tame dv/dt at transitions (UCC21520, MOC3063, 744826101).
7) “One overload locks it out and it won’t recover” — protection policy or thermal derating?
Read the event window for action=lockout, retry_count, and compare with T_hot/derate_level. If lockout happens with low temperature and no retries, it is a policy/latched fault design; if derate rises first, it is thermal-driven. First fixes: add staged overload timers and explicit recovery criteria, and log the reason (MAX31760, TPS2660, FM24CL64B).
8) “Some power strips / RCDs trip falsely” — leakage current or dv/dt-triggered switching artifact?
Measure leakage current (steady-state) and observe whether trips correlate with transfer edges (dv/dt spikes). Steady leakage points to Y-cap/SSR leakage paths; edge-correlated trips point to dv/dt artifacts during switching. First fixes: reduce/redistribute leakage paths and slow edge energy with snubbers; consider low-leakage PhotoMOS for control paths (AQH3213A, MOC3063).
9) “Light-load runtime is exaggerated” — metering zero drift or self-consumption too high?
Compare Ipack zero at near-no-load and the difference Ppack − Pout in battery mode. A drifting zero (especially with temperature) indicates metering offset; a large Ppack − Pout indicates self-consumption or poor light-load efficiency. First fixes: apply two-point calibration with temp bins and reduce always-on rails using low-Iq converters (INA240A1, MAX17055, TPS62740).
10) “After repeated plug/unplug, charging breaks” — inrush/hot-start or latched fault code?
Capture inrush peak (Vbus + current) on hot-start and check whether the last event shows a latched fault_code with no recovery. If inrush spikes grow after rapid re-plug, it is an inrush/thermal-start issue; if spikes are normal but faults remain, it is lockout policy. First fixes: stabilize inrush and store lockout context for debugging (TPS25940, V14E275, FM24CL64B).
11) “The fan is loud even at low power” — wrong hotspot sensing or wrong control policy?
Correlate T_hot with derate_level and compare to T_amb at the intake. If T_hot is inconsistent (jumps or disagrees with other points), sensing/placement/noise injection is likely; if T_hot rises smoothly with poor airflow, policy is reacting correctly. First fixes: re-anchor the hotspot sensor and implement a logged fan curve with hysteresis (NCP18XH103, TMP117, MAX31760).
12) “How can logs prove battery aging (not inverter failure)?”
Use a fixed test load and trend ΔVpack@step and estimated internal resistance (if available) while verifying that Vout quality stays stable. Rising sag/ESR with stable Vout indicates battery aging; worsening Vout distortion under the same Vpack suggests inverter/control issues. First fixes: log consistent step tests and store health metrics for comparison across months (MAX17055, INA240A1, MCP7940N).
Figure H2-12 — FAQ coverage map (questions → evidence chains → chapters)
Keep every FAQ inside this page’s measurable evidence chain. Cite this figure ID SHA-UPS-F12
