Smart Utility Meters (Home): Metering AFE, RTC, Anti-Tamper, PLC
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A home smart utility meter is a metrology + security evidence recorder: it must measure energy accurately, survive outages without losing time/log continuity, and produce tamper-proof event records that explain “what happened” on the wire and in the power rails.
This page focuses on the full on-device evidence chain—metering signal path → RTC/time-stamp → atomic log → tamper sensing → PLC/RF physical evidence → brownout/hold-up priority—so field issues can be isolated with minimal tools and fixed without scope creep.
H2-1. Page Center Idea
A home utility meter is a metrology + security evidence recorder: it must measure accurately, survive outages without losing truth, and prove tamper attempts with time-stamped, logged events.
This topic is organized as an evidence chain: measure → time-stamp → seal → deliver. Each chapter pins down what must be observable (two or three minimum checks) before proposing fixes or BOM choices.
What “done right” looks like (engineering anchors)
- Accuracy: gain/phase/temp drift controlled across low-to-high load; harmonics and crest factor do not break accumulation; calibration points are traceable and versioned.
- Power hold-up: brownout is detected early; logs commit atomically; RTC remains monotonic; readings do not repeat or roll back after recovery.
- Tamper evidence: common fraud attempts (magnet, bypass, reverse current, cover open, neutral missing) map to specific sensors/rules; events are time-stamped and integrity-protected.
- Connectivity: PLC/RF failures are explained by measurable counters (retry/fail codes) and analog evidence (TX current vs rail droop, SNR/RSSI trends), not by guesswork.
H2-2. System Boundary & What’s Inside a Home Utility Meter
This topic focuses on the meter body as a sealed instrument: sensing, metrology, time, secure logging, tamper evidence, communications, and power survival. The goal is not “smart home networking”; the goal is measurable truth that remains consistent under outages and adversarial conditions.
In scope (what this page goes deep on)
- Metrology chain: V/I (or flow) sensing → ADC → accumulation (energy/volume) with controlled error sources.
- Data integrity chain: RTC time base + atomic event/data logging in NVM (no rollbacks, no silent gaps).
- Anti-tamper chain: sensors + rule logic + sealed events (what happened, when, and why it is credible).
- Comms evidence: PLC/RF link stability explained via measurable counters and analog evidence (retry/fail codes, SNR/RSSI, TX current vs rail droop).
- Power survival: brownout detection + hold-up strategy that prioritizes RTC + log truth over best-effort reporting.
Out of scope (explicitly not covered here)
- HEMS panel and branch switching architecture, solar/storage interfaces, and whole-home energy orchestration.
- Matter/home gateway deep dive, router setup tutorials, and cloud/MDMS backend system design.
- Protocol-stack deep dives and step-by-step certification procedures.
The “Truth Chain” mental model (what the meter must produce)
The meter must output two types of artifacts that can be verified independently:
- Metering truth: accumulated energy/volume and supporting observables (RMS, PF, phase, diagnostics) that explain why a reading is correct.
- Evidence truth: time-stamped events and monotonic counters that prove continuity through outages and record tamper attempts with integrity protection.
| Chain segment | What it must output | What can break it | Minimum checks |
|---|---|---|---|
| Metrology | Accumulators (kWh/Wh or volume), RMS, PF/phase diagnostics | Phase error, temp drift, shunt self-heat, CT saturation, leakage paths | V/I waveforms + accumulator consistency (pulse/register) |
| Time base | Monotonic timestamps; bounded drift over temperature/outage | XO drift, holdover supply collapse, reset loops | RTC continuity + drift check vs known reference |
| Secure log | Atomic records with sequence counters + CRC/signature | Brownout mid-write, wear-out, rollback after crash | Commit flag + seq continuity across power cycles |
| Tamper | Typed events (magnet/cover/bypass/reverse/neutral-missing) | Sensor saturation, weak thresholds, missing correlation rules | Sensor raw + rule decision + event record presence |
| Comms | Retry/fail codes; link quality metrics; delivery success rate | Noise/impedance change, duty-cycle limits, TX current droop resets | Retry counters + TX current pulse + rail droop correlation |
| Power | Prioritized survival: RTC+log preserved; graceful degradation | Poor brownout thresholding, insufficient hold-up, POR chatter | BOD/POR timing + hold-up energy + commit success rate |
H2-3. Metering Signal Chain (Voltage & Current Sensing → ADC → DSP)
The metering chain is only as accurate as its phase alignment, gain integrity, and reference stability under real loads. This chapter maps each major error injection point to a measurable observable, so troubleshooting starts from evidence rather than assumptions.
Voltage sensing: divider, RC, protection (and where error enters)
- Divider ratio drift: tolerance and TCR translate directly into energy scaling error; high-value dividers also magnify leakage sensitivity.
- Leakage paths: clamp/ESD device leakage, PCB contamination, and humidity can bias the divider node and shift readings, especially at low current/low power.
- RC phase shift: front-end filtering changes phase at 50/60 Hz and harmonics; phase error directly impacts P/Q and PF.
- Clamp behavior: protection conduction during spikes can distort the waveform and inflate harmonic metrics or distort instantaneous power.
Minimum verification: (1) two-point linearity check against a reference at low/high input; (2) phase sanity check using a known PF load or controlled phase shift network.
Current sensing choices: Shunt vs CT vs Rogowski (selection → predictable error modes)
| Option | Why it is chosen | Most common error injections | Minimum verification |
|---|---|---|---|
| Shunt | High linearity; strong low-current fidelity; simple BOM | Self-heating drift, Kelvin routing sensitivity, EMI pickup, amplifier offset dominates at low current | Step-load run: observe drift vs time and temperature rise |
| CT | Isolation-friendly; low insertion loss; robust at high current | Phase error vs load and frequency, saturation, external magnetic influence, burden tolerance | Phase sweep at multiple currents + pre-saturation waveform check |
| Rogowski | Wide dynamic range; no saturation; good for high-current transients | Integrator drift/offset, low-frequency accuracy limitations, installation repeatability | Integrator baseline stability + phase consistency check |
ADC & reference: ΣΔ vs SAR (metering-focused)
- ΣΔ ADC: excels for low-frequency precision and dynamic range; accuracy depends on reference integrity and decimation settings that preserve phase alignment.
- SAR ADC: can work when sampling alignment is tightly controlled; performance hinges on reference settling, sampling jitter, and front-end anti-alias behavior.
- Reference integrity: reference noise or droop becomes a direct scaling error; supply coupling can appear as “mysterious drift” in accumulation.
- Channel alignment: V and I sample misalignment shows up as PF/P/Q instability even when RMS looks stable.
Digital metrology outputs: interpret symptoms without turning into a textbook
- PF instability: often indicates phase error (sensor phase, RC phase, or sampling alignment) rather than pure gain drift.
- RMS stable but kWh off: suggests scaling/accumulation coefficient issues, range switching discontinuity, or reference coupling into the accumulator path.
- Harmonics inflate: commonly caused by clamp conduction, front-end saturation, or anti-alias misconfiguration under real-world spikes.
- Low-load inaccuracy: points to leakage/offset/quantization dominance; this is where divider leakage and amplifier offset become visible.
H2-4. Accuracy & Calibration Strategy (Factory + In-field)
Accuracy is not a single calibration step; it is a closed loop that produces traceable coefficients, stores them with rollback protection, and continuously checks that the metering chain behaves like the calibrated model under real conditions.
Factory calibration: what must be produced (not just “performed”)
- Gain/offset set: multi-point coefficients with residual error recorded as a quality stamp.
- Phase compensation: V/I phase parameters verified under representative load conditions.
- Temperature compensation: coefficient sets or segments tied to temperature points, with a clear version identifier.
Factory artifacts to keep: coefficient version, calibration temperature point(s), residual error stamp, and a monotonic update counter (for anti-rollback).
In-field verification: minimal checks that keep results credible
- Known-load check: compare readings at a small set of anchor points (low / mid / high) to detect non-linearity and drift patterns.
- Pulse/register consistency: if an energy pulse output exists, verify pulse-count vs accumulator consistency over a fixed time window.
- Time consistency: confirm RTC monotonic behavior across power cycles; time rollback often explains duplicated or missing records.
Drift sources: link each cause to an observable
- Temperature drift: error changes monotonically or in segments; segment behavior suggests model mismatch.
- Self-heating: step-load produces a slow drift curve over minutes (common with shunt paths).
- Magnetic influence: abnormal behavior appears under external field exposure (sensing-specific signature).
- Supply/reference coupling: errors correlate with rail ripple or reference droop during bursts or noisy intervals.
Trusted coefficient storage (no cloud dependency)
- Atomic update: dual-copy or commit-flag update to avoid half-written coefficient sets.
- Anti-rollback: monotonic counter and version binding prevent old coefficient sets from being restored silently.
- Integrity check: CRC or signature (optional SE support) ensures coefficients are not tampered with.
- Audit trail: every coefficient update writes a time-stamped event into the secure log.
H2-3. Metering Signal Chain (Voltage & Current Sensing → ADC → DSP)
The metering chain is only as accurate as its phase alignment, gain integrity, and reference stability under real loads. This chapter maps each major error injection point to a measurable observable, so troubleshooting starts from evidence rather than assumptions.
Voltage sensing: divider, RC, protection (and where error enters)
- Divider ratio drift: tolerance and TCR translate directly into energy scaling error; high-value dividers also magnify leakage sensitivity.
- Leakage paths: clamp/ESD device leakage, PCB contamination, and humidity can bias the divider node and shift readings, especially at low current/low power.
- RC phase shift: front-end filtering changes phase at 50/60 Hz and harmonics; phase error directly impacts P/Q and PF.
- Clamp behavior: protection conduction during spikes can distort the waveform and inflate harmonic metrics or distort instantaneous power.
Minimum verification: (1) two-point linearity check against a reference at low/high input; (2) phase sanity check using a known PF load or controlled phase shift network.
Current sensing choices: Shunt vs CT vs Rogowski (selection → predictable error modes)
| Option | Why it is chosen | Most common error injections | Minimum verification |
|---|---|---|---|
| Shunt | High linearity; strong low-current fidelity; simple BOM | Self-heating drift, Kelvin routing sensitivity, EMI pickup, amplifier offset dominates at low current | Step-load run: observe drift vs time and temperature rise |
| CT | Isolation-friendly; low insertion loss; robust at high current | Phase error vs load and frequency, saturation, external magnetic influence, burden tolerance | Phase sweep at multiple currents + pre-saturation waveform check |
| Rogowski | Wide dynamic range; no saturation; good for high-current transients | Integrator drift/offset, low-frequency accuracy limitations, installation repeatability | Integrator baseline stability + phase consistency check |
ADC & reference: ΣΔ vs SAR (metering-focused)
- ΣΔ ADC: excels for low-frequency precision and dynamic range; accuracy depends on reference integrity and decimation settings that preserve phase alignment.
- SAR ADC: can work when sampling alignment is tightly controlled; performance hinges on reference settling, sampling jitter, and front-end anti-alias behavior.
- Reference integrity: reference noise or droop becomes a direct scaling error; supply coupling can appear as “mysterious drift” in accumulation.
- Channel alignment: V and I sample misalignment shows up as PF/P/Q instability even when RMS looks stable.
Digital metrology outputs: interpret symptoms without turning into a textbook
- PF instability: often indicates phase error (sensor phase, RC phase, or sampling alignment) rather than pure gain drift.
- RMS stable but kWh off: suggests scaling/accumulation coefficient issues, range switching discontinuity, or reference coupling into the accumulator path.
- Harmonics inflate: commonly caused by clamp conduction, front-end saturation, or anti-alias misconfiguration under real-world spikes.
- Low-load inaccuracy: points to leakage/offset/quantization dominance; this is where divider leakage and amplifier offset become visible.
H2-4. Accuracy & Calibration Strategy (Factory + In-field)
Accuracy is not a single calibration step; it is a closed loop that produces traceable coefficients, stores them with rollback protection, and continuously checks that the metering chain behaves like the calibrated model under real conditions.
Factory calibration: what must be produced (not just “performed”)
- Gain/offset set: multi-point coefficients with residual error recorded as a quality stamp.
- Phase compensation: V/I phase parameters verified under representative load conditions.
- Temperature compensation: coefficient sets or segments tied to temperature points, with a clear version identifier.
Factory artifacts to keep: coefficient version, calibration temperature point(s), residual error stamp, and a monotonic update counter (for anti-rollback).
In-field verification: minimal checks that keep results credible
- Known-load check: compare readings at a small set of anchor points (low / mid / high) to detect non-linearity and drift patterns.
- Pulse/register consistency: if an energy pulse output exists, verify pulse-count vs accumulator consistency over a fixed time window.
- Time consistency: confirm RTC monotonic behavior across power cycles; time rollback often explains duplicated or missing records.
Drift sources: link each cause to an observable
- Temperature drift: error changes monotonically or in segments; segment behavior suggests model mismatch.
- Self-heating: step-load produces a slow drift curve over minutes (common with shunt paths).
- Magnetic influence: abnormal behavior appears under external field exposure (sensing-specific signature).
- Supply/reference coupling: errors correlate with rail ripple or reference droop during bursts or noisy intervals.
Trusted coefficient storage (no cloud dependency)
- Atomic update: dual-copy or commit-flag update to avoid half-written coefficient sets.
- Anti-rollback: monotonic counter and version binding prevent old coefficient sets from being restored silently.
- Integrity check: CRC or signature (optional SE support) ensures coefficients are not tampered with.
- Audit trail: every coefficient update writes a time-stamped event into the secure log.
H2-3. Metering Signal Chain (Voltage & Current Sensing → ADC → DSP)
The metering chain is only as accurate as its phase alignment, gain integrity, and reference stability under real loads. This chapter maps each major error injection point to a measurable observable, so troubleshooting starts from evidence rather than assumptions.
Voltage sensing: divider, RC, protection (and where error enters)
- Divider ratio drift: tolerance and TCR translate directly into energy scaling error; high-value dividers also magnify leakage sensitivity.
- Leakage paths: clamp/ESD device leakage, PCB contamination, and humidity can bias the divider node and shift readings, especially at low current/low power.
- RC phase shift: front-end filtering changes phase at 50/60 Hz and harmonics; phase error directly impacts P/Q and PF.
- Clamp behavior: protection conduction during spikes can distort the waveform and inflate harmonic metrics or distort instantaneous power.
Minimum verification: (1) two-point linearity check against a reference at low/high input; (2) phase sanity check using a known PF load or controlled phase shift network.
Current sensing choices: Shunt vs CT vs Rogowski (selection → predictable error modes)
| Option | Why it is chosen | Most common error injections | Minimum verification |
|---|---|---|---|
| Shunt | High linearity; strong low-current fidelity; simple BOM | Self-heating drift, Kelvin routing sensitivity, EMI pickup, amplifier offset dominates at low current | Step-load run: observe drift vs time and temperature rise |
| CT | Isolation-friendly; low insertion loss; robust at high current | Phase error vs load and frequency, saturation, external magnetic influence, burden tolerance | Phase sweep at multiple currents + pre-saturation waveform check |
| Rogowski | Wide dynamic range; no saturation; good for high-current transients | Integrator drift/offset, low-frequency accuracy limitations, installation repeatability | Integrator baseline stability + phase consistency check |
ADC & reference: ΣΔ vs SAR (metering-focused)
- ΣΔ ADC: excels for low-frequency precision and dynamic range; accuracy depends on reference integrity and decimation settings that preserve phase alignment.
- SAR ADC: can work when sampling alignment is tightly controlled; performance hinges on reference settling, sampling jitter, and front-end anti-alias behavior.
- Reference integrity: reference noise or droop becomes a direct scaling error; supply coupling can appear as “mysterious drift” in accumulation.
- Channel alignment: V and I sample misalignment shows up as PF/P/Q instability even when RMS looks stable.
Digital metrology outputs: interpret symptoms without turning into a textbook
- PF instability: often indicates phase error (sensor phase, RC phase, or sampling alignment) rather than pure gain drift.
- RMS stable but kWh off: suggests scaling/accumulation coefficient issues, range switching discontinuity, or reference coupling into the accumulator path.
- Harmonics inflate: commonly caused by clamp conduction, front-end saturation, or anti-alias misconfiguration under real-world spikes.
- Low-load inaccuracy: points to leakage/offset/quantization dominance; this is where divider leakage and amplifier offset become visible.
H2-4. Accuracy & Calibration Strategy (Factory + In-field)
Accuracy is not a single calibration step; it is a closed loop that produces traceable coefficients, stores them with rollback protection, and continuously checks that the metering chain behaves like the calibrated model under real conditions.
Factory calibration: what must be produced (not just “performed”)
- Gain/offset set: multi-point coefficients with residual error recorded as a quality stamp.
- Phase compensation: V/I phase parameters verified under representative load conditions.
- Temperature compensation: coefficient sets or segments tied to temperature points, with a clear version identifier.
Factory artifacts to keep: coefficient version, calibration temperature point(s), residual error stamp, and a monotonic update counter (for anti-rollback).
In-field verification: minimal checks that keep results credible
- Known-load check: compare readings at a small set of anchor points (low / mid / high) to detect non-linearity and drift patterns.
- Pulse/register consistency: if an energy pulse output exists, verify pulse-count vs accumulator consistency over a fixed time window.
- Time consistency: confirm RTC monotonic behavior across power cycles; time rollback often explains duplicated or missing records.
Drift sources: link each cause to an observable
- Temperature drift: error changes monotonically or in segments; segment behavior suggests model mismatch.
- Self-heating: step-load produces a slow drift curve over minutes (common with shunt paths).
- Magnetic influence: abnormal behavior appears under external field exposure (sensing-specific signature).
- Supply/reference coupling: errors correlate with rail ripple or reference droop during bursts or noisy intervals.
Trusted coefficient storage (no cloud dependency)
- Atomic update: dual-copy or commit-flag update to avoid half-written coefficient sets.
- Anti-rollback: monotonic counter and version binding prevent old coefficient sets from being restored silently.
- Integrity check: CRC or signature (optional SE support) ensures coefficients are not tampered with.
- Audit trail: every coefficient update writes a time-stamped event into the secure log.
H2-5. RTC, Time-Stamping & Data Retention Under Outage
Outage robustness is not just “keeping data.” A home meter must preserve a continuous truth chain: a record stream that can prove no gaps, no edits, and no replay across brownouts and repeated flickers.
RTC architecture: time base, drift, and holdover rails
- Time source: XO/RTC time base stability sets long-outage behavior; drift must be measurable and compensable.
- Temperature drift: the key question is whether drift is predictable (model/segment) or erratic (supply or rail collapse).
- Holdover supply: battery/supercap/keep-alive rail must survive the transition moment when main rails cross BOD thresholds.
Minimum verification: (1) verify RTC never rolls back across power cycles; (2) measure drift vs temperature; (3) scope the holdover rail during the main-rail fall-through of BOD.
Outage modes: brownout, long outage, and repeated flicker
- Brownout: the most dangerous mode—firmware may continue running while storage writes become unreliable (half-written records).
- Long outage: priority is RTC holdover and a restart path that can prove record continuity.
- Flicker (chattering): frequent resets can destroy endurance and create duplicated/partial logs unless commit rules are strict.
Data retention media & write strategy (ring log + atomic commit)
| Medium | Strength | Typical risks | Best-fit logging |
|---|---|---|---|
| FRAM | Fast writes, high endurance; favorable for frequent events | Capacity and cost constraints | Ring log with per-record CRC |
| Flash | High density, low cost | Erase/write latency, wear under flicker storms | Buffered commit + wear-aware ring |
| EEPROM | Simple, moderate endurance | Limited throughput; still sensitive to half-writes | Small critical records + strict commit flag |
Evidence chain: prove “no loss, no edit, no replay”
- Sequence counter: proves continuity (missing numbers imply gaps or reorder).
- CRC / signature: proves record integrity (edits become detectable).
- Monotonic time: detects rollback and replay; time and sequence anchor each other.
- Atomic commit: guarantees “complete record or none,” preventing half-written evidence.
H2-6. Anti-Tamper Threat Model (Home Meter Reality)
Anti-tamper is not “add a security chip.” A practical home meter design starts from an enumerable threat list and turns each threat into observable evidence that can be recorded as a time-stamped, integrity-checked event.
Threat-to-evidence mapping (engineering closure)
| Threat | Observable evidence | Sensor / logic | Logged event | Min proof |
|---|---|---|---|---|
| Magnet | B-field high + PF/phase anomaly aligned in time | Hall + correlation to metrology flags | MAG_TAMPER | >X s |
| Neutral missing | Impossible V/I relationship; abnormal sign patterns | V/I consistency check + time gate | NEUTRAL_MISS | >Y s |
| Reverse current | Energy sign flips beyond expected transient behavior | Direction logic + hysteresis | REV_CURRENT | >Y s |
| Cover open | Cover switch edge with debounced duration | Switch/optical + debounce | COVER_OPEN | edge |
| Bypass/loose | Voltage present with abnormal current consistency | Consistency + rate-of-change guard | BYPASS_SUS | >Z s |
| Signal inject | Non-physical metric combination (RMS/PF/harmonics) | Multi-metric plausibility rules | INJECT_SUS | rules |
| FW rollback | Version counter mismatch / boot verify fail | Anti-rollback counter + boot check | FW_ROLLBACK | 1x |
Logged event should include: type, start/end (or duration), time stamp, sequence counter, small metric snapshot (e.g., PF flag), and CRC/signature with atomic commit.
False-positive control (so tamper evidence stays credible)
- Debounce & hysteresis: prevent mechanical chatter or noise from flooding logs.
- Correlation gates: require at least one supporting metrology anomaly for high-impact claims (e.g., magnet).
- Time windows: separate short transient phenomena from sustained tamper attempts.
H2-7. Tamper Sensing & Evidence Logging (Make It Court-Proof)
A tamper subsystem is only useful when it produces repeatable, integrity-checked evidence. The goal is a closed chain: detect → reduce false positives → record atomically → prove continuity → reproduce the trigger.
Sensing methods (evidence anchors, not a parts list)
- Magnetic (Hall/AMR): thresholded B-field becomes credible when aligned with metrology flags (phase/PF consistency anomalies).
- Cover / terminal: a debounced edge plus duration is stronger evidence than raw switch chatter.
- V/I consistency: “physically impossible combinations” (RMS/PF/phase relationships) form robust injection/bypass indicators.
- Vibration (brief): use as a supporting signal (time-aligned) rather than a sole trigger.
Rule engine: thresholds + combinations to control false positives
- Time gates: require sustained evidence (duration > X s) to avoid transient noise triggers.
- Correlation gates: require at least one supporting observable for high-impact claims (e.g., magnet + PF anomaly).
- Hysteresis: avoid repeated triggers near thresholds under flicker/noise conditions.
- Cross-check rules: combine cover/terminal state with metrology consistency to raise event level.
Event record schema (what must be logged to stay credible)
| Layer | Fields | Why it matters |
|---|---|---|
| Header | event type, level, start/end (or duration), sequence counter | enables continuity checks and severity handling |
| Evidence snapshot | minimal metrics (e.g., PF/phase flag), minimal sensor peaks (e.g., B-field) | supports reproduction and forensic comparison |
| Integrity | CRC + signature (or authentication), atomic commit flag | detects edits and prevents half-written “fake” evidence |
Anti-rollback & log continuity (concept-level, implementation-safe)
- Firmware version counter: monotonic counter prevents “load older rules” to silence detection.
- Log link field (hash-chain concept): each record references the prior record’s digest so deletion/insertion becomes detectable.
- Chain-break handling: a broken link is itself an event that must be logged and integrity-checked.
Minimum verification: (1) inject near-threshold disturbances to validate hysteresis/time gates; (2) force mid-write power loss to ensure atomic events; (3) simulate rollback/chain break and verify detection + logged evidence.
H2-8. Security Building Blocks (Secure Boot, Keys, Secure Element)
The meter-side security chain protects three assets: firmware integrity, key confidentiality, and tamper/reading authenticity. The design must also respect low-power windows and outage risks so security actions do not create partial states.
Secure boot (prevent modified firmware from running)
- Verify before execute: boot stage checks the image before application code is trusted.
- Fail behavior is evidence: verification failure should enter a safe mode and create an integrity event record.
- Outage interaction: verification and log sealing must not be interrupted without a detectable state.
Key storage: MCU internal security vs external Secure Element / TPM
| Option | Strength | Typical constraints | Best fit |
|---|---|---|---|
| MCU internal secure zone | lowest BOM, lower latency, easier low-power scheduling | physical extraction resistance varies by MCU family | lower risk / no remote updates |
| External SE / TPM | stronger key isolation; better anti-tamper key handling | extra power/latency window; interface robustness under outages | remote updates / higher fraud risk |
Signing & authentication (make logs/readings verifiable)
- Event logs: signatures/verification tags allow detection of edits after data leaves the meter.
- Reading summaries: sign periodic summaries (sequence-anchored) so replay and modification become detectable.
- Minimal scope: focus on meter-side authenticity; backend architecture is out of scope.
Security vs power: schedule cryptographic windows safely
- Wake budget: restrict key operations to controlled windows to avoid repeated high-energy actions.
- Power-fail gating: do not start signing when PF detect indicates insufficient time to commit.
- Atomic outcomes: security operations should end in “done” or “not started,” never “half applied.”
Decision card — Is an external SE needed?
Prefer SE: remote updates exist, high anti-fraud requirements, stronger physical key protection needed.
MCU may suffice: no remote updates, lower risk, ultra-low-power priority with short security windows.
H2-9. Communication Options: PLC vs RF (and What to Measure First)
This chapter stays out of protocol-stack details and focuses on why readouts drop or links become unstable. The fastest path is to capture three aligned evidence points and decide whether the failure is driven by the medium (PLC noise / RF environment) or by power & scheduling (TX peaks causing rail droop and retries).
First 3 measurements (triage in minutes)
- Rail droop: measure the main rail or the comm rail during transmit bursts and during heavy retries.
- Retry counter / fail reason: record retries, ACK failures, or a link-quality indicator from the module/stack.
- TX current: capture peak current and timing; align it with retry spikes and timestamp gaps.
PLC (power-line carrier): unstable links are often noise + coupling + impedance changes
- Noise bursts: switching events and appliance activity can cluster errors in repeatable time windows.
- Impedance changes: plug/unplug events and loads on the same branch can shift channel characteristics.
- Near zero-cross interference: certain disturbances concentrate around the AC waveform crossing, creating retry bursts.
Sub-GHz / RF mesh: judge link budget and retry pressure (not routing theory)
- RSSI/SNR: indicates whether the channel margin is fundamentally sufficient.
- Retransmit counts: shows whether reliability is achieved via excessive retries.
- Duty-cycle limits: rate limiting can look like “missing reads” when the system must back off.
NB-IoT (light mention): what it changes in the evidence chain
- Peak TX current: can be the dominant rail droop trigger if power gating is not aligned.
- Uplink latency: extends active time and increases the probability of outage overlap.
- Retries: multiply both energy cost and the need for clean time/sequence logging.
Fast triage rule: if retry spikes align with rail droop during TX, treat power / scheduling first. If rails stay stable but link metrics collapse (PLC noise indicator or RF SNR), treat the medium and coupling first.
H2-10. Power Architecture & Low-Power Operation (Meter Must Never Lose Truth)
The hardest power requirement is not “never reset.” It is never losing truth: even under edge rails, the system must preserve time, sequence continuity, and atomic logs. The power tree and low-power policy should therefore protect the truth rails first, then restore communications after integrity is secured.
Typical power-tree shapes (home meters vs battery meters)
- Mains-powered (electricity meter): AC/DC front end → main rail → branches (MCU, metrology AFE, comm, display).
- Battery/harvesting (water/gas meters): primary cell/harvester → ultra-low-power rail → gated high-power rail for TX / actuators.
- Truth rails: RTC + secure log + minimal MCU must remain valid through PF detect and commit windows.
Peak loads that most often corrupt evidence (if not gated)
- TX bursts: RF / NB-IoT / PLC activity can create droop and force retries.
- Actuators (if present): relay/valve pulses can overlap log commits.
- Backlight/indicators: small loads can become critical when rails are already marginal.
- NVM commits: the write/verify window is the most sensitive moment for integrity.
Brownout policy: degrade in levels, preserve truth first
| Level | Action | Protected outcome |
|---|---|---|
| Normal | full operation | all functions available |
| PF detect | freeze TX/start of heavy operations; prepare commit | avoid half operations under shrinking rail |
| Commit-only | keep RTC + log; seal event and stop non-critical rails | atomic evidence preserved |
| Resume | scan last record; verify continuity; then restore comm | no gaps/duplicates in truth chain |
Verification: three acceptance metrics (hard to fake)
- Rail droop under pulses: capture worst-case sag during TX and during retries.
- POR/BOD threshold alignment: ensure thresholds leave a usable commit window.
- Commit success rate: under repeated flicker/pulses, verify no half-writes, no sequence gaps, and no chain breaks.
Minimum verification: (1) pulse TX and measure rail droop; (2) induce brownout while forcing a log commit; (3) repeat flicker cycles and audit time/seq continuity + commit success rate.
H2-11. Validation & Field Debug Playbook (Symptom → Evidence → Isolate → Fix)
This playbook turns field issues into repeatable steps using minimal tools. Each case follows a fixed pattern: First 2 checks → Discriminator → First fix → Prevent. The goal is not “never reset”; the goal is never losing truth: time, sequence continuity, and atomic evidence stay trustworthy through outages and attacks.
Field record template: timestamp • seq • event_id • rail_min • tx_I_peak • retry_count • chain_status
Case 1 Meter reads high/low only in certain power bands metrology evidence
First 2 checks
- Capture V/I sampling evidence: RMS level and a phase indicator (even a coarse phase flag is useful).
- Read range / gain-state flags from the metrology engine (range switching often correlates with band-limited errors).
Discriminator (one-shot decision)
- Error only at light load → prioritize noise floor, gain switching hysteresis, and ADC linearity around zero.
- Error only at low PF / inductive loads → prioritize phase error (sensor phase, filters, group delay).
First fix (fastest change that moves the needle)
- Add hysteresis to range switching; lock gain during measurement windows used for billing accumulation.
- Introduce phase compensation using a known PF load point; store a calibration version alongside the coefficients.
Prevent (design-stage guardrails)
- Factory calibration must include: light-load point + low-PF point + temperature sweep anchor.
- Log “calibration set id” and “metrology firmware id” at each seal event.
Example MPN anchors (meter-side metrology):
ADI ADE9153A (single-phase metering SoC), ADI ADE7913 (isolated ADC for current/voltage),
ST STPM32/STPM33 (metering), TI MSP430i2041 (energy metering MCU family, use-case dependent).
Case 2 Reading jumps / rolls back after outage or flicker time + atomic log
First 2 checks
- Align PF detect / brownout flags with the RTC timestamp around the incident window.
- Audit sequence counter continuity and the last “commit state” (detect half-writes or missing seals).
Discriminator
- Seq gap + time rollback → suspect RTC holdover or monotonic-time chain logic.
- CRC/chain fail near outage → suspect commit window too short or power sag too steep during NVM write.
First fix
- Trigger PF detect earlier; freeze TX; perform a minimal seal commit before rails collapse.
- Use a two-step atomic commit (data write → valid marker) and log a “chain-break” event if needed.
Prevent
- Validation must include repeated flicker cycles with a measured metric: commit success rate must stay at 100%.
- Truth rails (RTC + log) must be power-isolated from TX peaks via gating policy.
Example MPN anchors (RTC / retention):
Micro Crystal RV-3032-C7 (ultra-low-power RTC), Maxim/ADI DS3231 (TCXO RTC),
NXP PCF8563 (basic RTC, use-case dependent).
FRAM examples: Infineon/Cypress FM24CL64B, Fujitsu MB85RC256V.
Supervisor/PF detect examples: TI TPS3839, Microchip MCP1316, TI comparator TLV3691.
Case 3 PLC/RF drops at certain hours (bursty retries) medium vs power
First 2 checks
- Record retry counter + fail code and a link quality metric (PLC noise indicator or RF RSSI/SNR).
- Capture TX peak current and rail droop in the same time window.
Discriminator
- Retry spike aligns with rail droop → power / scheduling first (TX bursts are collapsing rails).
- Rails stable but link metric collapses → medium first (PLC noise/coupling or RF environment).
First fix
- Power-driven: freeze display/backlight and block TX when PF detect indicates shrinking margin; cap retries.
- Medium-driven: shift send window; log “quality + retry + time/seq” so failures can be reproduced by time correlation.
Prevent
- Log must include per-failure: fail_code + retry_count + rail_min + timestamp.
- Validation should sweep: load switching, time-of-day interference patterns, and worst-case TX duty bursts.
Example MPN anchors (PLC / RF):
PLC modems: Microchip ATPL360 (G3-PLC), ST ST8500 (PLC modem family).
Sub-GHz/radio SoCs: TI CC1312R/CC1352P, Silicon Labs EFR32FG23.
NB-IoT modules (if used): u-blox SARA-R410M, Quectel BG95, Nordic nRF9160.
Case 4 False tamper alarms in winter / high temperature threshold + correlation
First 2 checks
- Identify the trigger source: magnetic, cover, or V/I consistency.
- Align triggers with temperature and rail voltage around the event window.
Discriminator
- Events cluster with temperature ramps → missing temperature compensation or insufficient hysteresis/debounce.
- Events cluster with low rail conditions → metrology consistency checks are being fed unstable data.
First fix
- Use temperature-segmented thresholds; add time gate + hysteresis; require a second evidence anchor for “high severity”.
- When rails are marginal, downgrade evidence level rather than claiming strong tamper.
Prevent
- Validation metric: false-positive rate under temperature corners + low rail corners must stay below target.
- Event log must capture minimal evidence snapshot (peak magnetic level or consistency flag) for reproducibility.
Example MPN anchors (tamper sensors):
Hall sensors: TI DRV5055 (linear Hall), Allegro A1324 (linear Hall family).
Secure element for event authenticity: Microchip ATECC608B, NXP SE050, Infineon OPTIGA Trust M.
Case 5 After update: metering shifts or log chain breaks version + anti-rollback
First 2 checks
- Read firmware version counter and calibration set id from the log near the update window.
- Check chain status / CRC failures and whether failures align with outage or reset markers.
Discriminator
- Calibration set mismatch → compensation tables / phase settings changed or not migrated.
- Rollback signs → monotonic counter not enforced or update executed in unsafe power window.
First fix
- Log an “update event” that includes firmware id + calibration id; block updates when PF detect indicates risk.
- On boot, verify last record continuity; if broken, record a chain-break event and enter integrity-safe mode.
Prevent
- Update validation must include forced brownout during update; post-update audit must confirm time/seq continuity.
- Anti-rollback requires a monotonic counter stored in secure storage (MCU secure zone or SE).
Example MPN anchors (secure boot / keys):
MCU families commonly paired with secure elements (implementation-specific): STM32 + SE, NXP MCUs + SE.
Secure elements: Microchip ATECC608B, NXP SE050, Infineon OPTIGA Trust M.
Case 6 Magnet attack suspected, but no tamper record exists evidence missing
First 2 checks
- Confirm whether the magnetic channel ever crossed threshold (peak or sampled flags).
- Check for simultaneous rail events (PF detect/reset) that could interrupt logging at trigger time.
Discriminator
- Sensor trigger exists but no log → event recording path is being cut by power window or gating is too strict.
- No trigger but metering anomalies exist → sensor coverage/placement/threshold may miss real-world attack vectors.
First fix
- Use two-stage logging: write a minimal “tamper pending” marker first (very short commit), then append evidence snapshot if power allows.
- Freeze TX immediately on tamper trigger to protect commit window.
Prevent
- Magnet tests must include: orientation sweep + distance sweep + concurrent TX burst + induced flicker.
- Log must capture at least a minimal magnetic peak and sequence/time when severity ≥ threshold.
Example MPN anchors (power integrity under tamper):
Buck converters (examples): TI TPS62130, TI TPS62840 (low-IQ, use-case dependent).
TVS examples (line protection, selection depends on standards): Littelfuse SMF/SMBJ families.
Use pattern: start with the case closest to the symptom, capture the first two checks, then lock a single discriminator decision. Only after the root bucket is confirmed should a fix be applied. Every fix should add one more logged evidence field so the next incident becomes faster to isolate.
Example BOM anchors (MPNs) — meter-side building blocks
These are reference part numbers to make the playbook actionable (selection depends on region, standards, and architecture). The focus stays on metrology, retention, tamper evidence, comm evidence, and truth-first power.
| Block | Example MPNs | Why useful in this page |
|---|---|---|
| Metering SoC / AFE | ADI ADE9153A, ST STPM32/STPM33, ADI ADE7913 (isolated ADC) |
Provides measurable flags/counters and repeatable error sources (gain/phase/range) |
| RTC | Micro Crystal RV-3032-C7, Maxim/ADI DS3231, NXP PCF8563 |
Trustworthy timestamps; drift and holdover behavior can be validated and logged |
| Retention memory | Infineon FM24CL64B, Fujitsu MB85RC256V (FRAM examples) |
Atomic event logs under brownout; improves commit success rate |
| Secure element | Microchip ATECC608B, NXP SE050, Infineon OPTIGA Trust M |
Protect keys and enable signed/verified evidence without expanding backend details |
| PLC modem | Microchip ATPL360, ST ST8500 |
Link quality / noise indicators and retry/fail evidence for PLC instability triage |
| Sub-GHz radio SoC | TI CC1312R/CC1352P, Silicon Labs EFR32FG23 |
RSSI/SNR and retry counters for RF evidence chain |
| NB-IoT module (optional) | u-blox SARA-R410M, Quectel BG95, Nordic nRF9160 |
Peak TX current / latency / retries impact truth-first power policy and logs |
| Supervisor / PF detect | TI TPS3839, Microchip MCP1316, TI comparator TLV3691 |
Creates reliable commit window gating and brownout state transitions |
H2-12. FAQs ×12 (Evidence-Backed, No Scope Creep)
Each answer falls back to this page’s evidence chain only: metering, RTC & atomic log, tamper evidence, PLC/RF physical evidence, and power hold-up.
Answer structure used in every item: First 2 checks → Discriminator → First fix → (Example parts)
Q1“Accurate at low power, wrong at high power”: phase error or gain compression first?
First 2 checks: capture a phase/PF flag and the gain/range state at high load; look for sensor saturation (CT, ADC headroom) or shunt self-heating drift. Discriminator: PF-correlated error points to phase/group-delay; amplitude-only error points to compression/saturation. First fix: add range hysteresis and a high-load phase anchor. Example parts: ADI ADE9153A, ST STPM33.
Q2Same load: normal in daytime, larger error at night—PLC noise injection or divider leakage?
First 2 checks: align metering error timestamps with PLC noise/quality and retry counters; in parallel, check the voltage-sense node for DC offset drift (protection leakage, contamination). Discriminator: quality/retry spikes that time-lock to error suggest EMI injection; stable PLC metrics suggest the divider/protection path. First fix: separate TX windows from accumulation, tighten sense protection leakage. Example parts: Microchip ATPL360, TI TLV3691.
Q3After power loss readings repeat/roll back—check RTC first or atomic log commit?
First 2 checks: audit timestamp monotonicity and sequence continuity around the outage; inspect last-record “commit state” for half-writes (CRC/chain fail). Discriminator: time rollback with continuous seq points to RTC holdover/drift; seq gaps/duplicates point to atomic commit window collapse. First fix: earlier PF detect + minimal seal-before-reset, two-step commit (data→valid). Example parts: Micro Crystal RV-3032-C7, FRAM FM24CL64B.
Q4Frequent tamper alarms in low temperature—mag sensor drift or missing temp compensation?
First 2 checks: log magnetic peak/threshold margin versus temperature and rail voltage (cold-start sag can mimic “tamper”). Discriminator: events clustering near threshold imply missing hysteresis/time-gate; systematic peak shift with temperature implies sensor/placement drift. First fix: temperature-binned thresholds, debounce, and require a second evidence anchor before high severity. Example parts: Microchip ATECC608B, Allegro A1324.
Q5Communication failed, but there is no event record—why?
First 2 checks: confirm retry/fail codes exist at all; then correlate failures with PF detect and rail minimum during TX. Discriminator: retries without logs usually means the “fail hook” never commits (TX collapses the commit window) or severity gating blocks recording. First fix: write a short “fail marker” first, freeze TX, then append details. Example parts: TI TPS3839, FRAM MB85RC256V.
Q6Magnet attack suspected: energy reads lower but no tamper—what evidence is usually missing?
First 2 checks: verify magnetic channel peak/flags and the V/I consistency evidence (PF/phase anomalies) at the same time. Discriminator: metrology anomaly without magnetic evidence suggests sensor coverage/orientation gaps; magnetic triggers without logs suggest commit was interrupted by power margin. First fix: two-stage logging (“tamper pending” → evidence snapshot) and immediate TX freeze on trigger. Example parts: TI DRV5055, Infineon OPTIGA Trust M.
Q7PLC unstable only in some apartments/floors—what to measure first (not “change protocol”)?
First 2 checks: log PLC noise/quality plus retry bursts, and capture TX peak current with rail droop in the same window. Discriminator: stable rails but poor quality points to coupling/impedance changes in that wiring; droop-aligned retries point to power budgeting/gating. First fix: cap retries, shift send windows, freeze non-truth loads during TX. Example parts: ST ST8500, TI TPS62840.
Q8Crypto/signing enabled → more brownout resets: peak current or longer write window?
First 2 checks: align “sign/verify” operations with rail minimum and TX current peaks; measure whether commit duration increases (more exposure to flicker). Discriminator: droop-aligned resets indicate current peaks; stable rails but failures during extended commit indicate window stretch. First fix: move crypto to higher-margin windows and seal minimally first, then append signatures. Example parts: Microchip ATECC608B, supervisor MCP1316.
Q9Calibration data may be overwritten—how to “self-prove” using versions/counters?
First 2 checks: verify calibration set ID and a monotonic version counter inside the sealed log; audit whether versions ever roll back after reset/update. Discriminator: version rollback implies missing anti-rollback storage; monotonic versions but wrong coefficients imply non-atomic writes or slot mapping errors. First fix: dual-bank calibration with atomic switch and “cal-update” seal events. Example parts: NXP SE050, FRAM FM24CL64B.
Q10“Current is small” but accumulation is faster—offset first or sampling sync?
First 2 checks: measure zero-load offset stability across temperature and supply corners; check a phase/sync indicator (unexpected PF/phase at light load is a red flag). Discriminator: fixed bias that scales little with load points to offset/leakage injection; PF/phase anomalies point to sampling sync/group-delay. First fix: strengthen zero-point calibration and add temperature anchors; lock sync timing for accumulation windows. Example parts: ADI ADE7913, comparator TLV3691.
Q11After remote update precision drifts—parameter set issue or signal-chain hardware issue?
First 2 checks: compare sealed “metrology FW ID” and “calibration set ID” pre/post update; repeat one known-load point to see if error is global or band-limited. Discriminator: global shift suggests parameter migration; only certain PF/power bands suggest phase/range behavior in the signal chain. First fix: enforce cal migration + update event logging; block updates under PF-detect risk. Example parts: Infineon OPTIGA Trust M, RTC DS3231.
Q12Logs grow and meter reading/reporting delays—optimize NVM first or reporting strategy?
First 2 checks: time-profile “log scan/read” versus “TX retry time” per report; verify whether delay is dominated by storage traversal or medium failures. Discriminator: read-time dominated delays point to indexing/summary needs; retry-time dominated delays point to link quality and retry caps. First fix: ring log + compact index/summary; report summary first and fetch details on-demand (device-side). Example parts: FRAM MB85RC256V, RF SoC CC1312R.