Smart Air Conditioner Main Control Board Design & Debug Guide
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Smart air conditioner main control reliability comes from closing an evidence chain across the power tree, inverter drive, sensing, and Wi-Fi/BT—so every reboot, trip, drift, or drop maps to a measurable waveform and counter. This page shows how to design and debug the board with two-point measurements and spec-first IC choices, then validate fixes under real compressor and load transients.
Definition & Engineering Boundary
Featured answer: A smart air conditioner main control board coordinates power conversion, compressor/fan drive, sensor acquisition, protection, and Wi-Fi/Bluetooth connectivity while recording faults for service diagnostics. This page focuses on board-level coupling and evidence hooks (waveforms, thresholds, counters, logs) and does not cover refrigerant/mechanical design, installation steps, or cloud/app workflows.
The main control board is the system “coupling point” where high-voltage power, motor inverter switching, mixed-signal sensing, and radio modules meet. Most field failures become measurable at a small set of board nodes: HV bus ripple/droop, inverter gate/current sense signals, sensor raw codes, reset/BOR events, and connectivity counters.
Boundary
- In scope: AC input & PSU chain (PFC + LLC/flyback), inverter/gate drive/current sense, sensor AFEs, MCU reset/clock integrity, Wi-Fi/BT power & EMI coupling, protection flags, and fault/event logging.
- Out of scope: refrigerant loop/mechanics, airflow duct design, installation/commissioning guides, and appliance cloud/backend architecture.
- Not covered: router configuration, mobile app tutorials, and deep protocol-stack walkthroughs (only board-level evidence and integration constraints).
What this page delivers
- An architecture map that splits the board into six engineering chains with clear interfaces and failure shapes.
- “First evidence to capture” per chain: the two most time-saving waveforms/log counters to collect first.
- Selection checklists for the key IC classes (PFC, LLC/flyback, gate drivers/IPM, sensing, power rails, radio power).
- Board-level EMC/protection hotspots that frequently create false trips, resets, or wireless dropouts.
- A field debug SOP (symptom → evidence → isolate → first fix) that remains strictly within this board scope.
The 6-Chain Coupling Map (Interfaces → Failure Shapes → Evidence)
A smart AC main control board can be debugged and specified faster by treating it as six coupled engineering chains. Each chain has identifiable interfaces, repeatable failure shapes, and a small set of first evidence signals to capture. This map also prevents scope drift: every later chapter zooms into one chain (or one coupling point) and stays board-level.
How to use this map
When a field symptom appears (reset, false trip, dropout, sensor drift), pick the most likely chain and capture the first evidence
listed below before changing hardware or firmware settings. Evidence-first ordering avoids “guessing loops” and quickly separates
true power/drive faults from measurement or interference artifacts.
| Chain | Primary interfaces | Typical failure shapes | First evidence to capture |
|---|---|---|---|
| Power Tree | AC input → PFC → HV DC-link → LLC/flyback → 12V/5V/3V3/1Vx rails | Cold-start fails, brownout reset, burst-mode noise, random reboot under load steps | HV DC-link ripple/droop + 3V3 droop slope at reset/BOR event |
| Motor / Power | 3-phase inverter, gate driver/IPM, bootstrap supply, current sense → protection flags | Immediate trip at start, false OCP, overheating, sporadic torque/fan speed instability | Gate waveform (HS/LS) + current-sense output (raw) around trip |
| Sensing | NTC/RTD dividers, RH/pressure sensors, ADC/reference, input protection & filtering | Sensor drift/jumps, humidity/pressure “spikes”, wrong decisions triggering protection | Sensor raw codes vs rail noise (3V3/REF) + input node noise/ESD clamp activity |
| Compute | MCU/SoC core rails, reset/BOR pins, oscillator/clock, isolation boundaries | Freeze, watchdog storms, unexpected resets, intermittent misreads under EMI | Reset cause register/log + oscillator node integrity (or clock-out) during disturbances |
| Connectivity | Wi-Fi/BT module power, RF coexistence, antenna keepout, UART/SPI links | Dropout only during inverter switching, poor range, reconnect loops, pairing failures | Radio rail peak droop + reconnect/retry counters & RSSI snapshots |
| Protection & Logs | OCP/OVP/OTP comparators, relay/contactor control, fault pins, event recording | False trips, delayed response, “reset only” with no context, hard-to-reproduce faults | Fault-pin timing vs trip + event log fields (reset cause, rail min, trip type) |
Note: “First evidence” intentionally prioritizes signals that differentiate true faults from false trips caused by coupling (ground bounce, measurement noise, rail droop, or EMI).
PFC + LLC/Flyback: From “Power On” to Field-Robust
Goal Lock down resets, reboots, and performance drops using a power evidence chain: HV DC-link behavior + LV rail thresholds + reset/BOR context. The fastest diagnosis starts with two captures: DC-link minimum/ripple during load steps and the 3V3 droop slope at reset.
A smart AC main control board typically contains two power domains with very different failure signatures. The HV domain (PFC-regulated DC-link around ~380–420V) determines whether inverter startup and load transients remain inside safe margins. The LV domain (12V/5V/3V3/1Vx rails) determines whether the MCU, gate-drive logic, and radio module remain above UVLO/BOR thresholds during the same events.
HV Domain (DC-link)
Focus on ripple, load-step minimum, startup ramp, and brownout response. Many “random resets” are deterministic when the board is stressed at startup, low line, or abrupt compressor torque steps.
Evidence priority: DC-link min/ripple during compressor start and during a commanded load step.
LV Domain (Aux rails)
Treat LV rails as a dependency chain (12V→5V→3V3→1Vx). The critical variable is not steady voltage, but droop slope and time spent below UVLO/BOR during transients.
Evidence priority: 3V3 droop slope aligned with reset timestamp + reset cause register/log.
PFC evidence hooks (what to observe)
- Startup ramp shape: smooth rise versus step-back/hiccup patterns (suggests UVLO or protection re-triggering).
- Ripple under load: ripple envelope growth during inverter switching (suggests bus capacitance/loop margin/sense noise).
- Load-step minimum: DC-link minimum value and recovery time when compressor current ramps.
- Brownout behavior: whether line dips push DC-link below a critical threshold that cascades into LV rail droop.
LLC/Flyback pitfalls (most common field edges)
- Light-load burst / skip: intermittent switching bursts can increase rail ripple and radiated/ conducted noise.
- Standby boundary: tiny loads can be less stable than moderate loads (poor damping / burst window interactions).
- Cold start: low temperature + low line narrows startup margin; auxiliary UVLO may retrigger repeatedly.
- Brownout cascade: HV sag → LLC control stress → LV rail droop → BOR/reset loops.
First 2 measurements
- TP1 (HV DC-link): capture ripple + minimum during compressor start and an intentional load step.
- TP2 (MCU 3V3): capture droop slope and align it with reset/BOR timing and reset-cause logs.
Power Rails checklist (deliverable)
| Rail | Typical range | Ripple target | UVLO / BOR threshold | Measurement point | Common symptoms | First suspect | Log hook |
|---|---|---|---|---|---|---|---|
| HV DC-link | ~380–420V (design dependent) | Low ripple; watch envelope on load steps | PFC/driver UVLO dependent | TP1 at bus cap bank (short loop) | Trip at start, hiccup, intermittent reboot | Bus caps/loop margin/sense noise | Brownout counter + DC-link min snapshot |
| 12V | 11–13V (typ.) | Moderate; check load step sag | Driver/relay UVLO dependent | TP3 near 12V bulk decoupling | Fan/relay misbehavior, false faults | Bulk cap ESR, wiring, return path | 12V min + fault correlation timestamp |
| 5V | 4.75–5.25V | Low; avoid burst envelope coupling | Peripheral UVLO dependent | TP4 at 5V regulator output | Sensor glitches, comm errors | Regulator stability/decoupling/layout | Peripheral error counters + rail min |
| 3V3 (MCU) | 3.1–3.5V | Very low; droop slope critical | MCU BOR setting dependent | TP2 at MCU VDD + local caps | Reset/reboot, Wi-Fi dropouts, freezes | Droop slope, BOR config, return bounce | Reset cause + brownout event record |
| 1Vx (core) | platform dependent | Very low; spikes can crash compute | SoC core UVLO dependent | TP5 near core regulator output | Freeze, watchdog storms | Core regulator transient response | Watchdog/reset loop counters |
Power Stage + Gate Drive + Current Sense (Evidence-First)
Goal Cover compressor-drive hardware keys without control-algorithm deep dives. The focus is evidence that separates true overcurrent from false trips, and isolates gate-drive integrity issues under high dv/dt.
Compressor drive reliability depends on three board-level chains: (1) the power device choice (IPM vs discrete), (2) the gate-drive chain (bootstrap, Miller/dv/dt immunity, deadtime margin), and (3) the current-sense chain (bandwidth/noise/CMR and layout return path). Most field “start-then-trip” events can be classified by capturing two waveforms and aligning them with the fault flag timing.
Power device options (engineering-level selection)
- IPM: higher integration and protection visibility (fault pins), often cleaner bring-up, but tighter thermal constraints and less layout freedom.
- Discrete MOSFET/IGBT: more flexibility and potential performance, but gate-loop layout and dv/dt control become primary risk factors.
- Selection focus: dv/dt tolerance, protection interface, thermal margin, and service diagnostics (fault reporting granularity).
Gate-drive evidence hooks
Validate bootstrap refresh, Vgs amplitude, and turn-off integrity. False turn-on from Miller/dv/dt coupling often appears as a gate “bump” during off-time and a current spike aligned to the fault.
Key risks: bootstrap undervoltage, dv/dt induced turn-on, deadtime/cross-conduction.
Current-sense evidence hooks
Separate true overcurrent from false OCP by checking whether the raw sense signal is saturating, spiking with switching edges, or drifting with ground bounce. Bandwidth and layout return path often dominate.
Key risks: dv/dt injection, reference ground shift, amplifier saturation recovery.
First 2 waveforms (deliverable)
- Waveform A: HV DC-link (TP1) + phase current (or current-sense amplifier output) around start/trip to identify bus sag vs overcurrent signature.
- Waveform B: gate waveforms (HS/LS, TP-GH/TP-GL) to confirm Vgs amplitude, deadtime margin, and off-time Miller bumps; align with FAULT timing.
Board-level coupling note
DC-link capacitor placement and return path shape the noise seen by both the current-sense reference and the gate driver ground.
Improving the current loop and sense return often reduces false trips more effectively than raising thresholds.
Indoor/Outdoor Fans, Valves, Relays/SSR: Switching Coupling & Protection
Goal Group all non-compressor loads into one evidence-driven chapter. The primary risk is not “can it drive the load” but whether switching transients and reverse injection couple into 3V3/1Vx, ADC/REF, or Wi-Fi rails, causing resets, packet drops, and false faults.
A main control board typically drives multiple auxiliary loads that switch frequently and often connect to long harnesses. These loads share the same low-voltage infrastructure as the MCU, sensor sampling chain, and radio module. The fastest classification is to treat each auxiliary load event as a potential transient source and verify whether the event produces a synchronized signature on 3V3 droop/spike and on a local load-side node.
Small BLDC fan drives
Implementations range from integrated fan-driver ICs to discrete MOSFET stages. The common coupling mechanism is di/dt return path during PWM edges and inrush/stall events.
Evidence focus: fan start/stall event → 12V/5V sag or spikes → 3V3 droop slope and fault counters.
Coils: valves, relays, contactors
Coil turn-off energy creates flyback. Reverse injection and ground bounce can lift the local reference, corrupting thresholds and sampling. Isolation must be judged by evidence, not by schematic intent.
Evidence focus: coil node flyback shape + 3V3/REF spikes aligned to reset/packet drops.
SSR / triac-input loads
- dv/dt susceptibility: noisy environments can create unintended triggering signatures that align with high-power switching events.
- Control-side injection: opto/SSR input currents and return paths can shift local ground at the MCU domain if not partitioned.
- Evidence rule: if packet drops or resets align to SSR switching edges, treat it as a coupling-path problem first.
First 2 evidence captures
- Evidence A: 3V3 (TP-3V3) droop/spike around each load transition + reset-cause / packet-drop counters aligned by timestamp.
- Evidence B: a load-side node (TP-LOAD) — fan driver switch node or coil drain/SSR input — captured in the same time window.
Load transient isolation checklist (deliverable)
| Load type | Transient type | Clamp method | Snubber / damping | Domain isolation | Return path rule | First measurement | Expected improvement signal |
|---|---|---|---|---|---|---|---|
| BLDC fan | inrush, stall, PWM edge di/dt | TVS on supply (as needed) | RC / gate-R (edge control) | separate fan rail / bead + local bulk | power return kept off ADC/MCU ref loop | TP-12V + TP-3V3 during fan start | 3V3 droop slope reduced; fewer packet drops |
| Relay/valve coil | flyback, reverse injection | diode/TVS/active clamp | RC across coil (optional) | coil rail partition + local decoupling | coil return routed away from MCU ground | TP-COIL node + TP-3V3/REF | spike amplitude reduced; reset cause clears |
| SSR / triac input | dv/dt false trigger, CM injection | input clamp + series R | RC snubber where appropriate | isolate control return from analog domain | keep high dv/dt loop far from ADC/REF | TP-SSR input + TP-3V3 during switching | fault timing no longer correlates to switching |
Temp / Humidity / Pressure: Sampling Stability (Not a Sensor Encyclopedia)
Goal Keep the scope on the main control board’s sampling chain: input protection, RC settling, ADC reference/ground integrity, and digital bus robustness. The chapter is evidence-first: a symptom is only trusted after checking raw codes or bus counters against REF/3V3 behavior.
In a smart AC controller, most “sensor drift” complaints are caused by sampling-chain instability rather than the sensor itself. The discriminator is synchronization: if multiple channels jump together or align with inverter/relay switching events, prioritize ADC_REF, 3V3 integrity, and return-path/common-mode injection before suspecting real physical changes.
Temperature (NTC / RTD divider)
Stability depends on divider impedance, input protection, and ADC settling. Long harnesses add EFT/ESD energy that often re-enters through the ground reference. Validate raw ADC code against ADC_REF and 3V3 in the same capture window.
Evidence: raw ADC code + TP-REF + TP-3V3 + event alignment (fan/relay/inverter).
Humidity (I²C digital or analog AFE)
For I²C sensors, VDD ripple and SCL/SDA edge quality dominate. For analog RH, REF and ground bounce dominate. Use error counters (NACK/CRC/retries) as the primary evidence, then correlate with supply and switching events.
Evidence: TP-SENS_VDD + SCL/SDA edges + NACK/retry counters vs event timing.
Pressure (analog 0.5–4.5V class)
- Input protection: series resistance + clamp strategy chosen by expected surge/ESD energy path.
- Filter vs responsiveness: RC must match sampling cadence to avoid “slow-follow” artifacts and ghost steps.
- Supply modulation check: correlate pressure output with sensor VDD ripple to separate real change from supply-induced variation.
Sampling stability rules (board-level)
- ADC_REF wins over input: a noisy reference makes all channels “look bad” simultaneously.
- Ground bounce signature: multi-channel correlated jumps often indicate reference/return issues.
- Anti-alias & settling: if changing sampling rate/order changes the artifact, the issue is in the sampling chain.
Sensor evidence table (deliverable)
| Symptom | First check | Second check | Quick discriminator | First fix direction |
|---|---|---|---|---|
| Temp jumps when fan/relay switches | raw ADC code (temp channel) | TP-REF + TP-3V3 in same window | channels jump together → REF/ground | REF decoupling, return path, input RC/TVS placement |
| Humidity reads erratic / I²C timeouts | NACK/CRC/retry counters | TP-SENS_VDD + SCL/SDA edge quality | errors align to switching → CM injection | sensor VDD isolation, pull-ups, routing/return |
| Pressure “drifts” with inverter activity | raw ADC code (pressure) | pressure VDD ripple + input node noise | output tracks VDD ripple → supply modulation | VDD filtering, input protection/RC, ground reference |
| Random spikes on one channel only | input node waveform (TP-AIN) | event correlation + cable EFT/ESD | single-channel only → harness injection | ESD clamp strategy, RC, connector shield/return |
Power-Up, Reset/BOR, Clock, and Isolation: Evidence-Driven “Random Reset” Triage
Goal Convert “random freeze/reset” into measurable evidence. The chapter stays on board-level facts: rail droop vs BOR threshold, reset cause, clock symptoms under EMI, and isolation mis-trigger under dv/dt. No firmware tutorials.
The control domain becomes predictable once the reset event is tied to a waveform and a timestamp. A reset is not defined by “power lost”; it is defined by whether the rail crosses a threshold long enough to trigger BOR/UVLO, or whether noise enters the reset pin, clock source, or an isolation boundary. The fastest path is to align three artifacts: 3V3 integrity, RESET/PG timing, and reset-cause logging.
Reset/BOR: threshold vs droop shape
Treat rail events as two shapes: a short “needle dip” (may not trigger BOR) and a long “shallow sag” (often triggers BOR). The discriminator is alignment: capture 3V3 droop and RESET/PG edge in the same window, then compare to the logged reset cause.
Evidence: TP-3V3 + TP-RST/PG + reset-cause field + event timestamp.
Clock under EMI: symptoms & measurement
Clock issues often present as peripheral anomalies without a full reset (UART framing errors, timer drift, watchdog spikes). Prefer a dedicated observable (CLK_OUT/MCO or a fixed-rate GPIO heartbeat) and correlate anomalies to high dv/dt events.
Evidence: TP-CLK_OUT (or heartbeat) vs inverter/relay events.
Isolation boundary (if present)
- Mis-trigger: short pulses on isolator output can create false faults or unintended state changes.
- Edge loss: missing edges on PWM/control lines can disturb the power stage even without a reset.
- How to prove: compare isolator input and output during high dv/dt windows; look for non-causal toggles.
Deliverable: Minimum instrumentation (DMM + 2-ch scope)
| Tool | Must-capture point | What to look for | Pass/Fail discriminator | First fix direction |
|---|---|---|---|---|
| DMM | 3V3 / 5V / RF rail steady-state | gross undervoltage, wrong rail selection | steady-state out of range → fix supply chain first | regulator config, rail mapping, load budget |
| Scope CH1 | TP-3V3 (MCU domain) | droop min, droop slope, spikes at events | RESET aligns to droop crossing threshold | decoupling, return path, rail partition, hold-up |
| Scope CH2 | TP-RST/PG (or heartbeat/CLK_OUT) | reset edge timing, false pulses, missing clocks | RESET not aligned to 3V3 droop → noise/chain issue | reset filtering, routing, isolation immunity, clock robustness |
Unstable Connectivity = Power + EMI + Counters (Board-Level Only)
Goal Diagnose Wi-Fi/BT instability using two evidence classes only: RF rail waveform and wireless counters. This chapter avoids router setup and protocol tutorials; it focuses on supply integrity, coupling paths, and on-board observables.
Connectivity failures in a smart AC controller are usually repeatable once a power waveform and a counter timeline are aligned. The radio domain draws burst current during scanning, association, and TX bursts. Meanwhile, inverter dv/dt and relay flyback can inject common-mode noise into the RF rail, the module ground reference, and the antenna keep-out region. The fastest triage is to correlate TP-RF_VDD with reconnect / TX retry counters and with brownout/reset counters.
Module power: peak current & return path
Partition the supply chain as: upstream rail (5V/3V3) → RF regulator (LDO/DC-DC) → RF_VDD → module. Problems manifest as short dips (brownout), ripple (retries), or return-path pollution (threshold jitter).
Evidence: TP-RF_VDD waveform vs reconnect/TX-retry timing.
EMI coupling: supply, common-mode, near-field
Inverter switching creates dv/dt common-mode injection. Coil/relay events create flyback and ground bounce. Near-field coupling occurs when high di/dt loops sit near the antenna/matching zone.
Evidence: counters change with inverter/relay events even when RF_VDD looks steady.
Key counters (evidence-first)
- Wireless: RSSI trend, reconnect count, TX retry count, association failures (as available).
- System: brownout counter, reset cause, rail-min snapshot (if implemented).
- Rule: a connectivity conclusion is accepted only after aligning counters to TP-RF_VDD and load-switching timestamps.
Deliverable: Connectivity triage (2-evidence flow)
| Step | Evidence | If abnormal… | If normal… | First fix direction |
|---|---|---|---|---|
| 1 | TP-RF_VDD waveform (dip/spike/ripple) + TP-3V3 compare | power integrity issue dominates | go to Step 2 | RF regulator choice, local bulk/MLCC, return path, rail partition |
| 2 | Reconnect / TX retry / RSSI timeline aligned to inverter/relay events | EMI coupling dominates | consider coexistence boundary | keep-out, shielding/grounding, cable CM path, filtering, layout loop reduction |
| 3 | Coexistence window (Wi-Fi + BT simultaneous) vs counters | boundary condition triggered | re-check evidence quality | rail headroom, clock robustness, isolation of noisy loads from RF domain |
ESD/EFT/Surge as Board-Level Paths: Parts, Layout Rules, and Test Hooks
Goal Convert harsh events into three actionable items: energy path, clamp/return implementation, and verification hooks. This section stays on the main control board (no certification procedures).
Ruggedness is achieved when energy is forced to flow through an intentional path. The practical question is never “which component is better,” but “where does the current go during surge/ESD/EFT, and which domain is kept quiet.” A correct design can be validated quickly if the board exposes measurement hooks for surge paths, ground bounce, and clamp effectiveness.
AC input protection: surge energy path
Treat the AC entry as an energy-router. The entry chain should define a preferred path that prevents surge stress from migrating into the PFC switch, rectifier, and DC-link. The board-level outcome is determined by placement: the clamp loop must be short and anchored at the entry region.
Focus: MOV/NTC/fuse placement + entry loop length + “what gets hit first.”
Low-voltage ports: clamp + return path
A TVS is only effective if the ESD return loop is short and does not pollute sensitive references. Pairing CMC (common-mode control), TVS (peak clamp), and RC/series-R (edge limiting) forms an “interface immunity chain.”
Focus: ESD return destination + CMC/TVS loop + RC impact on timing/sampling.
Board-level safety structures (no procedures)
- Creepage/clearance: keep the HV/primary region physically separated from low-voltage sensing/control. A visible isolation barrier (and keep-out) prevents accidental coupling and supports predictable noise return.
- Isolation power (if used): treat isolated DC-DC as a “domain bridge” with its own switching noise loop; keep its return and high-frequency current paths away from ADC reference and RF power.
- Leakage observation: reserve observation points for ground bounce and common-mode behavior so that “leakage-like symptoms” can be distinguished from real sensor drift or RF weakness.
Deliverable: EMC test hooks (design for measurability)
| Hook | Location | Purpose | Instrument | Expected signature | Failure signature |
|---|---|---|---|---|---|
| TP-ACIN | AC entry, near clamp loop | entry surge / clamp behavior | scope (HV probe if needed) | controlled clamp event, short ringing | long ringing, stress propagates downstream |
| TP-DCLink | HV bus capacitor region | bus ripple & disturbance coupling | scope | ripple envelope matches load profile | spikes/dips aligned to harsh events |
| TP-SW | PFC/primary switching node vicinity | switching-node stress & ringing | scope, near-field probe | bounded ringing and repeatable edges | excessive overshoot / burst instability |
| TP-IF | low-voltage connector protection zone | TVS effectiveness & return path | scope | short clamp pulse, clean return | clamp current pollutes ADC/3V3 reference |
| TP-GND_B | power ground vs signal ground reference | ground bounce / common-mode activity | scope (diff), current clamp | bounded bounce under switching | bounce aligns to reset/sensor jumps |
| TP-RF_VDD | RF rail near module | RF-domain immunity under EFT/ESD | scope | no brownout dips during events | dips aligned to reconnect/TX retry spikes |
Spec-First BOM Comparison: 6 Chains → Key Specs → Evidence Hooks
Goal Provide a spec-first selection map for procurement and engineering. The map prioritizes comparison dimensions, interfaces, and failure signatures rather than a brand/model catalog.
Selection is safer when each IC family is tied to (1) its position in the control-board chain, (2) the measurable behavior it controls, and (3) the evidence hook that confirms correctness during bring-up. The six groups below are aligned to this page’s chains: power tree, motor stage, sensing stability, MCU robustness, connectivity, and protection reporting.
PFC controller
Compare by power range, startup/brownout behavior, protection reporting, and EMI-friendly operating behavior. Ensure the controller’s fault signaling can be logged and correlated to DC-link disturbances.
Evidence: TP-DCLink ripple envelope + “soft-start repeat / hiccup” signature.
LLC / Flyback controller + primary switch
Compare light-load behavior (burst/skip), cold-start stability, protection mode observability, and stress margin. Favor designs that keep 3V3 droop slope predictable across standby and load steps.
Evidence: PG timing + rail droop slope at cold start / brownout.
Gate driver / IPM
Compare dv/dt immunity, gate drive current, bootstrap constraints, and protection interface (fault pins). The priority is “no false turn-on” and “fault timing is observable.”
Evidence: TP-GATE (HS/LS) + fault pin timing vs phase current.
Current sensing (amp / isolated)
Compare bandwidth vs noise, common-mode range, offset/drift, and recovery from saturation. A marginal choice often appears as protection trips that align with switching edges, not with real load.
Evidence: TP-CS output spikes aligned to trips vs true load events.
Sensor AFE / ADC / reference
Compare reference noise/drift, input protection compatibility, settling constraints, and interface robustness. The key discriminator is whether multiple sensors “jump together” during power-stage events.
Evidence: raw codes vs TP-REF / TP-3V3 correlation.
Wi-Fi/BT module power (DC-DC/LDO)
Compare transient response under TX bursts, PSRR/noise behavior, and layout sensitivity. A good choice keeps RF_VDD stable and prevents reconnect/TX-retry counters from spiking under switching.
Evidence: TP-RF_VDD dips vs reconnect/TX retry timeline.
Deliverable: Spec-first selection table
| Group | Key specs to compare (spec-first) | Interfaces / hooks | Board-level risks if wrong | Example device type (not a catalog) |
|---|---|---|---|---|
| PFC controller | power range, startup/brownout behavior, protection reporting, EMI-friendly operation | fault pin, enable/PG, current sense input | DC-link disturbance, repeated soft-start, EMI instability | CRM/CCM PFC controller family |
| LLC/Flyback + primary | light-load mode, cold-start stability, protection mode visibility, stress margin | PG, hiccup/latched fault behavior, opto/feedback hooks | standby ripple, brownout reset, audible burst artifacts | LLC controller + primary MOSFET family |
| Gate driver / IPM | dv/dt immunity, drive current, timing constraints, fault interface | fault pin, bootstrap, DESAT/OC hooks (as available) | false turn-on, shoot-through risk, unobservable faults | 3-phase gate driver or IPM family |
| Current sensing | bandwidth/noise trade, CMR range, offset/drift, saturation recovery | analog output to ADC, isolation interface (if needed) | nuisance trips, drifted thresholds, blind spots under dv/dt | CSA / isolated current sense family |
| Sensor AFE/ADC/REF | reference noise/drift, input protection compatibility, settling constraints, interface robustness | REF pin, ADC timing, I²C robustness hooks | false sensor drift, jumps aligned to switching events | precision reference + ADC/AFE family |
| RF rail regulator | transient response, PSRR/noise, EMI behavior, layout sensitivity | enable/PG, output monitoring TP, ground return rules | reconnect spikes, TX retry explosion, RF brownout | RF-grade LDO or DC-DC family |
SOP: Symptom → Evidence → Isolate → First Hardware Fix (with MPN examples)
Rule Each symptom starts with two measurements (highest yield), then uses evidence to split root-causes, and ends with the first hardware fix direction. Logs/counters must align in time with waveforms.
Minimum toolkit DMM + 2-ch oscilloscope (TP-3V3/TP-RESET or TP-PG as default). Optional: current clamp and near-field probe for hard-to-reproduce EMI.
| Hook | Measure | Used for | Typical correlation |
|---|---|---|---|
| TP-DCLink | HV bus ripple / sag | line-dependent faults, PFC/PSU stability | cold start, compressor start |
| TP-3V3 / TP-1Vx | MCU rail droop / ripple | reset/reboot, random hang | load switching, EMI events |
| TP-RESET / TP-PG | reset timing / PG chatter | BOR vs noise-injected reset | MCU resets |
| TP-GATE | HS/LS gate waveform | false turn-on, shoot-through risk | trip at start, hot mis-trip |
| TP-CS | current-sense output | real overcurrent vs sense spikes | start trip / nuisance trip |
| TP-REF | ADC reference stability | sensor drift/jump legitimacy | multi-sensor simultaneous jumps |
| TP-RF_VDD | Wi-Fi/BT rail dips | disconnect/reconnect evidence | TX burst / inverter edges |
| TP-GND_B | ground bounce (P-GND vs S-GND) | noise coupling path confirmation | reset, sensor jumps, RF drops |
1) Cold start fail / reboot loop
- CH1: TP-3V3 (or TP-1Vx), CH2: TP-RESET/TP-PG (same screen).
- TP-DCLink ripple envelope during start (low line / cold).
- RESET aligns with 3V3 droop crossing threshold → rail transient / UVLO/BOR chain.
- RESET toggles without 3V3 droop → reset pin noise injection / ground bounce.
- No reset cause logged but reboot occurs → clock loss / WDT behavior (use heartbeat GPIO if available).
- Increase MCU-rail transient margin: local bulk + shorter return path; isolate noisy loads from MCU domain.
- Harden reset chain: supervisor + RC/ESD clamp near MCU/reset header; shorten loop.
- Stabilize auxiliary/standby supply behavior at cold/low-line (avoid repeated hiccup).
2) Compressor start → trip / protection immediately
- CH1: TP-CS (sense output), CH2: TP-DCLink (same screen).
- TP-GATE (pick one phase HS/LS) if scope channels allow.
- TP-CS shows sharp spikes/saturation recovery aligned to trip → sense chain / layout injection.
- TP-DCLink deep sag at start → bus margin / start-up power path issue.
- Gate shows abnormal rise (Miller) or overlap tendency → dv/dt immunity / gate loop issue.
- Fix sense chain first: reduce dv/dt pickup, adjust bandwidth/RC at CSA input/output, improve kelvin routing.
- Improve gate-drive robustness: shorten gate loop, tune gate resistors, add Miller clamp where applicable.
- Increase DC-link hold-up at start and reduce bus ringing (layout + capacitor placement).
3) High-frequency noise / EMI → Wi-Fi drops (disconnect/reconnect)
- CH1: TP-RF_VDD (near module), CH2: TP-3V3 (same screen).
- Log counters trend: reconnect, TX retry, RSSI aligned to inverter/relay events.
- RF_VDD dips align to reconnect spikes → RF power integrity problem.
- RF_VDD stable but TX retry explodes aligned to inverter edges → EMI/common-mode coupling path.
- Worse only with BT+Wi-Fi concurrency → margin boundary (still evidenced by power + counters).
- Strengthen RF rail: regulator transient response + local decoupling + quiet return path.
- Reduce coupling: keep high di/dt loops away from RF zone; enforce keep-out and ground reference continuity.
- Add observability: keep TP-RF_VDD and TP-GND_B accessible for field correlation.
4) Humidity / pressure readings drift or jump
- Sensor raw code/voltage + TP-REF (or TP-3V3) correlation.
- TP-IF at connector protection zone during relay/motor switching events.
- Multiple sensors jump together → reference/ground-bounce modulation (not real environment).
- Only one channel jumps aligned to switching → interface injection/return path issue.
- Digital RH (I²C) shows intermittent read failures aligned to noise events → VDD/SCL/SDA integrity.
- Stabilize reference and return path for ADC/sensing; separate sensor ground from power switching currents.
- Build an interface immunity chain: CMC/series-R + TVS + RC matched to sampling/edges.
- For analog pressure (0.5–4.5V): clamp + RC so settling completes before sampling.
5) Load switching → MCU reset (relay/valve/aux load)
- CH1: TP-3V3, CH2: TP-RESET/TP-PG (same screen).
- Probe load drive node (coil/SSR control) aligned to the reset moment.
- 3V3 droop aligns with reset → rail transient margin / domain isolation.
- 3V3 stable but reset toggles → reset pin injection / ground bounce.
- Only specific inductive load triggers → flyback/snubber/return path issue.
- Clamp inductive energy locally: diode/TVS/RC snubber close to load and with short loop.
- Separate noisy load domain from MCU domain: dedicated supply path + local bulk near MCU.
- Observe ground bounce: keep TP-GND_B and verify bounce does not correlate with reset.
6) After heat-up: derate / nuisance protection trips
- Thermal channel raw code + TP-REF (or TP-3V3) correlation.
- Fault flags timeline (OT/OC/UV) aligned to temperature rise.
- Trip point stable vs temperature → real protection action.
- Trip aligns to switching edges and worsens with temperature → drift/noise in sense chain or gate robustness loss.
- Multiple channels drift together with REF ripple → reference/ground-bounce issue.
- Prioritize low-drift sense/reference components for thresholds that must hold over temperature.
- Control dv/dt pickup: gate loop, CSA routing, Kelvin sense, and ground segregation.
- Improve thermal measurement integrity: local filtering + stable reference path.
7) More failures at certain mains voltages (line-dependent)
- TP-DCLink ripple/sag under low-line and high-line.
- TP-3V3 minimum value and ripple across line conditions.
- Low-line: DCLink sags and LV rails degrade → PFC/PSU margin or light-load mode instability.
- High-line: more spikes/ringing → entry protection path / switching-node stress / layout loop length.
- RF drops correlate to line events → noise injected into RF rail/regulator.
- Make startup/standby behavior predictable: avoid repeated hiccup and uncontrolled burst at light load.
- Reduce switching-node ringing (layout + snubber) and keep energy path at entry short.
- Ensure measurement hooks exist: TP-ACIN, TP-DCLink, TP-SW for fast comparison between line cases.
8) Random hang in field, hard to reproduce in lab
- CH1: TP-3V3, CH2: TP-GND_B or TP-RESET (same screen, long capture).
- Event counters: reset cause / brownout / fault flags / reconnect & TX retry (align timestamps).
- Brownout/WDT counters rise but waveforms are missed → event is too short/rare; improve observability.
- No reset but function hangs → clock/EMI induced state errors; correlate to inverter/relay edges.
- Only in harsh environments → interface immunity and return paths (TP-IF + TP-GND_B) become primary suspects.
- Add capture hooks before changing parts: TP-GND_B, TP-RF_VDD, TP-IF, and consistent fault logging.
- Shorten noisy loops and enforce ground segregation; keep reset/clock traces protected.
- Use robust supervisors/watchdog strategies for recoverable faults (hardware + log visibility).
Quick triage checklist (copy into a work order)
- Is there a reset? Check reset cause/brownout/WDT counters. If yes → go to rail & reset chain.
- Rail & reset chain: TP-3V3 + TP-RESET/PG. If aligned droop → fix rail transient/isolation. If not aligned → fix reset injection/ground bounce.
- Trip at compressor start: TP-CS + TP-DCLink. If CS spikes/saturates → fix sense chain/layout. If DCLink sags → fix bus margin/start path. Confirm with TP-GATE.
- Wi-Fi drops: TP-RF_VDD + reconnect/TX-retry trend. If RF_VDD dips → fix RF rail. If counters lock to inverter edges → fix EMI coupling path.
- Sensor drift/jump: raw codes vs TP-REF/TP-3V3. Multi-channel jumps → reference/ground. Single-channel lock to switching → interface injection chain (CMC/TVS/RC + return).
Request a Quote
FAQs (Evidence-First): Power / Drive / Sensing / RF / Protection / Logs
Each answer is engineered to “close the loop” with two priority evidence points (waveform TP + log/counter/flag), then a discriminator split, then a first hardware fix direction with a clear validation signal.
Common evidence hooks: TP-DCLinkTP-3V3TP-RESET/PG TP-CSTP-GATETP-REF TP-RF_VDDTP-IFFault flags / reset cause
1) “Boots fine” but reboots when the compressor starts: which 2 waveforms first?
Start with one screen capture: TP-3V3 (or TP-1Vx) on CH1 and TP-RESET/TP-PG on CH2. If reset aligns with a rail dip crossing BOR/UVLO, the root is power transient margin. If reset toggles without a rail dip, suspect reset-line injection or ground bounce. Validate by removing the reboot while keeping compressor start unchanged.
2) DC-link looks stable but OCP still triggers: sense noise or real overcurrent?
Capture TP-CS (current-sense output) while logging the exact OCP fault flag timestamp. If TP-CS shows narrow spikes, saturation, or slow recovery that is phase-locked to switching edges at the trigger moment, it is usually pickup/noise in the sense chain. If TP-CS is clean and truly rises, confirm with TP-DCLink sag and gate behavior.
3) Wi-Fi drops only when the compressor runs: prove power first or EMI first—what 2 evidences?
Pair TP-RF_VDD waveform with reconnect / TX-retry counters. If reconnect spikes align with RF_VDD dips during TX bursts, fix RF rail transient response and return path. If RF_VDD is stable but TX-retry explodes in sync with inverter edges, it is EMI coupling (common-mode/return path). Validation is counters stabilizing under the same compressor PWM condition.
4) Low-temperature start failure: PFC not starting or auxiliary UVLO—how to separate?
Compare startup shapes of TP-DCLink and TP-3V3 (aux/LV rail). If DCLink never rises properly or has abnormal ripple during ramp, focus on the AC→PFC path and bus establishment. If DCLink rises normally but 3V3 hiccups (repeated rise/fall) or PG chatters, the auxiliary supply UVLO / light-load behavior is the primary suspect. Validate by stable LV rails before compressor enable.
5) Humidity reading is intermittent: check I²C first or power noise first—one test to decide?
Correlate sensor VDD at the RH device with I²C error evidence (NACK count, timeout, or “missing read” timestamps). If read failures align with VDD dips or noisy bursts during load switching, it is power integrity to the sensor domain. If VDD is stable but failures align to fast edges on SCL/SDA or ESD events, it is interface injection/return-path. Validation is stable reads during the same switching events.
6) Pressure readings “jump”: input clamp action or ground bounce—how to tell quickly?
Plot raw pressure voltage/code against TP-REF (or TP-GND_B). If multiple analog channels jump together and track REF or ground bounce, the root is reference/return-path modulation. If only pressure shows a clipped/flattened waveform at transients, the input protection network is likely clamping or injecting current. Validate by moving the clamp return path and seeing the jump disappear without changing the sensor.
7) Fan speed step causes MCU reset: flyback issue or 3V3 droop—most common split?
Capture TP-3V3 together with the fan drive/relay control node during the speed step. If 3V3 droops and reset aligns, it is rail transient margin or poor domain isolation. If 3V3 is stable but a large spike appears on the drive node (or on TP-IF) at switching, it is flyback/snubber/return-path. Validation is removing reset while keeping the same fan step profile.
8) Frequent nuisance trips after heat-up: check gate driver first or current-sense drift first?
Compare hot vs cold signatures on TP-CS and TP-GATE. If TP-CS baseline or noise floor increases with temperature and trips occur without a matching real current rise, suspect sense drift/bandwidth and pickup. If gate edges change (more Miller rise, slower turn-off, ringing) and trips align to switching edges, suspect dv/dt immunity and gate loop robustness. Validate by stabilizing the suspect waveform and observing trip count collapse.
9) Same batch, only some units fail in the field: which 3 tolerance stack items first?
Prioritize tolerance stacks that directly change margins: (1) minimum TP-3V3 valley during worst transient, (2) minimum TP-RF_VDD valley during TX burst, and (3) threshold-setting components for protection (sense resistor / divider / reference). If failing units show systematically lower valleys, it is power margin/timing. If valleys match but thresholds differ, it is protection chain tolerance. Validate by binning units by these three metrics.
10) Passes ESD tests but still hangs in the field: return-path issue or clock loss?
Correlate interface-zone stress evidence at TP-IF with reset cause / hang signature (reset counter vs “no reset but freeze”). If a hang follows an interface transient and TP-GND_B shows bounce, it is return-path/ESD current routing. If there is no reset yet behavior collapses during noisy motor operation, check clock robustness (suspect EMI into crystal/clock traces). Validation is eliminating hangs by fixing the identified path without firmware changes.
11) Light-load standby squeal / flicker: LLC burst or auxiliary flyback loop issue?
Observe LV rail ripple envelope (e.g., TP-5V/TP-3V3) and correlate it to audible squeal/flicker timing. A periodic burst-like envelope strongly suggests light-load burst/skip behavior. A low-frequency oscillation with slow ramping indicates loop stability/compensation or sampling point issues in the auxiliary path. Validation is removing the envelope/oscillation while holding standby load constant (minimum load, damping, or compensation fix).
12) Logs only say “reset”: which 3 reset evidences must be recorded and how to read them?
Record three items: (1) reset cause (POR/BOR/WDT/external), (2) brownout counter or minimum-rail event counter, and (3) protection snapshot (fault flags + key counters like reconnect/TX-retry) captured immediately before restart. First read (1)+(2) to decide “power vs logic,” then use (3) to bind the reset to a specific chain (drive/sense/RF). Validation is turning “reset” into a reproducible evidence entry.
