Intent Define the problem precisely, explain why long/heavy harnesses reduce margin at higher speeds, and state what SIC changes at the PHY waveform level.

Working definition (PHY-level)

Signal Improvement CAN (SIC / SIC-XL) is a PHY-side waveform strategy that restores symmetry and receiver decision margin on real automotive harnesses—especially when long cable runs, heavy loads, and topology discontinuities degrade edge behavior.

Typical pain points (observable symptoms → likely margin killers)

• Bench OK, vehicle harness fails: topology reflections and load-dependent ringing dominate on real wiring.
• Add 1–2 nodes and errors spike: extra node capacitance shifts damping and crossing stability.
• One branch is “weaker”: stubs and T-branches create localized impedance steps and late reflections.
• High bus load triggers bursts: reduced settle time exposes marginal crossings (not just timing configuration).
• Temperature corners diverge: driver/receiver behavior drifts, shrinking the usable decision window.

Why higher-speed phases become more fragile on long/heavy harnesses

• Tighter settle budget: shorter bit times leave less time for ringing/reflection energy to decay.
• Crossing-point instability: asymmetry and over/undershoot move the threshold crossing and add effective jitter.
• Common-mode sensitivity: ground offsets and CM noise couple into the receiver threshold region.
• Result: waveform imperfections are amplified into decision uncertainty, often misdiagnosed as “timing tuning.”

SIC vs SIC-XL (relationship and boundary)

Intent Make page ownership explicit: what changes at the PHY waveform level vs what stays in controller/timing, and route readers to the correct sibling pages.

The coordinate system (to prevent overlap)

SIC sits at the PHY waveform layer. It improves symmetry and decision margin so the electrical signal behaves predictably on harsh harnesses. Controller behavior, protocol framing, and full timing derivations are intentionally routed to sibling pages.

What changes vs what stays (fast routing rules)

See also (sibling-page anchors)

Intent Explain PHY logic end-to-end: why symmetry matters, how asymmetry erodes the decision window, and how SIC improves margin without relying on “just slowing edges.”

What “symmetry” means at the receiver

• Dominant/recessive balance: transitions and steady levels keep the threshold-crossing behavior consistent across directions.
• Crossing stability: the threshold crossing occurs once and stays stable (no repeated re-crossing inside the decision window).
• Predictable settle: residual ringing decays fast enough so the receiver is not forced to decide in a noisy threshold region.

How asymmetry erodes decision margin (the failure chain)

• Threshold-crossing jitter: ringing and slope variation near the receiver threshold shift the effective edge timing.
• Ringing-induced false edges: multiple threshold re-crossings can create ambiguous transitions and sampling uncertainty.
• Margin collapse: the usable decision window shrinks, so the same harness becomes sensitive to load, temperature, and common-mode disturbances.

How SIC-style shaping improves margin (not a blunt “slow everything” approach)

• Targeted threshold behavior: improves the predictability of the crossing region so the receiver sees fewer ambiguous transitions.
• Symmetry restoration: reduces direction-dependent distortions so dominant and recessive transitions behave more similarly.
• Controlled settle: reduces ringing energy that would otherwise land inside the decision window under heavy load/topology stress.

Quick validation (evidence chain)

1. Observe the threshold region: compare crossing stability and re-crossings inside the same decision window on a real harness.
2. Correlate with error counters: relate crossing instability to error bursts (TEC/REC trends) under bus-load changes.
3. Stress corners: check temperature and node-count changes; a robust solution keeps crossing behavior consistent across corners.

Intent Turn “long harness/heavy load” into a measurable model: reflection points, damping regimes, stubs, node capacitance, and what “good enough” looks like at the threshold region.

Harness as a distributed line (where reflections come from)

• Stubs (branch lengths): delayed echoes return into the decision window, especially in T-branches.
• Impedance steps: connectors, splices, and topology transitions create reflection hotspots.
• Mismatch / damping regime: under/over-damping changes how long ringing energy persists near the threshold region.

Heavy load patterns (many nodes, large C, star-like wiring)

• Node capacitance accumulates: additional nodes reshape edges and interact with reflections, worsening crossing stability.
• Branch-dominated behavior: the weakest branch can dominate network stability, even when the trunk looks acceptable.
• Localized worst cases: star-like wiring creates multiple reflection sources that can stack inside the same decision window.

What “good enough” looks like (qualitative + measurable knobs)

• Single, stable crossing: the threshold is crossed once, with minimal re-crossing inside the decision window.
• Ringing energy decays early: residual oscillations do not persist into the sampling-sensitive region.
• Predictable across corners: node-count and temperature changes do not trigger runaway error bursts.

Intent Convert mechanisms into engineering decisions: controllable PHY behaviors, expected effects, measurable indicators, and the risks/trade-offs under real harness stress.

Edge / drive knobs (conceptual)

• TX edge shaping / slope behavior: aims to reduce threshold-region ambiguity by controlling settle and overshoot behavior.
• Drive strength class: tunes how aggressively the network is excited; excessive drive can amplify reflections.
• Observable indicators: fewer re-crossings near threshold, reduced crossing jitter, error bursts less sensitive to node-count changes.

Symmetry enhancement behaviors (conceptual) + trade-offs

• Crossing stability focus: reduces direction-dependent distortions so dominant and recessive transitions behave more similarly.
• Margin restoration goal: improves decision-window cleanliness on long/heavy harnesses without relying on a blunt slowdown.
• Trade-off reality: “clean looking” edges are not sufficient; verify threshold-region behavior on the worst branch.

Compatibility modes & fallback behaviors (mixed networks)

• Mixed-node coexistence: choose modes that remain stable when some nodes do not support SIC-style behaviors.
• Fallback matters: validate that a fallback path does not shift the worst-branch behavior into the decision window.
• Observable indicators: stable crossing behavior and stable error counters across node subsets (SIC-capable vs legacy).

Practical decision order (avoid random tuning)

1. Pick the worst-branch test case first: longest stub / heaviest load / most reflection hotspots.
2. Tune for threshold-region stability: reduce re-crossings and crossing jitter before chasing timing parameters.
3. Validate mixed-node behavior: ensure compatibility mode keeps stability when legacy nodes join/leave the network.

Intent Explain why faster phases are more sensitive without re-deriving timing theory: waveform quality manifests as sample-point instability; measure loop-delay symmetry rather than “tune timing first.”

Why higher bit rates become sensitive (SIC-relevant view)

• Less settle time: ringing and reflections have fewer nanoseconds to decay before the receiver must decide.
• Threshold region dominates: small distortions near threshold translate into larger effective crossing-time uncertainty.
• Outcome: waveform imperfections appear as sampling uncertainty and error bursts under load/topology stress.

Loop-delay symmetry (conceptual) — measure, do not re-derive

• Symmetry matters: direction-dependent distortions create uneven effective delays, shrinking usable margin.
• Measure stability under stress: check whether crossing behavior stays consistent across node-count and branch changes.
• Use correlation: improvements should reduce sampling uncertainty and stabilize error counters on the worst branch.

What NOT to do (common misstep)

• Do not “fix timing first” when the threshold region shows re-crossings or crossing jitter on the real harness.
• Do not validate only on the trunk; the worst branch typically decides stability at higher speeds.
• Do not trust “pretty edges”; use threshold-region behavior and counter trends as the pass evidence.

Intent Explain the causal path from SIC waveform behavior to emission and immunity. Components and sizing details belong to the EMC page.

Emission vs robustness: why “faster edge” is not always better

• Fast edges excite the harness: more high-frequency energy can increase common-mode current and radiated emission on long wiring.
• Overly slow edges can linger near threshold: spending longer in the noisy crossing region can reduce RF immunity and increase false transitions.
• Engineering target: improve threshold-region predictability, not simply “fast” or “slow.”

SIC-style shaping: reduce emissions while keeping margin (conceptual path)

• Cleaner crossing behavior: fewer re-crossings and lower crossing jitter reduce receiver ambiguity under RF/common-mode disturbances.
• Controlled settle: reduces ringing energy inside the decision window on reflection-heavy harnesses.
• Balanced outcome: emission reduction is most credible when decision-window evidence and counter trends improve on the worst branch.

Scope guard + where details live

• This page covers: SIC waveform behavior → emission / immunity / margin / power trade path.
• This page excludes: split termination sizing, CMC selection, TVS parasitic modeling and placement rules.
• See also: EMC / Protection & Co-Design (termination / CMC / TVS parasitics).

Intent Turn “should SIC be used?” into repeatable patterns. Identify which network shapes benefit most and link out when details belong to sibling pages.

High-yield patterns

Decision checklist (SIC fit signals)

• Errors worsen with harness length / node count / branch count
• Threshold region shows re-crossing or crossing jitter on the worst branch
• Timing tweaks do not help until waveform behavior is stabilized
• Mixed nodes or forward XL planning make stability and compatibility more valuable

Intent Turn SIC work into an executable, repeatable workflow: freeze assumptions in design, close the waveform↔counter loop in bring-up, and add corner/aging guards for production.

Design gate (freeze topology + measurement plan)

Bring-up gate (close waveform ↔ counters loop)

Production gate (corners, aging drift, false-fail guards)

Intent Build a defensible evidence chain: define waveform metrics, log aligned counters and conditions, correlate by stress groups, and filter measurement artifacts.

What to measure (SIC-relevant metrics)

• Crossing stability: re-crossing count trend and crossing spread under node/load/temperature stress.
• Overshoot / undershoot trends: peak and decay behavior; confirm whether ringing reaches the threshold region.
• Common-mode coupling symptoms: bursty crossing jitter or counter spikes that align with disturbance/load changes.

What to log (minimum schema for repeatability)

Correlate (waveform ↔ TEC/REC ↔ load ↔ temperature)

1. Lock the worst-branch test point and measurement settings.
2. Run a controlled A/B comparison (one knob/mode change per run).
3. Align waveform metrics and counter windows by time reference.
4. Group results by stress variables (node/load/temp) and compare trends.
5. Decide: if waveform metrics improve but counters do not, suspect artifacts or hidden variables; if counters improve but waveform does not, suspect sampling/definition mismatch.

Common pitfalls (test artifacts to guard against)

• Probe/return-path artifacts: false ringing/overshoot from long ground loops.
• Bandwidth/trigger artifacts: “better waveform” illusion when settings change across runs.
• Window mismatch: counters collected over different windows than waveform captures.
• Wrong measurement point: trunk looks fine while the worst branch fails at speed.

Intent Translate “intermittent / hot-only / harness-dependent” field symptoms into SIC-verifiable paths: threshold-region behavior → counters → fastest checks → serviceable logs.

Scope guard (anti-overlap)

• Covers: SIC/SIC-XL waveform behavior in the threshold region, symmetry/margin failures, and fastest evidence checks.
• Mentions only: timing adjustments (use only after waveform evidence; link to CAN FD timing/transceiver page).
• Excludes: TVS/CMC/split-termination sizing and layout details (link to EMC & Protection page).

Intermittent error patterns (what changes the probability of failure)

Mixed-node compatibility (PHY behavior level only)

• Worst-node dominance: a single legacy or outlier PHY behavior can dictate the network’s effective margin.
• Waveform behavior mismatch: non-uniform edge/crossing behavior makes ringing alignment less predictable across branches.
• Fastest isolation strategy: roll up errors by segment/node-group and correlate with worst-branch captures (do not rely on trunk-only waveforms).

Serviceability (black-box logging fields)

Reference material numbers (examples; verify package/suffix/availability)

Intent Close the topic by mapping SIC to common ECU/domain patterns without expanding into controller/gateway internals.

Scope guard

• Covers: domain patterns that benefit from improved threshold-region predictability (long harness, heavy loading, mixed nodes, XL migration).
• Does not cover: controller scheduling/gateway filtering/DoIP/secure gateway internals (use sibling pages).
• FlexRay mention: sibling link only (no FlexRay deep dive here).

Example part mapping by application bucket (verify package/suffix)

Reminder: part numbers above are examples; always confirm the exact suffix (temperature grade, package, standby/PN feature set, EMC variant) and validate on the real worst-branch harness.

FD works on bench, fails on real harness — first symmetry or termination check?

Likely cause: A harness reflection/ringing event lands inside the receiver decision window, creating re-crossing and symmetry loss on a worst branch.

Quick check: Capture waveform on the worst branch (not trunk) and compare crossing stability (re-crossing + crossing spread) with counters aligned to the same time window.

Fix: First stabilize threshold-region behavior with SIC knob/mode A/B; if termination/CMC/TVS parasitics are suspected, validate via the EMC co-design page (no deep dive here).

Pass criteria: Crossing spread ≤ X ns and re-crossing count ≤ X per 1k edges on worst branch; TEC/REC delta ≤ X over Y minutes.

Errors spike only at high bus load — waveform distortion or sampling margin?

Likely cause: Threshold-region distortion scales with transition density, increasing crossing jitter and collapsing effective decision margin under load.

Quick check: Run low-load vs high-load A/B with identical measurement settings; correlate crossing spread/re-crossing to TEC/REC bursts using the same fixed time window.

Fix: Prioritize SIC behavior/mode that reduces re-crossing without simply over-slowing edges; if errors persist with clean waveform metrics, move to the CAN FD timing page.

Pass criteria: High-load TEC/REC burst rate ≤ X per Y minutes; crossing spread increase from low→high load ≤ X ns (worst branch).

Adding one more node breaks the network — capacitance threshold or stub resonance?

Likely cause: The incremental node pushes the worst branch into a regime where ringing crosses threshold again (re-crossing) or shifts reflection timing into the decision window.

Quick check: A/B with node N vs N+1 on the same branch; measure re-crossing count and crossing spread at the branch tap while logging TEC/REC with aligned windows.

Fix: Reduce threshold-region sensitivity using SIC behavior; if the failure is topology-driven (single branch), rework stub length/branch placement via harness constraints (details stay outside this page).

Pass criteria: With N+1 nodes, re-crossing count ≤ X per 1k edges and error frames ≤ X per Y minutes at target load.

EMI improved after slowing edges, but error frames increased — what knob is wrong?

Likely cause: Edges were slowed in a way that increased time spent near threshold or worsened symmetry, raising susceptibility to noise/reflections even as emissions dropped.

Quick check: Compare “EMI-friendly” setting vs baseline on the worst branch; look for increased crossing spread or re-crossing, then align with error bursts in the same window.

Fix: Choose SIC mode/behavior that preserves symmetry and reduces re-crossing; move component/layout tuning (CMC/TVS/split termination) to the EMC page.

Pass criteria: Emission improvement maintained while error frames ≤ X per 10^6 frames and crossing spread does not increase by more than X ns vs baseline.

Scope looks “fine”, but TEC/REC grows — what metric is missing?

Likely cause: The capture is at the wrong point (trunk not worst branch) or the missing metric is threshold-region behavior (re-crossing / crossing spread) rather than peak overshoot alone.

Quick check: Lock measurement settings and move to the suspected worst branch; compute crossing spread and re-crossing count, aligned to the same TEC/REC collection window.

Fix: Standardize a metrics dictionary (threshold crossing stability) and enforce window alignment; if waveform metrics are stable yet counters rise, suspect timing/definition mismatch (link to timing page).

Pass criteria: Worst-branch metrics recorded with fixed settings; TEC/REC delta ≤ X over Y minutes after mitigation, with no unexplained counter bursts.

Cold starts pass, hot soak fails — what drift correlates with symmetry loss?

Likely cause: Temperature drift reduces effective decision margin, visible as widened crossing spread or increased re-crossing on the same worst branch.

Quick check: Cold vs hot A/B on identical topology, identical capture settings, identical time-window alignment; compare crossing stability metrics and error bursts.

Fix: Select SIC behavior that tightens threshold-region predictability across temperature; enforce corner logging (temperature marker + mode state + counters).

Pass criteria: Hot soak crossing spread ≤ X ns and re-crossing count ≤ X; hot-window error frames ≤ X per Y minutes at target load.

Only one branch in a T fails — reflection point or ground return path?

Likely cause: The failing branch has a reflection hotspot (impedance step/stub) or a return-path issue that increases threshold-region noise coupling.

Quick check: Compare branch A vs branch B at the branch tap: crossing spread + re-crossing + overshoot trend, with aligned counter windows for each branch test.

Fix: Apply SIC setting that reduces re-crossing sensitivity; if branch-only, treat as topology/return-path issue and validate harness/ground strategy via EMC/co-design guidance.

Pass criteria: Branch A and B both meet crossing spread ≤ X ns; branch-specific error bursts ≤ X per Y minutes under the same load profile.

Mixed nodes: new SIC ECUs + legacy ECUs — what’s the first compatibility check?

Likely cause: Mixed PHY behaviors make symmetry and threshold-region stability non-uniform, so the worst node/branch dominates the network margin.

Quick check: Segment rollup: bucket errors by node-group/topology segment, then capture waveforms on the worst segment branch with aligned counter windows.

Fix: Converge to a compatible PHY behavior (SIC mode/knob) for mixed networks; if the waveform is stable but errors persist, move to timing configuration page.

Pass criteria: Worst segment error frames ≤ X per Y minutes and no dominant node-group burst remains after harmonizing mode/knob state.

After ESD test, CAN becomes fragile — what degradation pattern to verify?

Likely cause: Post-stress parameter shift reduces threshold-region margin, showing as increased crossing spread/re-crossing or higher sensitivity to load/temperature corners.

Quick check: Compare baseline vs post-ESD on the same worst branch with fixed settings; track metric trends across repeated runs and align with counter burst patterns.

Fix: Lock artifacts first (probe/ground/bandwidth), then confirm whether SIC behavior can restore stability; protection/layout verification belongs to the EMC page.

Pass criteria: Post-stress crossing spread increase ≤ X ns vs baseline; error bursts ≤ X per Y minutes across Y repeated runs.

Changing TVS vendor worsens errors — parasitics or edge-rate interaction?

Likely cause: Protection parasitics shift damping and threshold-region behavior, increasing re-crossing or moving reflection timing into the decision window.

Quick check: A/B with vendor A vs vendor B at the same worst-branch tap and identical settings; compare re-crossing + crossing spread and align with error bursts.

Fix: If waveform metrics shift, treat as parasitics interaction; move detailed TVS/CMC placement and selection rules to the EMC co-design page (linked), then re-validate with fixed windows.

Pass criteria: Re-crossing count ≤ X per 1k edges and error frames ≤ X per 10^6 frames with the chosen protection set on the worst branch.

Gateway ECU sees errors but others don’t — where to log and compare?

Likely cause: Observability mismatch: different ECUs log different windows/conditions, hiding the actual worst-branch waveform condition driving receiver margin loss.

Quick check: Standardize logging window definitions across ECUs and capture waveform on the gateway-adjacent worst branch; compare aligned TEC/REC bursts and bus load markers.

Fix: Implement a minimal black-box schema (bus load, TEC/REC burst timestamps, mode state, temperature marker, topology version) and enforce per-segment rollups.

Pass criteria: Aligned logs show consistent burst attribution; post-fix gateway segment error bursts ≤ X per Y minutes with stable worst-branch crossing metrics.

SIC-XL migration plan: what to validate first before enabling higher speed?

Likely cause: The network has hidden worst-branch margin limits that are masked at lower speed but become dominant when the decision window tightens.

Quick check: Establish a baseline on the worst branch: crossing spread, re-crossing count, and counter burst statistics with fixed settings across repeated runs.

Fix: Improve margin using SIC/SIC-XL behavior before raising speed; validate mixed-node compatibility via segment rollups, then proceed to the CAN XL PHY page for higher-speed specifics.

Pass criteria: Baseline metrics repeatable within X% over Y runs; at target speed, error frames ≤ X per 10^6 frames and TEC/REC delta ≤ X over Y minutes.