Port Protection Parasitics for CAN/LIN/FlexRay Ports
← Back to: Automotive Fieldbuses: CAN / LIN / FlexRay
Core idea
Port protection is a high-speed network element, not just a clamp: TVS/CMC/termination parasitics (Cdiff/ΔC/Lseries and return-path inductance) can quietly erase edge-rate and sampling margin.
This page turns “close placement” into measurable budgets and pass/fail checks so protection improves robustness without breaking signal integrity.
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H2-1 · Definition & Page Boundary
What “parasitics” means on this page
Port protection parasitics are the unintended C/L and mismatch introduced by TVS/ESD arrays, common-mode chokes (CMC), split-termination networks, pads/vias, and return paths. These parasitics reshape edges, create impedance steps, and convert differential energy into common-mode energy—directly reducing sampling margin and increasing ringing, reflections, and EMC sensitivity.
This topic is a standalone page because protection components are often treated as “bolt-on,” while modern automotive fieldbuses (CAN FD/XL, FlexRay) behave like high-speed networks. The protection stack must be designed as part of the channel.
The parasitics set (strict scope)
Cdiff
Differential capacitive loading that slows edges and shifts the channel’s effective impedance.
Ccm
Common-mode coupling (to local ground/chassis) that drives radiation and susceptibility via uncontrolled return paths.
Lseries (Ls)
Series inductance from package leads, pads/vias, and—most importantly—ESD return loop inductance. Creates overshoot and ringing with capacitance.
Mismatch (ΔC / ΔL)
Asymmetry between the two lines (or between channel A/B). Converts differential energy into common-mode energy and amplifies EMI/bit errors.
What gets impacted (engineering targets)
- Edge rate (dV/dt): too slow consumes timing margin; too fast worsens radiation and crosstalk.
- Reflections & overshoot: impedance steps and L–C resonance introduce ringing and false transitions.
- Common-mode radiation: mismatch + poor return converts energy into radiating currents.
- Sampling margin (eye/window): the final failure mode—error counters rise and “only fast mode fails.”
What this page delivers (outputs)
Use this page to build a closed loop from parasitic definition → budget → placement rules → selection logic → verification evidence.
Deliverable A — Scope guard
A strict Allowed/Forbidden list that prevents lateral topic drift and keeps this page focused on parasitics.
Deliverable B — Parasitic budget template
A page-level budget that turns Cdiff/Ccm/Ls/ΔC into measurable acceptance criteria (X placeholders).
Deliverable C — Placement & return-path rules
“Close placement” becomes enforceable rules: where to place TVS/CMC, how to avoid stubs, and how to keep ESD return inductance low.
Reading order (fastest value path)
Define parasitics → recognize symptoms → lock placement/return paths → set budgets → validate with evidence (before and after ESD/Surge).
Scope guard (hard rules)
Allowed
- Equivalent models for TVS arrays, CMC, split-termination, pads/vias, and return paths.
- How parasitics change edges, reflections, common-mode currents, and margin.
- Actionable placement, selection, and verification methods (evidence-first).
Forbidden
- Protocol-layer deep dives and register-level bit timing configuration (only margin impact is referenced).
- Non-fieldbus interface domains (Ethernet/USB/SerDes) and unrelated protection topologies.
- Full standard clause walkthroughs (only test scenarios and keywords are referenced).
Diagram — protection stack and parasitic paths
The same two wires carry differential signaling, while parasitic coupling and return paths determine whether protection preserves margin or creates new ringing and common-mode energy.
Minimal labels are intentional: Cdiff/Ccm/Ls/ΔC are the only variables that must stay consistent across modeling, placement, and validation.
H2-2 · Why Parasitics Break Buses
Build intuition using “symptom → physics → next verification”
Most failures that look like “controller instability” are channel changes caused by protection parasitics. This section maps common field symptoms to the smallest set of physical causes and the fastest evidence checks.
Keep this boundary
Focus on waveform/return-path evidence. Avoid protocol register tuning until parasitic causes are excluded.
Symptom index (fast triage)
Symptom: CAN FD/XL fails at top rate, stable one step down
First suspicion: Cdiff too high, Ls–C resonance, or ΔC imbalance shrinking the usable sampling window.
Next verification: check edge/ringing trend and correlate on real harness (later: Placement & Budget sections).
Fast first checks (evidence)
- Compare step response: overshoot/ringing frequency changes after adding TVS/CMC.
- Look for asymmetry: line-to-line mismatch or uneven overshoot (ΔC/ΔL clue).
- Confirm on real harness: bench cables often hide reflection sensitivity.
Symptom: passes ESD/Surge once, then becomes “more fragile” later
First suspicion: return path inductance or device drift changed the channel—small parasitic shifts can erase margin.
Next verification: run “before/after” margin comparison with the same setup (later: Verification hooks).
Fast first checks (evidence)
- Record baseline waveform and compare after stress (same probe, same harness).
- Check leakage or standby drift (low-power domains may reveal TVS changes early).
- Inspect return path integrity (short, wide, low-inductance clamp loop).
Symptom: EMI improves after CMC/TVS change, but communication gets worse
First suspicion: CMC imbalance (DM leakage) or new resonance formed with split termination and TVS capacitance.
Next verification: identify whether the change reduced common-mode at the expense of differential integrity.
Fast first checks (evidence)
- Check edge symmetry: mismatch often increases common-mode even when EMI at one band drops.
- Look for ringing relocation: resonance frequency shifts after BOM change.
- Confirm CMC placement: avoid creating a stubbed section or long midpoint return.
Symptom → first measurement mapping (minimal set)
The fastest path is to measure what parasitics change first: step response, ringing, asymmetry, and before/after stress deltas.
Measurement 1 — Step response (edge + overshoot)
Detects Cdiff increase and Ls–C resonance. Compare “with/without protection” under identical probing.
Measurement 2 — Asymmetry scan
Looks for ΔC/ΔL or CMC imbalance. Unequal overshoot or settling between the two wires is a primary clue.
Measurement 3 — Harness correlation
Validates reflection sensitivity. Real harness/stubs shift resonance and reveal margin loss hidden on short bench cables.
Measurement 4 — Before/after stress delta
Confirms degradation even when a single test “passes.” Capture baseline waveforms and counters before ESD/Surge and compare after.
Diagram — three common failure mechanisms
No detailed waveforms are required to spot the pattern: parasitics either slow edges, create ringing, or shrink the usable sampling window.
These three patterns typically explain “fast mode fails / slow mode passes.” The corrective action should follow evidence: parasitic reduction, placement optimization, or mismatch control.
Evidence chain (recommended order)
- Capture baseline waveform and error counters (same probe, same harness).
- Compare with/without protection stack to isolate Cdiff/Ls/ΔC effects.
- Validate on real harness and worst-case topology (stubs/branches).
- Only after parasitics are controlled, adjust protocol timing knobs if still needed.
H2-3 · Parasitic Model for Low-C TVS Arrays
Treat the TVS as a channel element first, a clamp second
In normal communication, a TVS rarely operates in the clamping region. What shapes edges and margin is the parasitic network it adds to the port:
Cdiff, Ccm, series inductance (Lpkg), and mismatch (ΔC). These variables create impedance steps, resonance, and differential-to-common-mode conversion.
Channel variables to keep consistent across this site
Cdiff / Ccm / Lpkg (or Ls) / ΔC (match) / return-path inductance
Model card — simplified equivalent circuit (what matters to edges)
The simplest useful model separates differential loading from common-mode coupling. Mismatch (ΔC) is treated as an asymmetry term that converts differential energy into common-mode energy.
Cdiff (differential loading)
Dominant knob for edge rate and high-rate margin. Excess Cdiff slows transitions and shrinks usable timing window.
Ccm (to reference)
Sets how strongly the port drives common-mode currents through local ground/chassis paths; impacts EMC and susceptibility.
Lpkg / ESL + return-path inductance
Forms resonance with capacitance and creates overshoot/ringing. Return-path inductance often dominates when the clamp loop is long.
ΔC (match / imbalance)
Primary cause of differential-to-common-mode conversion. Small mismatch can raise common-mode noise and degrade stability even if “total C” looks acceptable.
Parameter card — datasheet fields mapped to engineering meaning
Use worst-case conditions (bias/temperature) for channel budgets. Use clamp fields for reliability, not for edge shaping.
Field: Capacitance (C) with conditions
Meaning: proxy for Cdiff and per-line capacitance. Always interpret with the stated test voltage and frequency.
Failure mode: edges slow, top data-rate fails first.
Verification: compare step response and settling time with/without TVS on real harness.
Field: Line-to-line match (ΔC / tolerance)
Meaning: controls imbalance and differential-to-common-mode conversion.
Failure mode: common-mode noise rises, EMI/susceptibility worsens, sporadic errors appear.
Verification: inspect asymmetry (unequal overshoot/settling) across the two wires.
Field: Leakage current (Ileak)
Meaning: low-power risk factor, especially with temperature. Use max at hot and relevant bias.
Failure mode: standby current budget breaks, false wake patterns become harder to attribute.
Verification: measure sleep Iq across temperature with bus lines biased to the system’s worst case.
Field: C(V) behavior (capacitance vs bias)
Meaning: defines worst-case Cdiff/Ccm under operating bias. Typical C at 0 V is not sufficient for budgeting.
Failure mode: designs pass on bench but fail with different bias, harness, or temperature.
Verification: validate under the same common-mode and supply conditions used in the vehicle.
Field: Dynamic resistance (Rdyn) / clamp voltage (Vclamp)
Meaning: reliability and energy handling during ESD/Surge events. These fields do not define normal edge shaping.
Use: select for protection strength, then verify parasitic impact with the channel model and measurements.
Worst-case rule (budgeting)
For channel budgets, use C and Ileak at the stated worst-case bias and temperature. Use Rdyn/Vclamp for protection survivability gates, not for signal-integrity budgeting.
Diagram — TVS array parasitic model (differential + common-mode paths)
The diagram shows the minimum structure needed to reason about edge rate, ringing, and differential-to-common-mode conversion.
A “low-C” TVS can still break margin if ΔC is uncontrolled or if Lpkg/return-path inductance creates a new resonance point.
H2-4 · Parasitic Model for CMC & Split Termination
Why EMI can improve while communication gets worse
CMC and split termination primarily shape common-mode impedance and return currents. If the implementation introduces imbalance (DM leakage) or forms a new resonant network with TVS capacitance and layout inductance, differential integrity can degrade even when some EMI bands improve.
CMC model card — the key is imbalance, not “big impedance”
DM leakage (imbalance)
The failure driver: differential energy leaks into common-mode (or vice versa), raising susceptibility and error rate.
Leakage inductance
Adds phase delay and can create ringing with port capacitance; impacts high-rate margin.
DCR
Mainly a loss/thermal term. It can reduce edge amplitude and contribute to heating under fault conditions.
Saturation
Under strong common-mode events, choke behavior can change abruptly—often observed as “sporadic” instability.
Split termination card — common-mode shaping can create resonance
A split termination (midpoint-to-reference C/RC) changes common-mode impedance and return currents. If the midpoint return path is long or referenced inconsistently (GND vs chassis), the network can combine with TVS capacitance, CMC leakage, and layout inductance to form a resonant peak that hurts differential stability.
Placement note (return path dominates)
The midpoint capacitor is only effective when its return path is short and tied to the intended reference. “Same values” can behave differently with different loop areas.
Common misuses checklist (CMC / split termination)
Misuse: placing CMC on a stubbed branch
Why it hurts: the stub becomes a resonant section; differential ringing increases.
Symptom: top-rate fails first; ringing frequency shifts with harness changes.
Misuse: midpoint capacitor return is long
Why it hurts: return inductance dominates; “common-mode shaping” turns into a new resonant peak.
Symptom: EMI may improve in one band, but sporadic errors increase.
Misuse: “CMC swap” without imbalance control
Why it hurts: DM leakage converts energy into common-mode; susceptibility rises.
Symptom: stable on bench, fragile on real harness or in RF fields.
Misuse: mixed references (GND vs chassis) without a plan
Why it hurts: return currents take uncontrolled paths; loop area and coupling change.
Symptom: results vary by mounting and harness routing; repeatability collapses.
Diagram — CMC ideal behavior vs DM leakage (imbalance)
The choke should block common-mode currents. Imbalance creates a leakage path that pollutes differential signaling.
Diagram — split termination midpoint return path (reference is the design)
The midpoint capacitor only behaves as intended when the return path is short and tied to the planned reference (local ground or chassis).
Split termination is not only a value choice; it is a return-path design. Different reference points produce different common-mode impedance and resonance.
Next step (to keep evidence-driven)
After modeling TVS/CMC/split networks, the next chapters should enforce placement and budgeting so that BOM changes cannot silently create new resonance or imbalance.
H2-5 · Bus Sensitivity Map
Same parasitics, different buses — sensitivity is not equal
This section ranks which bus gets fragile first under the same port parasitics. No protocol deep-dive—only physical-layer mechanisms:
Cdiff (edge bandwidth), ΔC (imbalance), Ls (ringing/reflection), and CM return (common-mode loop).
How to use this map
Control the primary sensitivities first (layout + matching), then verify with the fastest “first check” listed on each bus card.
CAN Classic
Card
Rate / edge character
Low–Medium bandwidth; typically more margin than high-rate variants.
Most sensitive parasitics
CM return + Ls (ringing/overstress), then ΔC (conversion).
Design focus
Keep clamp loop small; avoid protection-induced impedance steps.
Fastest first check
Overshoot/ringing asymmetry and common-mode rise under real harness events.
CAN FD
Card
Rate / edge character
Higher bandwidth; data phase margin shrinks quickly when edges degrade.
Most sensitive parasitics
Cdiff + Ls (resonance + window loss), then ΔC.
Design focus
Minimize stub and clamp-loop inductance; validate on real harness at top rate.
Fastest first check
Errors appear at top rate but disappear when downshifted; check ringing and settling vs sample window.
CAN SIC / SIC-XL
Card
Rate / edge character
Waveform integrity depends more on symmetry and controlled common-mode behavior.
Most sensitive parasitics
ΔC + CM return (conversion and susceptibility), then Ls.
Design focus
Match the protection network; keep reference consistent; avoid imbalance from CMC/TVS swaps.
Fastest first check
EMI improves after a BOM swap but error rate rises; inspect symmetry and common-mode rise.
CAN XL PHY
Card
Rate / edge character
Highest sensitivity group; port network behaves like a high-speed channel element.
Most sensitive parasitics
Cdiff + Ls + ΔC can all be first-order limiters.
Design focus
Enforce strict placement and matching rules; require BOM-change regression for the port network.
Fastest first check
“Looks OK” on a scope but margin collapses under load/harness; check settling and resonance shift with small parasitic changes.
LIN
Card
Rate / edge character
Single-wire; slew controlled; behavior strongly depends on reference and coupling.
Most sensitive parasitics
CM return + clamp-loop Ls; watch leakage / bias for low-power budgets.
Design focus
Define a clean reference strategy (GND vs chassis); budget leakage at worst-case temperature/bias.
Fastest first check
Sleep current or false-wake anomalies across temperature; inspect return path and leakage gates.
FlexRay
Card
Rate / edge character
High-rate and topology dependent; extra impedance steps become critical.
Most sensitive parasitics
Ls (reflection) + Cdiff (window/phase), then CM return for EMC coupling.
Design focus
Avoid protection-induced impedance steps; validate worst-case topology (bus/star) with the port network assembled.
Fastest first check
Failures correlate with topology changes; inspect reflection points and added “steps” from CMC/TVS/termination placement.
Sensitivity priority list (for selection + layout decisions)
High-rate buses (CAN FD / CAN XL / FlexRay): prioritize Cdiff and Ls control first, then ΔC.
SIC variants: prioritize ΔC and CM return.
LIN: prioritize CM return and leakage gates.
Diagram — sensitivity map (Low / Med / High)
Each row is a parasitic type; each column is a bus. Levels are qualitative (no numeric values).
H2-6 · Placement Rules
“Close placement” must be a reviewable rule, not a slogan
Placement rules target three failure drivers: stub resonance, clamp-loop inductance, and reference inconsistency.
The port network is treated as a channel segment: connector → TVS → CMC → termination → transceiver.
Rules card (Do / Don’t)
DO: keep TVS on the main path near the connector
Reason: clamps incoming energy early while avoiding an extra impedance step.
DON’T: create a long branch to the TVS
Risk: the branch becomes a stub resonator; high-rate margin collapses first.
DO: minimize TVS return loop (short, wide, many vias)
Reason: effective clamp speed is limited by loop inductance; large loop area weakens protection and worsens overshoot.
DO: place CMC between connector and transceiver on the main route
Reason: reduces harness-driven common-mode currents while keeping the differential route contiguous.
DON’T: place CMC on a stub or after a branching point
Risk: the choke becomes part of a resonant branch and adds a new reflection step.
DO: keep termination and reference strategy consistent
Reason: mixed references (GND vs chassis) and long midpoint returns can introduce common-mode resonance and instability.
Placement pass criteria (X placeholders)
TVS branch / stub length ≤ X
Measured as distance from main trace to TVS pins (shortest electrical path).
TVS return loop (length or loop-area proxy) ≤ X
Use via stitching + short, wide return to the intended reference.
Return vias count ≥ X (parallel)
Parallel vias reduce effective inductance of the clamp loop.
No reference-plane split under the port network (boolean gate)
Avoid forcing return currents to detour around gaps.
Differential symmetry through protection path (skew) ≤ X
Prevent ΔC/ΔL sources from routing asymmetry.
Diagram — PCB top view: correct vs wrong placement (stub + return loop)
The same BOM can behave differently when placement changes the stub length and clamp-loop inductance.
H2-7 · Parasitic Budgeting
Turn C / L / mismatch into acceptance criteria (X placeholders)
A parasitic budget is not a universal number. It is a worst-case envelope bound to a specific
target bus, data-rate, harness condition, and termination network.
The budget must be verifiable with a defined method (A/B build, step response, TDR, or common-mode check).
Key rule
ΔC mismatch often breaks systems faster than “large C” because it converts differential energy to
common-mode, raising EMI and reducing immunity margin.
Cdiff budget
Budget card
What it controls
Differential edge bandwidth and settling. Excess Cdiff slows edges and reduces the usable sample window after reflections.
Worst-case scope
Bound to target bus, data-rate tier, harness condition class (X), termination stack, and temperature/bias states.
Acceptance (X)
Allowed Cdiff ≤ X
How to validate
Step response / edge settling check at the transceiver pins, plus A/B build comparison across the full harness condition.
ΔC match budget
Budget card
What it controls
Symmetry and DM→CM conversion. ΔC imbalance raises common-mode current, worsening EMI and reducing immunity margin.
Worst-case scope
Includes TVS channel-to-channel match plus layout implementation error (routing symmetry, via count parity, pad geometry).
Acceptance (X)
Allowed ΔC ≤ X
How to validate
A/B build common-mode rise comparison, CM current proxy measurement, and EMI delta correlation after protection BOM swaps.
Lseries budget
Budget card
What it controls
Resonance frequency, overshoot peak, and ring-down time. Ls comes from package, pins, vias, and clamp-loop geometry.
Worst-case scope
Includes clamp-loop inductance and any added series elements from CMC placement and reference detours.
Acceptance (X)
Allowed Ls ≤ X
How to validate
Overshoot and ring-down acceptance at the receiver pins under worst-case harness; compare resonance shift after small layout/BOM changes.
Example — back-solve budgets from margin targets (all placeholders)
Step 1: define target
Target bus + data-rate tier + harness class (X) + topology notes (stub/branch).
Step 2: translate to constraints
Required settling time ≤ X, allowed ringing window ≤ X, common-mode rise ≤ X.
Step 3: allocate budgets
Map constraints to allowed Cdiff (X), allowed ΔC (X), allowed Ls (X).
Step 4: choose + implement
Select TVS/CMC meeting budgets, then enforce placement gates (stub/return symmetry).
Step 5: validate
A/B builds, step response, TDR, and CM-noise checks define pass/fail acceptance.
Deliverable — parasitic budget template (field list)
- Target bus: Classic / FD / SIC / XL / LIN / FlexRay
- Data-rate mode: nominal + high-rate tier (X)
- Harness condition class: length / stub / load notes (X)
- Termination network: end values + split termination + midpoint C/RC (X)
- Protection stack: TVS + CMC ordering + placement notes
- Allowed Cdiff: X
- Allowed ΔC: X
- Allowed Ls: X
- Validation method: A/B build, step response, TDR, CM noise proxy
- Acceptance rule: pass/fail gating with X placeholders
H2-8 · Selection Logic
Protection strength vs signal integrity — enforce gates, not opinions
Selection must follow a closed-loop flow: bus sensitivity → threat level → rate tier →
isolation → TVS + CMC combination → placement rules → validation.
Split termination and midpoint capacitors are treated as part of the common-mode network and must be co-designed.
Decision tree (If / Then)
IF: high-rate tier (FD / XL / FlexRay)
THEN: select TVS with low Cdiff and strict ΔC match; treat package/pins as part of Ls budget; require A/B regression.
IF: SIC / immunity-driven designs
THEN: prioritize ΔC and DM leakage / imbalance gates; avoid CMC/TVS choices that improve EMI but break symmetry.
IF: low-power domains (LIN / selective wake)
THEN: enforce leakage worst-case gate and bias-dependent behavior review; reference strategy (GND vs chassis) must be explicit.
IF: split termination / midpoint capacitor present
THEN: require common-mode resonance sanity check; midpoint return path must meet length/loop gate (X); validate with CM-rise delta.
ALWAYS
Enforce budget gates (Cdiff / ΔC / Ls) and placement gates (stub / return loop / symmetry). Confirm on the real harness.
Parameter priority (Top 5 specs)
TVS
Top 5
- Cdiff / Ccm: must fit the Cdiff budget (X) for the data-rate tier.
- ΔC match: primary gate to prevent DM→CM conversion and EMI/immunity collapse.
- Package / pin structure: drives Ls and layout realizability; treat as part of the channel.
- Protection capability: current/energy is reliability dimension; avoid over-sizing that violates budgets.
- Leakage (worst-case): enforce for low-power domains; include temperature and bias corners.
CMC
Top 5
- CM impedance curve: target band behavior matters more than a single number.
- DM leakage / imbalance: gate to preserve symmetry and avoid SIC / high-rate fragility.
- DCR: impacts drop/heat and can signal trade-offs against leakage and size.
- Saturation behavior: ensure the chosen choke does not become a weak link under events.
- Package + placement feasibility: must allow short routes, parity vias, and controlled loop area.
Selection pass criteria (X placeholders)
TVS ΔC ≤ X (primary)
Prevents DM→CM conversion and EMI/immunity instability.
TVS Cdiff ≤ X (by rate tier)
Keeps edge/settling within the sample-window constraint.
TVS leakage ≤ X (low-power only)
Enforce at worst-case temperature and bias.
CMC DM leakage grade ≤ X
Maintains symmetry; avoids “EMI better but data worse” outcomes.
If split termination: midpoint return ≤ X
Prevents CM resonance and return detours.
Diagram — selection decision tree (bus → environment → rate → isolation → TVS/CMC combo → gates)
H2-9 · Simulation & Correlation
Convert parasitics from guesses into evidence
Correlation is a closed-loop chain: model → simulation → bench → real harness → system.
Each step must align the same observable(s): edge settling, reflection magnitude, common-mode rise, and error counter trends.
Boundary
For signal integrity correlation, prefer frequency-aware behavior (S-parameters) when high-rate details matter.
Use simplified SPICE for trend scans and budget sensitivity, not for final harness-level proof.
Model sources
What to use
Simplified SPICE
Best for budget sensitivity scans (Cdiff / ΔC / Ls) and directional comparisons (A vs B protection stacks).
Not suitable for fine high-rate ripple/resonance details.
S-parameters (S2P / S4P)
Best for frequency-dependent insertion loss, reflections, and DM↔CM conversion.
Use when harness-level behavior and high-rate fragility must be reproduced.
Key note
Clamp parameters (Vclamp / Rdyn) are protection-domain properties; they do not replace Cdiff / ΔC / Ls gates for SI.
Correlation methods
How to align
- TDR / step response: align impedance discontinuities and settling/ringing windows to the parasitic budgets.
- Differential probing: confirm edge speed and overshoot at the receiver pins; keep probe loading consistent.
- Common-mode trend checks: observe DM→CM conversion sensitivity to ΔC mismatch and placement symmetry.
- Real harness vs bench cable: bench proves local behavior; harness proves branches, return paths, and worst-case reflections.
Alignment targets (examples)
Use the same observable across all levels: edge settling, reflection amplitude, CM rise, and error counter stability.
Replace “works/doesn’t work” with measurable pass/fail gates (X placeholders).
Common pitfalls
Self-deception traps
Probe loading
Differential probes and short ground connections add C/L and can “clean up” edges artificially.
Keep the measurement system identical for A/B comparisons.
Wrong reference point
Confusing ground/chassis/reference plane invalidates CM conclusions and masks midpoint-cap return issues.
Always document the reference used.
Fixture parasitics dominate
Long adapters and test fixtures can hide device differences. Establish an empty-fixture baseline before part comparisons.
Deliverable — correlation checklist (tickable)
- Model type documented (SPICE / S-parameter) with the intended frequency/rate scope.
- Connector + vias + return path elements included in the interconnect model.
- Observables chosen map to budgets: edge settling (Cdiff), CM rise (ΔC), ringing (Ls).
- TDR/step response uses the same fixture baseline for all A/B comparisons.
- Probe type and loading recorded; measurement system is constant across runs.
- Reference point (GND plane vs chassis) is explicit for each capture.
- Bench cable results treated as local evidence only; harness sweep is mandatory for final sign-off.
- Harness class (X) and topology (stub/branch) recorded with each dataset.
- Error counters logged with a stable window; pass/fail uses an X threshold, not “feels stable”.
- Post-event degradation runs captured (before/after ESD or surge) with identical conditions.
Diagram — correlation chain (model → sim → bench → harness → system → back to model)
H2-10 · Verification & Test Hooks
Make verification a design feature, not an afterthought
Verification must be anchored to measurable gates: edge/overshoot, reflection, common-mode trend, and error counter stability.
Test hooks (TPs and logs) turn those gates into repeatable sign-off evidence.
Test hooks (measurement + logging)
TPs around TVS
Place test points before and after TVS to separate port-side disturbances from downstream ringing and to validate clamp-loop behavior.
TPs around CMC
Place test points before and after CMC to detect DM leakage / imbalance and to isolate “CMC improves EMI but harms data” cases.
TPs at transceiver pins
Treat the transceiver pins as the final judge point for edge settling, overshoot, and reflection acceptance gates.
Logs and event tags
Record error counters and tag events (ESD/surge/temperature/harness changes) to enable post-event degradation checks.
Test plan (sequence)
- Baseline: capture waveforms and counters with a controlled bench setup (fixture documented).
- Harness sweep: repeat the same observables on representative worst-case harness conditions (X classes).
- Stress + degradation: compare before/after ESD or surge, and across temperature; sign-off uses margin deltas, not only “still works”.
Must-measure set
Edge speed and overshoot, reflection/ringing settle time, common-mode trend, and error counter stability.
Capture the same set across baseline, harness sweep, and post-event checks.
Deliverable — verification table fields (X placeholders)
- Overshoot: ≤ X (measured at transceiver pins)
- Ringing settle: ≤ X ns (window definition recorded)
- Step response settling: ≤ X (same fixture + probe across runs)
- Common-mode trend: ≤ X (proxy metric + reference point defined)
- Error counters: stable within X per time window Y
- Post-event degradation: margin drop ≤ X (before/after ESD or surge)
Diagram — test point placement (TPs before/after TVS, CMC, and at transceiver pins)
.
H2-11 · Engineering Checklist (Design → Bring-up → Production Gates)
This checklist enforces repeatable port-protection quality by requiring evidence at three gates:
Design Gate
Bring-up Gate
Production Gate
Focus stays strictly on parasitics (Cdiff / Ccm / Lseries / ΔC, ΔL) and how TVS/CMC/termination placement preserves edge-rate and SI margin.
Focus stays strictly on parasitics (Cdiff / Ccm / Lseries / ΔC, ΔL) and how TVS/CMC/termination placement preserves edge-rate and SI margin.
Design Gate
Lock model + budget + layout rules
Check item
- Reference definition: define the protection return reference (chassis / shield / ECU ground) and the exact return path policy.
- Protection stack locked: TVS type + CMC + termination/split network decided with footprints that preserve symmetry (ΔC/ΔL minimized).
- Parasitic budget written: allowed Cdiff / allowed ΔC / allowed Lseries (all as X placeholders) mapped to target bus + harness condition.
- Placement rules executable: “close placement” becomes measurable (stub length, return loop length/inductance, pair symmetry).
- Test hooks planned: TP locations before/after TVS and before/after CMC; probe loading and bandwidth constraints documented.
Quick method
- Schematic + stack review: confirm TVS is connector-side and CMC/termination are placed on the main trunk (not on a stub).
- Footprint symmetry audit: verify paired pins, matched routing length, and matched reference copper under both lines.
- Return loop visualization: highlight TVS-to-reference loop and confirm it is short, wide, and low-inductance.
Pass criteria (placeholders)
- Defined budgets exist: allowed Cdiff ≤ X, allowed ΔC ≤ X%, allowed Lseries ≤ X (with “worst-case harness” stated).
- Layout rules captured: TVS stub length ≤ X, TVS return loop length ≤ X (or equivalent inductance ≤ X), pair skew ≤ X.
- Test hooks reserved without adding new stubs beyond X.
Owner (role)
Hardware EE (schematic + footprint), SI/PI (budget + stub/return), EMC (emission/immunity trade), Validation (test plan), ME/DFM (assembly constraints).
Reference BOM examples (MPN)
Use as starting points; final choice must satisfy the project’s parasitic budget (Cdiff/ΔC/Lseries) and the intended stress profile (ESD/Surge).
- CAN/CAN FD/FlexRay (low-C TVS): Nexperia PESD2CANFD24LT-Q; ST ESDCAN01-2BLY; Littelfuse AQ24CANFD / AQ24COM-02.
- CAN (surge-focused TVS option): Littelfuse SM24CANB.
- LIN (single-line TVS): TI ESD1LIN24-Q1; ST ESDLIN03-1BWY; Littelfuse AQ24-01FTG.
- CMC (AEC-Q200 examples): TDK ACT45B-510-2P-TL003; Murata DLW21SN900SQ2L; Würth 744232090.
- Split termination resistors (AEC-Q200 example): Panasonic ERJ-3EKF60R4V (use 2× for split termination; value is a design choice).
- Midpoint capacitor (AEC-Q200 example): Murata GCM1885C1H472JA16D (4.7 nF, C0G/NP0, 0603).
Bring-up Gate
Turn budgets into measurements
Check item
- Step/TDR correlation: capture reflection/stub signatures with TVS/CMC populated vs depopulated.
- Edge integrity at pins: measure edge rate, overshoot, ringing settle time at transceiver pins (not only at connector).
- Common-mode trend: observe CM noise tendency when swapping TVS/CMC lots (ΔC/imbalance often shows up as CM growth).
- Stress-before/after delta: after ESD/surge exposure, repeat the exact captures to detect “passed but degraded” behavior.
Quick method
- Two-probe discipline: differential probe for pair; separate high-bandwidth probe for CM reference checks (avoid “false CM” from bad reference).
- Fixture control: use the same fixture/cable whenever comparing component variants; log fixture parasitics.
- Harness realism: correlate bench cable results against a representative harness early (bench-only correlation is commonly misleading).
Pass criteria (placeholders)
- Overshoot ≤ X, ringing settles ≤ X ns, edge target met within X (defined at transceiver pins).
- Correlation holds across setups: TDR/step signatures match within X% between simulation and bench.
- After stress, the delta stays within X (no “silent degradation”).
Owner (role)
Validation/Lab (captures + stress), SI (correlation + interpretation), Hardware EE (rework variants), EMC (scan + immunity checks).
Production Gate
Prevent drift: lot-to-lot + assembly parasitics
Check item
- AVL enforcement: TVS/CMC exact MPN and package revision controlled; substitution requires parasitic re-qualification.
- Assembly symmetry: solder fillet and pad wetting balanced on both lines (uneven solder can create ΔC/ΔL).
- SPC hooks: sample-based waveform capture or error-counter trend check on production lots.
- Stress audit sampling: periodic ESD/surge audit and “after-stress delta” check to catch creeping fragility.
Quick method
- Incoming scan: reel label + date/lot capture; verify against approved list.
- AOI focus points: TVS orientation, CMC placement, split termination routing/return via presence.
- Golden board compare: compare step response or ringing signature to a golden reference board.
Pass criteria (placeholders)
- Variant control: substitutions trigger re-qualification; no uncontrolled alternates.
- Waveform fingerprint stays within X of golden board (overshoot/ringing/settle signature).
- Error counters remain stable within X per test window under defined harness + temperature sweep.
Owner (role)
Manufacturing/Process (AOI + assembly controls), Quality (AVL/SPC + audits), Validation (golden board + re-qualification), Hardware EE (ECO ownership).
Gate Funnel (evidence required at each step)
Evidence is mandatory because parasitics drift with layout, assembly, and component variation.
H2-12 · Applications (Protection Stack Patterns by ECU/Harness Context)
These patterns describe what to combine (TVS / CMC / termination network) and what parasitic pitfalls to avoid.
They do not expand into protocol specifics; each pattern points back to placement/return and parasitic budgeting.
Powertrain / Chassis (long harness, harsh EMC)
Environment: long harness, high dI/dt domains, stronger surge/ESD exposure, frequent ground offsets.
Priority risk: common-mode radiation + after-stress fragility; margin loss from return inductance and ΔC mismatch.
Priority risk: common-mode radiation + after-stress fragility; margin loss from return inductance and ΔC mismatch.
Recommended stack
- Low-C TVS at connector side + tight chassis return.
- CMC on the main trunk (avoid stub placement); validate DM leakage impact under worst-case harness.
- Split termination (if used): keep midpoint return short and controlled.
MPN examples:
TVS: PESD2CANFD24LT-Q / ESDCAN01-2BLY / AQ24CANFD.
CMC: ACT45B-510-2P-TL003 / 744232090.
Split R: ERJ-3EKF60R4V (2×). Mid cap: GCM1885C1H472JA16D.
Body / Comfort (low-power, false-wake sensitive)
Environment: many small ECUs, sleep-heavy usage, frequent human ESD events (connectors, servicing).
Priority risk: standby leakage and imbalance-driven false wakes; “EMI improved but SI worse” after alternate sourcing.
Priority risk: standby leakage and imbalance-driven false wakes; “EMI improved but SI worse” after alternate sourcing.
Recommended stack
- Low-leakage TVS chosen with a clear “worst-case leakage” definition for the sleep rail policy.
- CMC optional (use only when emission/immunity needs it; verify it does not close the sampling window).
- Strict AVL control to prevent ΔC-driven behavior shifts across lots.
MPN examples:
LIN TVS: ESD1LIN24-Q1 / ESDLIN03-1BWY / AQ24-01FTG.
CAN TVS: PESD2CANFD24LT-Q / AQ24COM-02.
CMC: DLW21SN900SQ2L (space-saving).
Gateway / TCU (dense multi-port, service exposure)
Environment: many ports close together, high connector touch probability, frequent maintenance/diagnostics cycles.
Priority risk: layout crowding creates hidden stubs and shared return inductance; cross-port coupling elevates common-mode.
Priority risk: layout crowding creates hidden stubs and shared return inductance; cross-port coupling elevates common-mode.
Recommended stack
- Per-port TVS with short, dedicated return to the intended reference; avoid sharing a long return trace among many ports.
- CMC placement aligned per-port to prevent asymmetric routing and unintended stubs.
- Golden-board fingerprint required for alternate sourcing (TVS/CMC).
MPN examples:
TVS: ESDCAN01-2BLY / AQ24COM-02 / PESD2CANFD24LT-Q.
CMC: ACT45B-510-2P-TL003 / DLW21SN900SQ2L.
Sensors / Actuators (small PCB, connector very close)
Environment: tight space, short routing distances, limited ground/chassis stitching options.
Priority risk: “close placement” is easy, but return inductance and pad asymmetry dominate (ΔC/ΔL from layout details).
Priority risk: “close placement” is easy, but return inductance and pad asymmetry dominate (ΔC/ΔL from layout details).
Recommended stack
- TVS first with the shortest possible return; prioritize symmetrical pads and symmetrical reference copper.
- CMC only if needed; if used, avoid creating a new stub between TVS and transceiver.
- Manufacturing control emphasized: solder imbalance can be a first-order parasitic.
MPN examples:
LIN: ESD1LIN24-Q1 / ESDLIN03-1BWY.
CAN: PESD2CANFD24LT-Q / ESDCAN01-2BLY.
Mid cap: GCM1885C1H472JA16D (when split termination is used).
Protection Stack Patterns (2×2)
Each quadrant shows the same stack (Connector → TVS → CMC → Transceiver) with the pattern’s dominant parasitic risk highlighted.
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H2-13 · FAQs (Port Protection Parasitics, 10–12)
Scope is strictly limited to TVS / CMC / termination networks / placement / parasitics / return paths.
Each answer is a fixed, data-oriented 4-line checklist: Likely cause, Quick check, Fix, Pass criteria (X).
After changing the TVS, CAN FD CRC spikes at full rate but is OK at lower rate — suspect Cdiff or ΔC mismatch first?
Likely cause: ΔC mismatch (imbalance) converting DM→CM and shrinking sampling margin; or higher effective Cdiff slowing edges and increasing ringing sensitivity.
Quick check: Capture step/edge at transceiver pins and compare (old vs new TVS): DM rise/fall symmetry + CM step magnitude; confirm the TVS “ΔC / C(V)” spec is evaluated under the same bias/temperature assumption.
Fix: Prefer a matched low-C array with explicit ΔC control; keep footprint and routing fully symmetric; minimize TVS-introduced stub. Example TVS candidates: Nexperia PESD2CANFD24LT-Q, ST ESDCAN01-2BLY, Littelfuse AQ24CANFD.
Pass criteria (X): At target data rate on representative harness: overshoot ≤ X (at TRX pins), ringing settles ≤ X ns, CM step ≤ X, error counters stable within X per Y minutes (defined window/temperature).
Adding a CMC improves EMI, but intermittent bus-off appears — check DM leakage or resonance first?
Likely cause: CMC DM leakage/imbalance distorting the differential waveform; or a resonance formed by CMC + TVS + split termination midpoint capacitance + harness.
Quick check: Compare step response with CMC populated vs bypassed (same fixture): look for new ringing frequency and longer settle at TRX pins; sweep midpoint capacitor (or RC) and observe whether the ringing peak shifts.
Fix: Select a CMC with lower DM leakage in the relevant band and avoid placing it on a stub; add damping (midpoint RC) if resonance is confirmed. Example CMC candidates: TDK ACT45B-510-2P-TL003, Murata DLW21SN900SQ2L, Würth 744232090.
Pass criteria (X): Ringing settles ≤ X ns and overshoot ≤ X (TRX pins); resonance peak reduced to ≤ X; bus-off rate ≤ X per Y hours on representative harness and temperature sweep.
Same footprint, different TVS vendor makes overshoot worse — which parasitic to verify first?
Likely cause: Different internal leadframe/package inductance (Lpkg) or different Cdiff/ΔC under bias; “same package size” does not guarantee the same high-speed parasitics.
Quick check: Run a controlled A/B: identical fixture/probe, capture step at TRX pins and compare ringing frequency (L-dominant) vs edge-slowing (C-dominant); confirm any ΔC/matching spec is measured at comparable conditions.
Fix: Choose a TVS family with explicit matching control and proven waveform fingerprint; keep pad/via symmetry and minimize via count differences between the pair. Example TVS candidates: PESD2CANFD24LT-Q, ESDCAN01-2BLY, Littelfuse AQ24COM-02.
Pass criteria (X): Waveform fingerprint matches golden board within X (overshoot, ringing frequency, settle time) at TRX pins; error counters stable within X per Y minutes.
ESD testing passes immediately, but the link becomes fragile a week later — fastest degradation confirmation?
Likely cause: Latent damage shifting leakage/C(V)/parasitics; solder micro-cracks or connector wear increasing return inductance; “pass/fail” stayed the same while margin collapsed.
Quick check: Repeat the same capture/log pre- and post-stress on the same harness: step response at TRX pins + CM trend + error counters. Compare the delta, not just pass/fail.
Fix: Tighten the return path (short, wide, stitched to the intended reference), replace suspect TVS/connector lots, and require “after-stress delta” as a gate item in validation and production audits.
Pass criteria (X): After-stress delta ≤ X (overshoot/settle/CM trend); error counters remain within X per Y minutes over Z repetitions; no progressive drift over X days storage/thermal soak.
TVS is placed “very close,” yet protection feels ineffective — what return-path mistake is most common?
Likely cause: The TVS return loop is long/high-inductance (thin trace, distant vias, wrong reference), so the clamp current does not return locally and the transceiver still sees a large transient.
Quick check: Trace the ESD/surge current loop on layout: connector → TVS → reference → back to connector/shield. Verify via stitching density and whether the return jumps planes or detours around cutouts.
Fix: Rework return path first (short, wide copper to the intended reference; via fence/stitching). Only after return is fixed, reconsider TVS strength. Example surge-focused CAN TVS option: Littelfuse SM24CANB (use only if SI budget allows).
Pass criteria (X): Clamp effectiveness at TRX pins: peak transient ≤ X; ground/reference bounce at TRX ≤ X; after-stress delta ≤ X; no new stub beyond X introduced by the return rework.
Changing the split-termination midpoint capacitor degrades communication — CM impedance shift or ringing frequency shift?
Likely cause: Midpoint capacitance changes the common-mode impedance and moves the resonance with TVS/CMC/harness; a “better EMI” setting can narrow sampling margin.
Quick check: Compare step response and CM trend with the old vs new midpoint value; confirm the midpoint return reference and path length (long return often dominates over the capacitor value).
Fix: Restore midpoint value within the parasitic budget, add damping (midpoint RC) if needed, and shorten the midpoint return. Example parts: midpoint cap Murata GCM1885C1H472JA16D, split R Panasonic ERJ-3EKF60R4V (use 2×).
Pass criteria (X): Resonance peak reduced to ≤ X and ringing settles ≤ X ns; CM step ≤ X; error counters stable within X per Y minutes on worst-case harness.
The bus becomes unstable only when harness length increases — suspect CMC saturation, TVS capacitance, or a stub first?
Likely cause: Reflection/stub sensitivity grows with longer harness and reduced margin; TVS Cdiff and added Lseries become more visible; CMC saturation is secondary unless strong CM current exists.
Quick check: TDR/step compare short vs long harness: identify new reflection points and settle time change; temporarily eliminate suspected stubs (TP leads, branch routing, connector-to-TVS detours) and re-capture.
Fix: Enforce stub limits (TVS and CMC must sit on the main trunk), tighten parasitic budgets for the worst-case harness, and choose lower-C/more-matched TVS or lower-leakage CMC only after placement is correct.
Pass criteria (X): On worst-case harness: ringing settles ≤ X ns and overshoot ≤ X (TRX pins); error counters ≤ X per Y minutes; behavior remains stable across Z harness variants.
FlexRay is “only 10 Mbps,” but adding TVS causes edge/jitter anomalies — check package L or probe loading first?
Likely cause: Probe/fixture loading (added C) distorts the edge and exaggerates ringing; or TVS adds Cdiff/Lpkg that reshapes the edge at the transceiver pins.
Quick check: Re-measure with a lower-capacitance probing method and a controlled fixture baseline; compare captures at multiple points (connector-side vs TRX pins) to separate measurement artifacts from real parasitics.
Fix: Fix measurement setup first; then use a low-C matched TVS and a symmetric footprint; avoid long TP leads that create stubs. Example TVS candidates: PESD2CANFD24LT-Q, ESDCAN01-2BLY.
Pass criteria (X): With validated probing: edge target within X, ringing settles ≤ X ns, overshoot ≤ X at TRX pins; no “jitter anomaly” observed across Y minutes logging window.
LIN intermittent false wake: can TVS be involved — check leakage/bias or CM injection first?
Likely cause: TVS leakage under worst-case bias/temperature shifts LIN recessive level; or return-path CM injection creates threshold crossings that look like activity.
Quick check: Measure sleep Iq and LIN recessive voltage with TVS populated vs removed (controlled rework); correlate false-wake events with CM noise snapshots and reference-point stability.
Fix: Use a low-leakage LIN-rated TVS and define leakage acceptance under worst-case conditions; shorten/clean the TVS return path to the intended reference. Example TVS candidates: TI ESD1LIN24-Q1, ST ESDLIN03-1BWY, Littelfuse AQ24-01FTG.
Pass criteria (X): Sleep Iq ≤ X; false-wake rate ≤ X per day (defined temperature); LIN recessive level stays within X; no correlated CM spikes above X during the observation window.
“Stronger” protection makes the system less stable — how can parasitic budgeting explain this?
Likely cause: Higher surge/ESD capability often comes with higher Cdiff/Lseries or worse matching (ΔC/ΔL), which reduces edge-rate and sampling window; EMI can improve while SI margin collapses.
Quick check: Map the chosen TVS/CMC into the parasitic budget fields (Cdiff, ΔC, Lseries, DM leakage) and compare against the target bus/harness worst-case; verify using step response and error-counter trends.
Fix: Separate “protection strength” from “signal parasitics”: prioritize matched low-C parts for the signal path, and use placement/return-path optimization as the first lever; only then escalate surge rating where necessary (with re-correlation).
Pass criteria (X): All protection components stay within budget: Cdiff ≤ X, ΔC ≤ X%, Lseries ≤ X, DM leakage ≤ X; stable error counters within X per Y minutes on worst-case harness.
Connector shield ground differs from signal ground — where should TVS return be tied?
Likely cause: Returning TVS current into the wrong reference injects stress energy into the signal ground, causing ground bounce and CM disturbances at the transceiver; the clamp exists but the loop is wrong.
Quick check: Draw the full stress-current loop and identify the intended low-impedance reference (shield/chassis vs signal ground); measure reference bounce at TRX pins during stress and compare to the connector-side reference.
Fix: For connector-side protection, prioritize a short, stitched return to the connector’s reference (often shield/chassis) while keeping signal ground quiet; enforce a single, reviewed reference policy across TVS, split midpoint, and EMC components.
Pass criteria (X): Reference bounce at TRX ≤ X; CM step at TRX ≤ X; after-stress delta ≤ X; error counters remain within X per Y minutes under defined stress and harness conditions.
Production alternate sourcing (CMC/TVS) reduces yield — how to design a minimal regression test?
Likely cause: Parasitics changed (ΔC/ΔL, DM leakage, C(V)) and shifted the waveform fingerprint; the system still “works” on a short bench cable but fails on production harness variability.
Quick check: Use a golden-board fingerprint: (1) step/TDR signature at TRX pins, (2) CM trend snapshot, (3) error-counter stability window; compare original vs alternate lots under the same fixture and representative harness.
Fix: Enforce AVL with parasitic-critical fields (Cdiff/ΔC/Lseries/DM leakage) and require re-correlation for any change; pre-approve alternates (e.g., PESD2CANFD24LT-Q ↔ ESDCAN01-2BLY, CMC candidates listed in Q2) only after passing the minimal regression suite.
Pass criteria (X): Fingerprint deviation ≤ X (overshoot, settle, ringing frequency, CM step) and error counters within X per Y minutes; after-stress delta ≤ X on sampled units; yield ≥ X% over Z lots.
