Low-C TVS Arrays for CAN/LIN/FlexRay Port Protection
← Back to: Automotive Fieldbuses: CAN / LIN / FlexRay
Low-C matched TVS arrays protect CAN/LIN/FlexRay ports only when coupling and return paths are controlled. This page turns “which TVS to pick” into an explainable flow: define the distortion budget, enforce symmetry, close the energy loop, and validate with repeatable metrics.
What is a Low-C TVS Array for Automotive Ports?
A low-capacitance (Low-C) TVS array is a multi-channel clamp placed at the vehicle port to shunt ESD/EFT/surge energy without pushing the bus waveform beyond its timing and EMI limits. The engineering goal is not “minimum capacitance at any cost”; it is meeting a signal-distortion budget while still closing a short, low-inductance energy-return loop.
Scope Guard (to avoid overlap with sibling pages)
- Included: port-level TVS arrays (Low-C + matched channels), parasitics, placement/return path, coupling-aware reasoning, and waveform impact.
- Not expanded here: CMC / split termination design method (link to the dedicated CMC & split-termination page).
- Not expanded here: transceiver internal shaping/diagnostics or protocol details (link to CAN/LIN/FlexRay transceiver pages).
TVS array vs. single TVS (why arrays matter on buses)
- Channel matching: differential buses penalize asymmetry; unmatched parasitics convert differential energy into common-mode noise and emissions.
- Co-packaged consistency: channels share the same package and thermal environment, improving parasitic consistency over temperature and aging.
- Layout controllability: array pinouts often enable symmetric routing and a tighter, repeatable return path versus discrete single parts spread across the board.
What “Low-C” means in engineering terms
- Budgeted capacitance, not minimum capacitance: Low-C is the capacitance ceiling that keeps edge rate, sample-point margin, and EMI within targets for the real harness load.
- Trade-off is unavoidable: lower capacitance frequently comes with higher dynamic resistance and higher residual clamp voltage, shifting the design burden to return-path quality and placement.
- A port is a system: the effective distortion comes from the TVS array plus package ESL, pads/vias, plane discontinuities, and the harness/termination environment.
Covered ports (port-protection view only)
CAN / CAN FD / SIC / CAN XL (differential), LIN (single-wire), FlexRay (differential).
Focus stays at the connector-to-pin protection chain: energy return and signal integrity.
Practical definitions (use these as the page’s baseline vocabulary)
- Port-level protection: designs the injection-to-return loop at the connector; the clamp is only as strong as the return path it closes.
- Low-C: the maximum allowable added capacitance that preserves edge rate, timing margin, and emissions under the real harness load.
- Matched channels: channels whose parasitics stay sufficiently symmetric so differential-to-common-mode conversion remains below a defined limit (threshold to be filled in later).
- Clamp strength vs. distortion: residual voltage and dynamic resistance compete with capacitance; selection must satisfy both protection and waveform budgets.
- Pass criteria: “communication still works” is not enough; soft errors, false wake, and post-stress degradation must stay within limits (thresholds to be filled in later).
Diagram: ECU port protection chain (signal path vs. energy return)
Threat Model: ESD vs Surge vs EFT — what actually hits the port?
Port protection decisions become consistent only when threats are classified by time scale, energy, coupling method, and repetition. This model prevents misleading “datasheet-only” choices and makes selection and validation align to the same reality.
The 4 axes that matter (use the same axes for every design review)
- Time scale: fast edges stress parasitic inductance; long pulses stress power dissipation and residual voltage.
- Energy: higher energy shifts the problem from “peak voltage” to “where heat and charge go.”
- Coupling: direct discharge and harness/fixture injection produce different return paths and different common-mode behavior.
- Repetition: burst and repeated stress expose soft errors and long-term degradation, not only immediate damage.
Three outcome classes (what “failure” looks like in the field)
1) Hard damage (immediate and obvious)
- Typical symptoms: short/open at the port, abnormal leakage, bus never comes up, permanent bus-off.
- Quick check: static resistance/leakage at the port (threshold placeholder), and a pin-level sanity check on the PHY side.
2) Soft errors (intermittent, often misdiagnosed)
- Typical symptoms: CRC/frame errors, link flaps, false wake, sporadic resets, or error counters climbing only under load.
- Quick check: correlate error counters and bus state transitions to the stress event timestamp (a missing timestamp is a common root cause).
3) Degradation (passes now, fails later)
- Typical symptoms: the design becomes “more fragile” after stress: reduced margin, higher false-wake rate, or higher error rate at the same operating point.
- Quick check: repeat-stress + traffic test and verify the error rate does not trend upward (threshold placeholder, e.g., X per 1k frames over Y minutes).
Threat → typical symptoms → minimum logging set (make results reproducible)
ESD (fast edge, high dv/dt)
- Common symptoms: immediate resets, sporadic frame errors, post-event bus-off, or a “works on bench, fails on harness” pattern.
- Log at minimum: event timestamp, bus state transitions, error counters, wake-source attribution, supply rail dips, and temperature.
Surge (higher energy, longer duration)
- Common symptoms: thermal-driven degradation, leakage increase, latch-up-like behavior, or delayed failures after repeated events.
- Log at minimum: event timestamp, port leakage trend (pre/post), recovery time to stable communication, and any protective shutdown flags.
EFT (burst / repetition)
- Common symptoms: elevated soft-error rate under certain load, false wakes, or failures that disappear when averaging or using a different measurement window.
- Log at minimum: burst parameters (if available), error counters vs. time window, CPU load/scheduling jitter (to rule out “buffer underrun” mimics), and wake-source attribution.
Diagram: ESD vs Surge vs EFT (time scale & repetition)
Next-step hook (keeps the page vertically deep)
Once the threat class is known, the next question becomes: how does the energy couple into the bus and where does it return? The following chapter uses an IEC-style coupling view to make the injection and return paths explicit, so placement and parasitic control can be engineered rather than guessed.
IEC Coupling Models: how the energy couples into your bus
The discharge style (contact vs. air) is only the trigger. The outcome is dominated by return-path geometry and the effective coupling C/L network that injects energy into the bus and closes the loop. A coupling-first view turns “TVS selection” into an explainable, reproducible engineering decision.
What matters in practice (port view)
- Loop area: fast-edge stress becomes voltage through stray inductance; the shortest return loop usually wins.
- Coupling network: the port sees a network of parasitic capacitors/inductors between harness, connector shell, PCB planes, and signal lines.
- Where energy goes: TVS effectiveness depends on where its current is returned (chassis/return network) and how directly it is connected.
Three common coupling paths at automotive ports
Path-1 · Differential injection into the bus pair
Harness → connector pins → PCB traces → PHY input.
Key risk is signal distortion: added capacitance and asymmetry shift edges and sampling margin.
Primary controls are Cdiff and routing symmetry.
Path-2 · Common-mode injection via shield / shell / chassis
Harness shield/ground → connector shell → chassis/return network → PCB planes.
Key risk is common-mode movement that converts into differential noise and emissions.
Primary controls are return-path definition and chassis boundary clarity.
Path-3 · TVS package / pad / via return path
TVS current is only effective if it returns through a short, low-inductance loop.
Package ESL, pad inductance, and long ground routes raise peak residual voltage and re-inject energy into the bus.
Primary controls are placement, via stitching, and loop area minimization.
Why Low-C + matched channels reduce waveform damage
- Cdiff controls edge/timing: excessive differential capacitance slows transitions and erodes sampling margin at higher bit rates.
- Ccm and asymmetry drive common-mode swing: mismatched coupling paths convert common-mode movement into differential noise.
- Matching is a symmetry tool: consistent channel parasitics plus symmetric routing reduce differential-to-common-mode conversion under stress.
Coupling-path checklist (board review “tick box” list)
Step 1 · Define the return destination (where energy must go)
- Chassis/return network boundary is explicitly defined near the connector (no ambiguous “floating” shell).
- A short return path exists from TVS ground to the chosen return destination (plane continuity is verified).
- Plane splits, neck-downs, and long detours are avoided around the port return region.
Step 2 · Check each path (Path-1/2/3)
Path-1 (differential) — symmetry & stubs
- TVS to each line is symmetric (equal trace length, equal via count, mirrored pads).
- No long stubs are introduced between connector and TVS or between TVS and PHY.
- Differential pair reference plane is continuous through the port region (no slot/cut under the pair).
Path-2 (common-mode) — shell & chassis boundary
- Connector shell has a deliberate, short path to chassis/return (not through the signal ground maze).
- Common-mode current has a return path that does not traverse sensitive PHY areas.
- Any chassis-to-signal reference coupling element is intentional and documented (value placeholder).
Path-3 (TVS return) — loop area & via stitching
- TVS ground pad is tied to return with multiple close vias (via-in-pad or tight stitching where allowed).
- The energy loop is visibly small on the layout (no long thin ground trace acting as an inductor).
- Return network is wide, short, and continuous beneath the port region (no bottlenecks).
Diagram: IEC injection → port coupling → return loop (Path-1/2/3)
TVS Array Electrical Behavior: C, Rdyn, Vclamp, Ipp, and leakage
Datasheet parameters become useful only after they are translated into observable waveform changes and measurable system effects such as error counters, false wakes, recovery time, and long-term degradation trends.
Parameter → impact → what should be validated (thresholds are placeholders)
Cj / Cdiff / Ccm (capacitance & symmetry)
- Impact: sets edge-rate reduction, sampling-margin loss, and common-mode swing under stress; asymmetry increases DM↔CM conversion.
- Reality check: capacitance is bias/frequency dependent; “headline C” is not the system effective C under operating voltage.
- Validate: edge-rate change (Δtr/Δtf), overshoot/ringing trend, and CM movement; keep within budget (placeholders).
Rdyn & Vclamp (residual voltage under current)
- Impact: determines residual clamping voltage slope with current; interacts with package/layout inductance to set peak overshoot.
- Trade-off: low Vclamp often conflicts with low capacitance; the “best” part is defined by the system budget, not a single number.
- Validate: peak residual voltage at the PHY pins (placeholder), plus recovery to stable communication after stress.
Ipp / surge rating (energy handling)
- Impact: sets survivability under longer pulses; depends on pulse width and thermal path (package size, copper area, return plane).
- Risk: “same footprint” does not guarantee equal energy robustness; thermal bottlenecks can dominate.
- Validate: post-stress leakage drift, functionality recovery time, and repeated-stress stability (placeholders).
Leakage (standby current & false-wake risk)
- Impact: elevates standby current and can shift thresholds or noise sensitivity in low-power states.
- Temperature tie-in: leakage growth at high temperature can turn an “ESD-pass” design into a field false-wake problem.
- Validate: sleep current delta (placeholder), false-wake rate under stress/noise, and pre/post leakage trend over temperature.
Translation rules that prevent “parameter tunnel vision”
- Capacitance must be treated as a curve: evaluate at the operating bias and relevant frequency content of the bus edge.
- Clamp must be evaluated at the pin: package/layout inductance can dominate the peak; measure or simulate at the PHY pins, not at the TVS symbol.
- Energy robustness is thermal + electrical: copper area, return planes, and pulse width define survivability beyond the Ipp headline.
Bridge to next chapters (keeps vertical depth)
Once parameters are mapped to observable effects, the next step is to constrain them with a
signal distortion budget and then enforce that budget through
placement and return-path layout.
Diagram: TVS array equivalent model (what each parameter influences)
Matching & Symmetry: why array matching matters on differential buses
On differential buses, matching is a baseline requirement. Any left/right asymmetry increases DM↔CM conversion, which can degrade emissions and immunity at the same time. A matched array helps, but only when pads, routing, reference, vias, and return are also symmetric.
Mechanism: how asymmetry creates DM↔CM conversion
- Asymmetry source: unequal line-to-reference coupling (capacitance/inductance/return) between the two wires.
- Conversion: common-mode movement turns into differential noise (and vice versa) through imbalance.
- System effect: higher CM radiation + reduced eye/edge margin → error frames/BER increase under stress.
What “matching” must include (beyond the part number)
- Device channel consistency: same package, same channel geometry, consistent parasitics across lines.
- Pad symmetry: mirrored pads and equal ground connection geometry.
- Routing symmetry: equal length, equal via count, mirrored layer transitions.
- Reference symmetry: continuous reference plane under both lines; avoid one line crossing a split/slot.
- Return symmetry: both lines “see” the same return network impedance and loop area through the TVS ground.
Typical failure mode: same TVS, different layout → error spikes
A matched array cannot compensate for an imbalanced implementation. Common triggers are an extra via on one line,
non-mirrored pads, one trace crossing a plane split, or a return path detour on only one side.
The result is higher DM↔CM conversion and a sudden rise in error frames/BER under stress.
Symmetry 6-point checklist (review-ready)
1) Device
Use a matched array; keep channel mapping consistent (Diff+ / Diff− assigned to symmetric channels).
2) Pads
Mirror pad shapes and ground connections; avoid different pad stubs on the two lines.
3) Routing
Keep equal length and equal via count; maintain mirrored transitions and consistent spacing.
4) Reference
Ensure the reference plane is continuous under both lines; do not let only one line cross a split/slot.
5) Vias
Match via positions and counts; keep a symmetric via fence where used.
6) Return
Both lines must see the same return impedance and loop area through the TVS ground into the return network.
Diagram: symmetric vs asymmetric differential-TV S implementation
Placement & Return Path: the real protection is the loop you close
TVS placement is solved by loop minimization: place the clamp where injected energy can return through the smallest, lowest-inductance loop. A “correct” footprint can still fail if the return path detours through sensitive PCB regions.
Placement decision: connector-side vs PHY-side (return-loop view)
- If the injected energy enters the PCB traces first, it can couple into adjacent nets and planes before it is clamped.
- Connector-side clamping typically reduces coupling by keeping the high-current segment short and close to the boundary.
- Final criterion: choose the placement that produces the smallest return loop to the defined return destination.
Return-path boundary: chassis vs signal ground must be explicit
- Define the return destination (chassis/return network vs signal ground) near the connector boundary.
- Route TVS return directly to that destination using a wide, short, continuous path.
- Avoid “silent detours” where high-current return traverses sensitive PHY or clock regions.
Layout controls (port-protection scope)
- Via stitching at TVS ground: multiple close vias reduce inductance and keep peak residual voltage under control.
- Via fence (where used): symmetric stitching helps confine common-mode current paths near the boundary.
- Reference plane continuity: keep the pair’s reference plane intact; avoid splits/slots near the port.
Placement & return-path review checklist (reusable)
A) Injection & loop
- Injection point (pin/shell) is identified for the port boundary.
- Return loop can be drawn on layout; loop area is minimized (placeholder).
B) TVS placement & return
- TVS is placed to avoid energy traveling deep into PCB before clamping.
- TVS ground uses short, wide return to the defined destination; no thin trace detours.
C) Planes & stitching
- Reference plane continuity is verified under the pair through the port region.
- Via stitching/fence is symmetric where applied; return impedance is controlled near the boundary.
D) Observable hooks
- Measurement/monitor points exist for waveform + CM movement near the PHY pins.
- Error counters and post-stress recovery are logged for comparison (placeholders).
Diagram: placement strategies and the return-loop area that matters
Signal Distortion Budget: how much capacitance is too much?
“Low-C” must map to an allowed distortion budget. The effective port capacitance (TVS + pads + routing + input) interacts with harness and termination to slow edges, move threshold-crossing time, and shrink sampling margin. A budget makes selection and layout bounded and reviewable.
Simplified estimate model (selection boundary, not a simulation replacement)
- Port capacitance: Cport ≈ CTVS + Cpads + Crouting + Cinput (placeholders).
- Edge impact: Cport with harness/termination forms an effective bandwidth limit → Δtr/Δtf (placeholders).
- Sampling impact: slower edge shifts threshold crossing and reduces sample-point window.
- Symmetry impact (differential): Cdiff imbalance increases DM↔CM conversion and can raise emissions while reducing immunity.
Sensitivity focus by bus (port-protection view)
CAN FD / CAN XL
- Edge-rate change can shift effective timing and shrink sampling margin.
- Overshoot/ringing can create false crossings under stress.
- Cdiff asymmetry can increase DM↔CM conversion and degrade margin.
LIN
- The risk is not “fastest edge”; it is threshold noise, glitches, and EMI trade-offs.
- Extra capacitance can reshape slew control behavior and increase false-wake sensitivity.
FlexRay (10 Mbps)
- At 10 Mbps, edge shape and threshold margin are tighter.
- Slower crossing increases timing uncertainty and can reduce receiver decision margin.
Distortion budget template (fill-in placeholders)
Use these placeholders to define an explicit “Low-C” boundary for a given harness/termination and operating mode. The goal is consistent review and repeatable validation.
Cdiff / Ccm
Allowed max:
Cdiff ≤ [____] pF, Ccm ≤ [____] pF
Notes: specify bias/frequency conditions if the datasheet varies; keep channel symmetry constraints explicit.
Edge delta
Allowed:
Δtr ≤ [____] ns, Δtf ≤ [____] ns
Measure at PHY pins under representative harness/load; record bandwidth and probe method.
Overshoot / ringing
Allowed:
Overshoot ≤ [____] %, Ringing ≤ [____] mV
Define the reference window and trigger method to avoid mis-counting transient artifacts.
Common-mode change
Allowed:
ΔVCM ≤ [____] mV, CM swing ≤ [____] mVpp
Track CM behavior across ground conditions; asymmetry often shows up as CM spikes and DM penalties.
Sampling margin proxy
Allowed:
Threshold-crossing shift ≤ [____] ns, Jitter window ≥ [____] ns
Define measurement point (connector-side vs PHY pins); use consistent statistic window and denominator.
Diagram: capacitance slows edges and shifts threshold crossing (sampling margin shrinks)
Validate & Measure: how to test without lying to yourself
“Still communicates after stress” is not a pass. Validation must include counters, false-wake behavior, recovery time, and post-stress degradation. Measurements must control probe/trigger/statistics to avoid self-deception.
Pass definition (port-protection scope)
- Hard fail: permanent damage, latch-up, or loss of communication.
- Soft fail: error frames / retries / resets / false-wake events during or after stress.
- Degradation: “passes once” but becomes more fragile later (trend of counters, timing margin, leakage).
Key test combination set (threat × condition)
1) Board-level injection
Apply ESD/EFT/Surge from a port boundary perspective; keep coupling and return path consistent and documented.
2) Communication stress
Run full load + boundary data rates + temperature points; track counters and recovery time (placeholders).
3) Harness & grounding variation
Repeat with long harness, heavy load, and different ground points; many failures are return-path dependent.
Measurement traps (fast self-check list)
- Probe ground bounce: can fabricate overshoot/ringing; use a low-inductance ground method.
- Bandwidth limits: can make edges look slower (or hide spikes); document bandwidth and probe.
- Trigger/window bias: a narrow capture window can miss rare events; define the observation window.
- Metric denominator mismatch: inconsistent “per time” vs “per frames” can fake improvements or regressions.
- Wrong measurement point: measuring only near the connector can miss stress at PHY pins.
Validation matrix template (fill-in placeholders)
Each line item is a repeatable test definition. Keep threat, conditions, metrics, and pass criteria explicit.
Threat
[ESD / EFT / Surge]
Condition
Harness=[____], Load=[____], Temp=[____], Rate=[____]
Metric
Waveform @ PHY pins + counters + false-wake + recovery time (placeholders)
Pass criteria
Counter delta ≤ [____] / window; false wake = [____]; recovery ≤ [____] ms; waveform budget met.
Threat
[ESD / EFT / Surge]
Condition
Ground point=[____], Variant=[____], Mode=[____]
Metric
CM movement + error counters + reboot/reset logs (placeholders)
Pass criteria
No regression vs baseline; counters stable within [____] over [____] minutes; no false wake.
Logging fields (placeholders): timestamp, harness config, injection method, temperature point, firmware version,
counters window, measurement bandwidth, probe method, and recovery timeline.
Diagram: validation bench (injection + harness + counters logging)
Engineering Checklist: design → bring-up → production
A Low-C TVS array program succeeds only when the budget, symmetry, return path, measurements, and production controls are defined as a repeatable checklist. This section is intended to be copied into any automotive port-protection page.
Phase A — Design (freeze the boundary)
Output: review-ready checkboxes + placeholders
1) Threat & scope boundary
- Target port: CAN / LIN / FlexRay (port-protection view only).
- Threat set: ESD / EFT / Surge with injection method placeholders.
- Return destination must be explicit: chassis / signal ground / defined boundary (placeholder).
2) Distortion budget lock (defines “Low-C”)
- Cdiff/Ccm max: [____] pF / [____] pF (placeholders).
- Waveform deltas: Δtr/Δtf, overshoot, ΔVCM, crossing shift (placeholders).
- Measurement point is frozen: PHY pins for pass decisions.
3) Part screening (array matching first)
- Choose arrays with channel consistency for differential symmetry (packaging + datasheet context).
- Balance Rdyn/Vclamp versus capacitance; avoid “low clamp” without budget justification.
- Leakage vs high temperature and standby/false-wake sensitivity is recorded (placeholder).
4) Placement & return plan (loop is the protection)
- Placement decision uses loop-minimization: connector-side vs PHY-side is justified.
- Ground vias/return path are drawn as a closed loop (no ambiguous “to GND”).
- Via fence / plane continuity rules are defined for the port region.
5) Symmetry rules (6-point check)
- Device channels mapped symmetrically (Diff+ / Diff− are not swapped across packages).
- Pads, routing length, via count, reference plane, and return path are matched.
- Any intentional asymmetry is documented with measured impact (placeholder).
Phase B — Bring-up (measure without bias)
Output: point list + counters + stress sweep
1) Instrumentation & statistics freeze
- Probe method avoids ground-bounce artifacts; bandwidth is documented.
- Denominator/window for metrics is fixed (e.g., per [____] frames over [____] minutes).
2) Mandatory measurement points
- Primary: PHY pins (pass/fail basis).
- Secondary: connector-side and TVS-near points for localization (not pass-only).
3) Counter & event logging
- Error frames / retries / CRC / protocol flags (placeholders).
- False wake, resets, recovery timeline are logged with timestamp and test conditions.
4) Stress sweep and harness substitution
- Full-load + boundary rate + cold/hot points (placeholders).
- Short/long harness and heavy-load variants are compared under identical logging rules.
5) Post-stress degradation check
- Re-run the same waveform budget checks after injection.
- Look for counter drift or increasing sensitivity to harness/ground changes.
Phase C — Production (variation and traceability)
Output: minimum audit set + trace fields
1) Incoming variation control
- Lot/vendor/date-code are recorded (placeholders).
- Spot-check: capacitance consistency and leakage trend at temperature points (placeholders).
2) Second-source policy (must satisfy the same budget)
- Replacement must meet the distortion budget and symmetry constraints.
- Re-validate using the minimum matrix subset (threat × conditions × counters).
3) Sample injection audit
- Run the defined minimum injection set (placeholders).
- Pass criteria include counters, false-wake, recovery time, and post-stress budget checks.
4) Failure traceback fields (make issues reproducible)
- Harness config, ground point, temperature, firmware, bandwidth, probe method, injection method.
- Counters window definition and recovery timeline are stored with timestamps.
Diagram: reusable swimlane flow (Design → Bring-up → Production)
Applications: where low-C arrays pay off most
Low-C matched arrays matter most when the system is sensitive to edge distortion, symmetry loss, or return-path ambiguity. The patterns below remain strictly within a port-protection scope.
Scenario
Powertrain / Chassis (CAN FD/XL on heavy harness)
Risk
- Edge distortion shrinks sampling margin under load and temperature.
- Symmetry loss increases DM↔CM conversion and can worsen both emission and immunity.
- Harness-dependent ringing causes false crossings at boundaries.
Recommended strategy
- Lock a distortion budget (Cdiff/Ccm + waveform deltas) before part selection.
- Enforce symmetry at device, pads, vias, and return paths.
- Validate with the real harness and boundary modes; use counters and recovery metrics.
Scenario
Body / Comfort (low-power + false-wake sensitive)
Risk
- Leakage at temperature increases standby loss and raises sensitivity to policy thresholds.
- Glitches near threshold can produce false wake events.
- Inconsistent metric denominators can hide regressions.
Recommended strategy
- Treat leakage and false-wake as first-class pass metrics (placeholders).
- Define observation windows and trigger rules to catch rare wake events.
- Re-test after injection to detect degradation trends.
Scenario
HV / e-drive (ground potential differences)
Risk
- Return-path ambiguity can route energy through sensitive domains.
- Harness and ground point changes dominate behavior.
- Validation may pass on bench but fail in real ground-offset conditions.
Recommended strategy
- Define the return destination and boundary explicitly; minimize loop area at the port.
- Repeat validation across ground points and harness variants.
- Track CM movement and recovery metrics as primary indicators.
Diagram: application map (where Low-C + symmetry is most valuable)
IC Selection Notes: picking a Low-C TVS array (with sanity checks)
This chapter turns “low-capacitance TVS array selection” into a repeatable gate-and-verify flow for automotive ports (CAN/CAN-FD/SIC/XL, LIN, FlexRay), without drifting into transceiver design details.
A · Hard Gates (fail fast)
If any gate is violated, the candidate is rejected before trade-offs.
- Voltage & operating state gate: VRWM / working bias must match the port’s real recessive/common-mode conditions (include sleep/partial-network states as applicable). Keep a single “allowed bias window” entry in the design doc.
- Leakage@T gate (power & false-wake guard): define leakage max at high temperature (placeholder: ILEAK ≤ X at T = Y°C). Leakage slope matters more than room-temp typical.
- Capacitance budget gate: enforce a hard limit from the signal distortion budget (H2-7). Use placeholders to keep the page protocol-agnostic: Cdiff ≤ X pF, ΔC(match) ≤ Y pF, Ccm ≤ Z pF.
- Threat alignment gate (ESD/EFT/Surge): the rating must align with the chosen coupling/injection plan (IEC model) and the validation matrix. Avoid “pass once” criteria—use repetitive stress + post-stress behavior metrics.
- Automotive grade gate: AEC qualification and temperature range must match the ECU environment and production policy (documented as a hard requirement).
Sanity check (quick):
if a datasheet only shows one capacitance point, require a “capacitance vs bias/frequency” confirmation step (vendor curve, bench measurement, or both) before freezing the BOM.
B · Trade-offs (waveform outcomes)
Translate datasheet knobs into “what changes on the bus.”
- Vclamp vs C: lower clamp often costs capacitance. If Cdiff budget is tight, prioritize staying inside the budget over chasing the lowest clamp number.
- Rdyn (residual voltage control): dynamic resistance shapes residual voltage under stress. Its practical benefit is limited if the board return loop is large (placement/return path dominates).
- Package parasitics (Lpkg) & layout feasibility: a “good” part can underperform if the footprint cannot realize tight, symmetric routing and short return. Treat package + footprint as one decision.
- Channel matching & symmetry: mismatched channels convert differential energy into common-mode (hurts emission and immunity simultaneously). Prefer parts explicitly aimed at in-vehicle networks with matched capacitance behavior. :contentReference[oaicite:0]{index=0}
Sanity check (quick):
if “same footprint” is the only equivalence argument, the candidate is not considered equivalent—require re-validation (Step 5) for any substitution.
C · Second-source guardrails (must re-check)
Minimum re-check set before approving alternates.
- Cdiff (and test conditions): stay within the budget limit from H2-7; confirm bias/frequency dependence.
- Rdyn / clamp behavior: ensure residual voltage behavior does not change under the chosen injection/coupling model.
- Leakage@T: verify worst-case at high temperature against standby current and false-wake policy.
- Package parasitics & pinout symmetry: confirm the package/leadframe does not force asymmetric routing or longer loops.
- Channel-to-channel matching: confirm matching (or max delta) rather than typical values only.
Risk note: Same footprint ≠ same waveform. Any alternate must re-run the minimum validation subset (Step 5) on the real harness and grounding strategy.
D · Concrete material examples (sanity list)
Verify package/suffix/qualification and local availability before freezing BOM.
In-vehicle network focused (dual-line, matched behavior):
- TI: ESD2CANFD24-Q1, ESD2CANXL24-Q1, ESD2CAN24-Q1 (automotive dual-line ESD TVS for in-vehicle networks; variants cover CAN-FD and CAN-XL). :contentReference[oaicite:1]{index=1}
- Nexperia: PESD2CANFD24U-U, PESD2CANFD24UU-QX (automotive ESD protection for in-vehicle network bus lines; marketed for CAN/CAN-FD/FlexRay/SENT protection families). :contentReference[oaicite:2]{index=2}
- ST: ESDCAN03-2BWY, ESDCAN02-2BWY, ESDCAN01-2BLY (AEC-Q101 dual-line CAN/LIN TVS family; pick the VRWM/VBR variant that matches 12V/24V networks). :contentReference[oaicite:3]{index=3}
- Littelfuse: AQ24CANFD (example orderable code: AQ24CANFD-02HTG) designed for automotive CAN lines with ESD/EFT and surge capability. :contentReference[oaicite:4]{index=4}
- onsemi: NUP3125 / SZNUP3125 (dual-line CAN bus protector stated for 24V designs). :contentReference[oaicite:5]{index=5}
Automotive low-C dual-channel ESD arrays (general-purpose fallback when CAN-specific parts are constrained):
- TI: TPD2E2U06-Q1 (automotive low-capacitance dual-channel ESD/TVS array; apply only if the voltage gate and bus budget gates are satisfied). :contentReference[oaicite:6]{index=6}
- ST: ESDAVLC6-2BLY (automotive low capacitance diode array listing; treat as a candidate that still must pass the same gates and the Step-5 matrix on the real harness). :contentReference[oaicite:7]{index=7}
Sanity check (materials):
lock each part by full ordering code (package + suffix + automotive grade) and record the measurement conditions for C and leakage. A BOM line without conditions is not actionable in production.
Decision tree (selection flow): Hard gates → trade-offs → layout feasibility → minimum validation subset
Practical rule:
selection is only “done” when the part is locked by full ordering code and the minimum validation subset passes on the real harness with the intended grounding/return boundary.
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FAQs: Low-C TVS arrays for automotive ports (troubleshooting only)
These FAQs close long-tail debugging without expanding the main text. Scope is strictly port TVS arrays, coupling/return paths, distortion budgets, and validation/measurement traps. Each answer is a fixed 4-line SOP: Likely cause → Quick check → Fix → Pass criteria (placeholders).
Same TVS footprint, new vendor → CAN FD error frames spike. First check Cdiff or Rdyn?
Likely cause: Cdiff/ΔC (and its test conditions) changed, breaking edge/symmetry margin; channel mismatch increases DM↔CM conversion; Rdyn/clamp change is secondary.
Quick check: Compare Cdiff + ΔC for old vs new under the same bias/frequency; scope at PHY pins for Δtr/Δtf and common-mode movement; correlate errors with bitrate/load.
Fix: Enforce the H2-7 distortion budget as a hard gate; require channel matching proof; re-run the minimum validation subset (H2-8) before approving any alternate.
Pass criteria: ErrorFrameRate ≤ X / 10^6 frames over Y minutes at worst bitrate/load; Δtr ≤ X ns, ΔVCM ≤ X V (vs baseline); Cdiff ≤ X pF under defined conditions.
ESD “passes”, but later the port becomes more fragile. TVS degradation or return-path issue?
Likely cause: Parametric drift (leakage↑, C shift, clamp behavior shift) or a return-path/ground boundary change that enlarges the energy loop and increases board coupling.
Quick check: Re-measure leakage and key waveform deltas before/after stress; repeat the same injection with an alternate chassis/ground point; compare “connector-side” vs “PHY-pin” observations to localize.
Fix: Lock a post-stress drift criterion; tighten return path (via fence/short loop) and clarify the boundary (chassis vs signal ground) in the layout review checklist.
Pass criteria: Leakage drift ≤ X% and absolute leakage ≤ X µA @ T=Y°C; post-stress ErrorFrameRate ≤ X / 10^6 frames; performance does not depend on ground point within defined test matrix.
“Low-C TVS” makes EMI worse. Common-mode conversion or layout asymmetry?
Likely cause: Asymmetry (device/pads/vias/return) converts differential energy into common-mode; the TVS placement/return loop injects common-mode currents onto the harness/shield.
Quick check: Compare CM swing and DM↔CM conversion indicators with A/B symmetry changes (e.g., swap to a matched array or mirror-route test coupon); verify via-count and return proximity are symmetric.
Fix: Enforce the “symmetry 6-point checklist” (device/pads/routing/refs/vias/return); tighten the return boundary and minimize loop area at the connector side.
Pass criteria: CM swing ΔVCM ≤ X V vs baseline at PHY pins; radiated emission improvement ≥ X dB in the failing band (placeholder); CAN/LIN/FlexRay error counters remain ≤ X over Y minutes.
CAN FD works at 2–5 Mbps but fails at 8 Mbps. TVS capacitance budget or sampling window?
Likely cause: Capacitance-driven edge slowdown and symmetry loss shrink timing margin at the highest bitrate; apparent “window” issues are often waveform/budget violations at the measurement point.
Quick check: Measure Δtr/Δtf and crossing shift at PHY pins (not only connector side); compare with/without TVS or with a lower-C matched array; log errors vs bitrate and harness load.
Fix: Tighten the Cdiff budget gate; improve symmetry/return loop; require a “worst harness + worst rate + worst temperature” validation subset for any candidate.
Pass criteria: At 8 Mbps worst-case load: ErrorFrameRate ≤ X / 10^6 frames over Y minutes; Δtr ≤ X ns and crossing shift ≤ X ns vs baseline; Cdiff ≤ X pF under defined conditions.
LIN occasionally false-wakes. Leakage@T or noise-coupled TVS triggering?
Likely cause: High-temperature leakage increases standby current and threshold sensitivity, or common-mode disturbances couple into the wake detection path through an unclear return boundary.
Quick check: Correlate false wakes with temperature and injection events; log wake-source attribution (bus/local/timed placeholder); measure leakage @ T=Y°C and compare to standby budget.
Fix: Add leakage@T as a hard gate in selection; tighten return-path definition and placement; require a long-window wake audit as part of bring-up and production sampling.
Pass criteria: FalseWakeCount ≤ X / 24h at worst temperature and harness; standby current ≤ X µA (placeholder); leakage ≤ X µA @ T=Y°C.
TVS is “very close”, but protection still fails. Return loop too large or package inductance too high?
Likely cause: Return path is long/ambiguous (large loop area), causing high residual stress on the PHY; package inductance can amplify peaks if the loop is not controlled.
Quick check: Trace the real return loop (to chassis/signal ground boundary) and measure at PHY pins; A/B test via-fence density and return proximity; compare connector-side vs PHY-side waveforms.
Fix: Close the loop locally with dedicated return vias; clarify the boundary (where energy is allowed to go); choose a package/footprint that supports symmetric routing and short return.
Pass criteria: Residual peak at PHY pins ≤ X V (placeholder) under defined injection; post-injection functionality stable with ErrorFrameRate ≤ X / 10^6 frames over Y minutes.
IEC gun hits the connector shield, and communication errors appear. TVS weakness or chassis-ground strategy?
Likely cause: Energy couples through shield/chassis paths into the board reference; the issue is often an unclear chassis bonding/return boundary rather than TVS stand-off itself.
Quick check: Repeat with controlled chassis bonding states; observe common-mode movement at PHY pins; compare error counters when the shield bonding point is changed (A/B).
Fix: Define the chassis/ground boundary and the intended return destination for injected energy; keep TVS return paths short and consistent with that boundary; update the coupling-path checklist.
Pass criteria: Under shield-hit injection: ErrorFrameRate ≤ X / 10^6 frames over Y minutes; CM swing at PHY pins ≤ X V; behavior is robust across defined chassis bonding states.
Oscilloscope waveform “looks fine”, but errors still happen. How to rule out probe/setting artifacts first?
Likely cause: Probe ground bounce, insufficient bandwidth, wrong trigger window, or inconsistent statistics denominator hides rare edge failures and CM events.
Quick check: Use a low-inductance probing method; document bandwidth and filtering; freeze the metric window (e.g., per 10^6 frames over Y minutes); correlate errors with load/temperature.
Fix: Standardize measurement SOP: point at PHY pins, defined bandwidth, defined trigger, defined logging window; make this SOP part of bring-up and production audits.
Pass criteria: With SOP frozen: repeated runs yield ErrorFrameRate variation ≤ X%; no missed events in a Y-minute window at worst load; waveform deltas stay within the H2-7 placeholders.
Adding TVS reduces overshoot but makes edges too slow. How to tell “C too large” vs harness/termination effects?
Likely cause: TVS capacitance dominates the local RC and slows edges; alternatively, harness/termination changes shift ringing and the apparent edge shape at different measurement points.
Quick check: A/B test with a known lower-C matched array (or remove TVS on a controlled coupon) and keep the same harness; measure at PHY pins; compare Δtr/Δtf and crossing shift against the H2-7 budget.
Fix: Enforce Cdiff gate and matching; if harness dominates, freeze validation on the real harness set and treat harness variants as separate conditions in the matrix.
Pass criteria: Δtr ≤ X ns, crossing shift ≤ X ns, overshoot ≤ X% at PHY pins; ErrorFrameRate ≤ X / 10^6 frames over Y minutes for all harness conditions in scope.
After surge, TVS is not shorted but leakage increases. How to define pass/fail and screening?
Likely cause: Parametric degradation (leakage increase, C shift, clamp behavior drift) that does not create a hard short but can break standby budgets and long-term robustness.
Quick check: Measure leakage @ temperature and defined bias; compare to pre-stress baseline; re-run the minimum subset: stress + communication load + recovery time logging.
Fix: Define “post-stress drift limits” and “audit frequency” in production; reject alternates that cannot provide stable leakage@T and capacitance conditions; add a sample injection audit.
Pass criteria: leakage ≤ X µA @ T=Y°C and drift ≤ X%; standby current ≤ X µA; recovery time ≤ X ms (placeholder); audit rate: 1 per X units.
Changing harness length flips pass/fail at the same TVS. Budget issue or return/coupling issue?
Likely cause: Harness-dependent ringing and CM currents expose an underestimated distortion budget or an unclear return destination, making the port sensitive to small topology changes.
Quick check: Test short vs long harness under identical logging window; measure at PHY pins; track Δtr/overshoot/ΔVCM and correlate with error counters and ground point.
Fix: Expand the validation matrix to include representative harness variants; tighten return-loop control and symmetry so harness changes do not amplify CM conversion.
Pass criteria: ErrorFrameRate ≤ X / 10^6 frames over Y minutes for all harness variants in scope; ΔVCM ≤ X V; waveform deltas stay within budget placeholders across variants.
Two labs/scopes disagree on “good/bad”. How to enforce a consistent decision?
Likely cause: Different probe methods, bandwidth/filters, trigger rules, or metric denominators produce incompatible conclusions even when the port behavior is unchanged.
Quick check: Freeze a shared SOP: measurement point (PHY pins), bandwidth, probe method, trigger window, and statistics definition; re-run the same harness + load + temperature condition set.
Fix: Make the SOP mandatory in bring-up and production audits; store SOP fields with logs (bandwidth, probe, harness, ground point, window definition) for traceability.
Pass criteria: Cross-lab correlation: median ErrorFrameRate difference ≤ X% and waveform delta difference ≤ X% under the same SOP; pass/fail decisions identical across N repeated runs.
