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Jitter & Clocking for PTP/SyncE and ADC/DAC Sampling Clocks

Jitter & Clocking for PTP/SyncE and ADC/DAC Sampling Clocks

← Back to: Industrial Ethernet & TSN

This page turns jitter and clocking into a repeatable engineering workflow: budget → measure → correlate → validate, so PTP accuracy, SyncE mask compliance, and ADC/DAC clock performance can be proven on real hardware. The goal is consistent pass/fail criteria (X) backed by fixed measurement nodes and profiles—not “better-looking plots.”

H2-1 · Scope & Field Checklist (What this page answers)

Page thesis
End-to-end clock jitter control is the common limiter for PTP accuracy, SyncE template compliance, and ADC/DAC performance. This page turns “paper specs” into a budget → measurement definition → pass criteria workflow.
Scope card (hard boundaries)
In-scope (owned by this page)
  • Clock/jitter definitions that map cleanly to budgets and acceptance tests (RJ/DJ/PJ, TIE/MTIE/TDEV, L(f) → integrated jitter).
  • Measurement definitions: where to measure, bandwidth/window, statistics, and common false readings.
  • PTP accuracy (clock-related terms only): timebase stability, timestamp noise at the tap point, and drift/offset signatures.
  • SyncE jitter templates (engineering interpretation): mask intent, cleaner/PLL transfer behavior, and template margin testing.
  • ADC/DAC clock coupling: jitter/phase-noise impact on SNR/ENOB/spurs and when recovered clocks are risky.
  • Design hooks: ref clock routing, power-noise injection paths, layout/return, EMI coupling, and validation closure.
Out-of-scope (do not expand here)
  • TSN scheduling (Qbv/Qci/GCL tables, admission control) — mention only; link out.
  • Full PTP protocol coverage (profiles, BMCA, message flows, full parameter tuning) — mention only; link out.
  • SyncE standard text and network-wide planning — mention only; link out.
  • Industrial stack certification details (PROFINET/EtherCAT/CIP procedures) — link out.
  • ADC/DAC architecture lectures — only clock-interface consequences are covered.
Cross-link rule
If a topic belongs to a sibling page, keep it within two lines and provide a See also link; no deep dive.
Audience stages (how to use this page)
  1. Pre-selection: build the budget sheet, set clock targets, and select measurement points.
  2. Bring-up: run the validation sequence and correlate jitter/PN to offset, masks, and converter performance.
  3. Field troubleshooting: map symptoms (drift, mask margin loss, SNR drop, spur bursts) to clock injection paths and quick checks.
See also (sibling pages)
Deliverables card (takeaways you can copy)
Deliverable 1 · Jitter/Phase-Noise budget sheet fields
  • Node: OSC → PLL/Cleaner → Buffer/Fanout → Load (PHY/MAC/ADC/DAC).
  • Metric: integrated jitter σt, TIE/MTIE/TDEV (when applicable), spur list (if discrete lines exist).
  • Bandwidth/window: integration range or time window; must be explicitly stated.
  • Transfer function assumption: loop bandwidth and attenuation regions (track vs clean).
  • Contribution rule: RSS for uncorrelated noise; mark correlated paths explicitly.
  • Validation point: where the metric is measured on real hardware.
  • Pass criteria: threshold placeholder X (filled after system targets are defined).
Deliverable 2 · Measurement definition (to avoid “pretty but wrong” results)
  • Where: clock node name + tap point (pre/post cleaner, pre/post buffer).
  • How: instrument class, coupling, probe/fixture constraints, reference timebase.
  • Bandwidth: integration range / RBW-VBW / filtering rules.
  • Statistics: window length, confidence and outlier handling.
  • Record: temperature, supply ripple, load state, link mode (EEE, rate), and event markers.
Deliverable 3 · Pass criteria (system-level acceptance language)
  • SyncE: template/mask margin ≥ X across temperature and supply corners.
  • PTP: offset drift stays within X over Y minutes under defined load states.
  • ADC/DAC: SNR/ENOB degradation vs clock budget ≤ X (and no persistent discrete spurs above X).
Jitter & Clocking — Three linked outcomes PTP accuracy SyncE templates ADC/DAC coupling Timestamp tap Servo timebase Offset / drift Recovered clock PLL / cleaner Mask margin Sampling clock Timing error SNR / spurs Shared clock foundation (controls all three) OSC / XTAL PLL / Cleaner Buffers Power Layout/EMI Same noise sources → different outcomes
This page keeps three outcomes aligned by sharing one measurable foundation: the clock tree, its power/layout injection paths, and consistent measurement definitions.

H2-2 · Jitter & Phase Noise: Practical Definitions That Don’t Lie

Jitter metrics only become useful when time scale, bandwidth/window, and application responsibility are stated explicitly. Without that, budgets cannot close and acceptance testing becomes subjective.
Hard rule (use everywhere on this page)
Every jitter/phase-noise number must carry (1) where measured, (2) bandwidth/window, and (3) what outcome it protects (PTP, SyncE, or ADC/DAC).
1) Time scale first: jitter vs wander
Jitter (short-term timing fluctuation)
  • Lives on: ns to µs scales (and nearby frequency offsets in phase noise).
  • Protects: SyncE mask margin and converter sampling instant stability.
  • Breaks when wrong: using a “pretty RMS jitter” number without bandwidth can hide discrete spurs that ruin SNR or mask compliance.
Wander (long-term phase/frequency drift)
  • Lives on: ms to seconds and beyond (temperature, aging, holdover behavior).
  • Shows up as: slow offset drift and slope changes in time error statistics.
  • Breaks when wrong: treating drift as “random jitter” leads to incorrect fixes (filter tuning instead of timebase stability).
2) Statistical view: RJ / DJ / PJ and what budgets can add
Budgets fail most often due to mixing addable noise with non-addable deterministic effects. Use the following taxonomy to decide whether RSS is valid.
RJ (Random jitter)
Uncorrelated noise-like timing variation. Usually RSS-addable across independent blocks (osc, PLL, buffer) when measurement bandwidth is consistent.
DJ (Deterministic jitter)
Pattern-dependent timing variation (ISI, duty-cycle distortion, periodic modulation). Not safely RSS-addable unless the deterministic mechanism is modeled.
PJ (Periodic jitter / discrete spurs)
Discrete lines (often from switching regulators, reference coupling, or clock-domain interactions). A low RMS number can still fail a mask or create converter spurs. Always capture spur frequency + amplitude as a first-class budget item.
3) Time-error view vs frequency-domain view (use the right lens)
TIE / MTIE / TDEV (time-domain statistics)
  • TIE: instantaneous time error sequence at a defined tap point.
  • MTIE/TDEV: summarize stability vs observation interval (useful for drift/holdover signatures).
  • Best use: timebase stability questions (PTP drift patterns, holdover behavior).
Phase noise L(f) and integrated jitter σt
  • L(f): noise density vs frequency offset; reveals where noise/spurs live.
  • σt: integrated jitter derived from L(f) over a stated integration band.
  • Critical trap: changing the integration band can change σt dramatically; the band must match the protected outcome (mask vs converter).
4) Responsibility map: which metric protects which outcome
For PTP accuracy (clock-related terms only)
  • Primary lens: timebase stability and timestamp noise at the tap point.
  • Common failure: slow drift attributed to “random jitter” instead of stability/holdover behavior.
  • Measurement note: capture TIE over defined windows; record temperature and supply states.
For SyncE templates
  • Primary lens: mask/margin and cleaner transfer (track vs clean regions).
  • Common failure: “good RMS jitter” but discrete spurs or wrong bandwidth fail the template.
  • Measurement note: define the mask test point and sweep corners (temp/supply/load).
For ADC/DAC sampling and spurs
  • Primary lens: phase noise near offsets that fold into sampling uncertainty and create modulation.
  • Common failure: ignoring supply-synchronous spurs that create deterministic tones in the spectrum.
  • Measurement note: track both integrated noise and discrete spur lines; correlate with converter FFT.
Time scale → metric → outcome responsibility ns µs ms s jitter RJ/DJ/PJ TIE wander L(f) → σt ADC/DAC: sampling jitter & spurs (ns → µs) SyncE: template/mask margin (µs → ms) PTP: timebase stability & drift patterns (ms → s) Always state: measurement node + bandwidth/window + protected outcome
Use time scale to choose the correct metric lens. Drift and stability live on longer windows; mask compliance and sampling uncertainty live on shorter scales. Numbers without bandwidth/window are not actionable.

H2-3 · Measurement First: How You Will Be Fooled (and How Not)

Clock and jitter numbers are only actionable when the measurement node, bandwidth/window, and instrument reference are stated. This section prevents budgets and acceptance tests from being built on “pretty but wrong” readings.
Measurement map (define the node before any number)
  • N1 · Source: OSC/XTAL output (baseline noise and spurs).
  • N2 · Cleaner output: PLL/cleaner output (transfer behavior and residual noise).
  • N3 · Distribution: fanout/buffer output (additive jitter and isolation quality).
  • N4 · Load pin: PHY/MAC refclk input (what the system truly consumes).
  • N5 · Timestamp timebase: clock feeding the timestamp tap (PTP accuracy sensitivity).
  • N6 · ADC/DAC clock: sampling/reconstruction clock (SNR/spur coupling point).
Hard rule
Every reported value must include: Node (N1–N6) + bandwidth/window + instrument timebase/reference.
Trap cards (Trap → Quick check → Fix → Pass criteria)
Trap 1 · RBW/VBW mismatch makes numbers incomparable
Trap: changing RBW/VBW/averaging shifts spur visibility and integrated-noise results, then comparisons become invalid.
Quick check: repeat with the same RBW/VBW and capture settings; log them in the dataset.
Fix: standardize a measurement profile per node (N1–N6) and lock it for bring-up and production.
Pass criteria: repeated runs with identical settings agree within X and show stable spur detection.
Trap 2 · Integration band not stated (σt becomes meaningless)
Trap: integrated jitter σt changes dramatically with the chosen band; “low jitter” without the band is not actionable.
Quick check: report σt with explicit integration band and the node; compare apples-to-apples only.
Fix: define one integration band per protected outcome (template vs converter) and keep it consistent.
Pass criteria: σt reported with the mandated band; mask or converter criteria pass with margin ≥ X.
Trap 3 · Averaging hides rare spurs and intermittent modulation
Trap: long averaging can bury intermittent spurs that later dominate masks or create converter tones.
Quick check: switch to peak-hold or shorter averaging; compare spur lists across load states.
Fix: log spur frequency/amplitude as a first-class dataset field; correlate with supply and load events.
Pass criteria: no persistent discrete spur above X across required corners.
Trap 4 · Instrument timebase (reference) is the hidden limiter
Trap: the instrument timebase or lack of external reference turns instrument drift into apparent DUT drift.
Quick check: lock to a known reference or compare two instruments; observe whether drift signatures follow the instrument.
Fix: mandate reference discipline for long windows; record reference source in the dataset.
Pass criteria: baseline runs on a reference source meet stability within X.
Trap 5 · Ground loop and probe loading inject false jitter
Trap: ground loops create low-frequency modulation; probe capacitance changes edge shape and introduces deterministic timing artifacts.
Quick check: switch grounding scheme, shorten return, use a different probe/fixture; compare node N2 vs N4.
Fix: use controlled impedance paths, minimize loop area, and avoid heavy probe loading on sensitive nodes.
Pass criteria: measured jitter/spurs remain within X under alternate probing setups.
Trap 6 · Window length and confidence (looks stable ≠ pass)
Trap: short windows miss drift and rare events; long windows mix environmental changes unless fields are recorded.
Quick check: run a short window and a long window with logged temperature/supply/load; compare signatures.
Fix: bind the window length to the protected outcome (mask vs drift vs spur capture) and standardize repetition.
Pass criteria: meets threshold X and repeats consistently across required corners.
Minimum viable dataset (MVD) for reproducible acceptance
  • Setup: node (N1–N6), instrument class, timebase/reference, probe/fixture, cable length.
  • Settings: RBW/VBW, integration band or window length, averaging mode, trigger/capture mode.
  • Environment: temperature, supply ripple/mode, load state (power events and clock mode).
  • Outputs: σt, spur list (freq/ampl), TIE trend, template/mask margin (X).
Measurement chain (where false jitter is injected) DUT clock out Node: N4/N6 Buffer / fanout Additive jitter Fixture / probe Load + reflections Instrument PN / jitter / TIE Timebase External ref? Ground loop Probe C Reflection Supply spur Timebase
A trustworthy result requires controlling the probe/fixture loading, avoiding ground loops, and disciplining the instrument timebase for long windows.

H2-4 · Clock Tree Architecture Patterns for Industrial Ethernet Nodes

Clock trees must satisfy three linked requirements: short-term noise (templates and sampling uncertainty), long-term stability (drift/holdover), and distribution integrity (isolation and additive jitter). The patterns below stay at the clock-tree layer and avoid protocol-level tuning.
Block roles (gen / clean / distribute)
Gen · XTAL / TCXO / OCXO
  • What matters: baseline phase noise, temperature drift, startup behavior.
  • Field risk: aging and temperature gradients show up as drift signatures.
Clean · PLL / jitter cleaner
  • What matters: loop bandwidth (track vs clean), attenuation region, holdover behavior.
  • Field risk: wrong bandwidth passes lab tests but fails corners (spur leakage or slow relock).
Distribute · fanout / buffer
  • What matters: additive jitter, isolation, skew control and rail sensitivity.
  • Field risk: a “quiet” cleaner can be undone by noisy distribution power or coupling.
Architecture patterns (A/B/C)
Pattern A · Single ref + cleaner + fanout
  • Best for: gateways and switches needing one disciplined reference and consistent distribution.
  • Strength: consistent clock domain and predictable measurement points (N1→N2→N3→N4/N5/N6).
  • Risk: single-point failure; spur leakage from power and distribution paths.
  • Bring-up checks: measure N2 and N3 for additive jitter; confirm N4/N6 spur list under load events.
  • Pass criteria: template margin ≥ X and converter spur limits ≤ X.
Pattern B · SoC PLL + external cleaner
  • Best for: SoC-centric designs where the system clock exists, but critical outputs require additional cleaning.
  • Strength: separates convenience clocks from performance clocks; cleaner output can feed PHY/timebase/converters.
  • Risk: SoC PLL spurs and rail noise coupling into the cleaner input or shared distribution.
  • Bring-up checks: characterize SoC PLL spur lines; verify cleaner transfer region meets the intended role (track vs clean).
  • Pass criteria: spur lines remain below X and mask margin holds across corners.
Pattern C · Recovered clock + local oscillator holdover
  • Best for: endpoints that must maintain stability through link disturbances and recover cleanly.
  • Strength: enables syntonized operation while preserving a stable local reference during disruptions.
  • Risk: loop bandwidth mis-selection causes spur/noise tracking; holdover drift dominates long windows.
  • Bring-up checks: log lock time, holdover drift signature, and mask margin under temperature sweep.
  • Pass criteria: drift stays within X over Y minutes and mask margin ≥ X.
Engineering trade-offs (holdover / lock time / loop bandwidth)
  • Loop bandwidth too wide: tracks disturbances; spurs/noise leak through and can fail template or create tones.
  • Loop bandwidth too narrow: cleans noise but increases lock time; recovery and convergence become slow.
  • Holdover quality: determines long-window drift signatures; must be validated across temperature and supply corners.
  • Distribution isolation: protects sensitive loads (timestamp timebase and converters) from noisy domains.
Node clock-tree patterns (A/B/C) Pattern A Pattern B Pattern C OSC / XTAL Cleaner / PLL Fanout Loads PHY TS SoC PLL External cleaner Fanout Loads PHY ADC Recovered clk Cleaner / PLL Fanout Holdover OSC Loads PHY TS Blue outline: cleaner role / discipline point
Choose a pattern by prioritizing short-term noise (templates/converters), long-term stability (drift/holdover), and distribution isolation. Validate at real load pins.

H2-5 · Budgeting Method: From Phase Noise to End-to-End Time Error

This section provides a reusable budgeting workflow that turns phase-noise and per-block jitter into end-to-end jitter, TIE/offset statistics, and a clean mapping to acceptance metrics for PTP, SyncE templates, and ADC/DAC clocks. No results are actionable unless node, bandwidth/window, and reference are stated.
Budget steps (Step 1–6)
Step 1 · Define the budget target and time scale
  • Goal: lock the metric and window before collecting numbers.
  • Inputs: target outcome (template/mask, PTP offset window, converter tone risk).
  • Method: bind each outcome to a window/band; avoid mixing short-term jitter with long-term drift.
  • Outputs: required statistic (RMS/peak/percentile) + window/band + pass threshold (X).
Step 2 · Build the error tree (nodes and handoff points)
  • Goal: decompose the clock path into measurable nodes.
  • Inputs: OSC/XTAL, PLL/cleaner, divider, fanout/buffer, load pins (PHY/timebase/ADC).
  • Method: each node carries a measurement definition and its own contribution line.
  • Outputs: a node list with measurement node IDs and acceptance placeholders (X).
Step 3 · Convert phase noise to a comparable contribution
  • Goal: normalize inputs (L(f) or σt) to consistent bands and frequencies.
  • Inputs: L(f) curves or integrated jitter, output frequency, and integration band/window.
  • Method: record node + fout + band; apply divider/multiplier scaling consistently.
  • Outputs: per-node σt (banded) and a spur list (freq/ampl) for discrete lines.
Step 4 · Combine terms (RSS + correlation rules + spur handling)
  • Goal: avoid optimistic budgets from incorrect independence assumptions.
  • Method: use RSS for uncorrelated noise; treat correlated modulation and shared spurs as separate ledger lines.
  • Quick correlation test: if a line tracks temperature/load identically across nodes, mark it correlated.
  • Outputs: E2E σt (uncorrelated) + correlated ledger + spur ledger.
Step 5 · Emit three deliverables (jitter / TIE / spur list)
  • E2E jitter: for template/mask compliance and short-term clock quality.
  • TIE/offset stats: for long-window drift and holdover behavior tied to timebase stability.
  • Spur list: discrete lines that can dominate masks, servos, or converter tones (never RSS these away).
  • Pass criteria: each deliverable meets its own threshold (X) with repeatability.
Step 6 · Freeze the budget field template (copy-paste ready)
  • Goal: enforce consistent reporting across bring-up and production.
  • Method: require node + band/window + reference + corner tags on every line item.
  • Outputs: a field catalog that prevents “pretty but incomparable” numbers.
Budget field template (field catalog, not a big table)
Path fields
  • Node ID: N1–N6 (where the number applies).
  • f_in / f_out: frequency at this node; include divider/multiplier N.
  • Owner block: OSC / PLL / divider / buffer / load.
  • Corner tag: temperature, supply mode, load state.
Noise fields
  • L(f) source: measurement or model reference for phase noise.
  • Band / window: integration band or time window definition.
  • σt (banded): integrated jitter contribution at this node.
  • Spur list: frequency + amplitude for discrete lines.
Transfer fields
  • PLL loop BW: track vs clean boundary and attenuation region.
  • Residual noise: output noise floor after cleaning.
  • Holdover mode: drift signature and recovery characteristics.
  • Distribution isolation: additive jitter and coupling notes.
Acceptance fields
  • Metric: E2E σt, mask margin, TIE/offset stat, or spur limit.
  • Pass threshold: X (placeholder), plus margin reporting.
  • Setup ID: measurement profile ID (links to MVD definition).
  • Repeatability: reruns and corner coverage status.
Budget error tree / waterfall (from blocks to end-to-end time error) OSC / XTAL L(f), σt, Spur PLL / Cleaner Transfer + BW Divider / N Scale f Fanout Additive Loads PHY TS ADC Per-node ledger (Contribution / Measurement / Limit) OSC σt contrib Band / node Limit: X PLL Residual σt BW / transfer Limit: X Divider Scale rule f_in → f_out Limit: X Fanout Additive σt Isolation Limit: X Outputs E2E jitter RSS + rules TIE / offset stats Windowed Spur list Discrete lines
Budgeting is repeatable when each node contribution is defined with a node ID, a band/window, and a clear rule for correlation and discrete spurs.

H2-6 · PTP Accuracy: What Clocking Actually Controls

This section covers only the PTP accuracy error terms that are controlled by timebase noise, timebase stability, and capture-latency stability. Protocol configuration details are intentionally excluded and should be handled on the dedicated timestamping page.
Clock-related error terms (scope)
Timebase noise (short-term)
Phase noise and jitter at the timestamp timebase sets the noise floor of timestamping and the servo input.
Timebase stability (long-window)
Holdover and drift signatures dominate offset statistics over longer windows and temperature changes.
Capture-latency stability (clock-domain sensitivity)
Stability of the timestamp capture path can be affected by timebase noise, power modulation, and temperature-driven delays.
Error term cards (Symptom → Clock-related cause → Quick check → Fix → Pass criteria)
Pattern 1 · Periodic ripple in offset (fixed frequency)
Symptom: offset shows a stable sinusoidal ripple or repeating waveform.
Clock-related cause: discrete spur or modulation coupled into the timestamp timebase (supply/PoE/load periodicity).
Quick check: capture a spur list at the timebase node and correlate ripple frequency with spur frequency.
Fix: improve supply isolation, reduce coupling into the timebase, and control spur sources at the clock tree.
Pass criteria: ripple amplitude stays below X and does not increase with load events.
Pattern 2 · Step change followed by slow recovery
Symptom: offset jumps, then decays slowly to a new steady shape.
Clock-related cause: PLL/cleaner dynamics and loop bandwidth effects during relock or disturbance tracking.
Quick check: log lock time and observe whether recovery time scales with cleaner bandwidth settings.
Fix: tune the clock-tree loop bandwidth (track vs clean) and isolate noisy domains from timebase inputs.
Pass criteria: recovery settles within X time and stays inside drift limits.
Pattern 3 · Temperature-driven monotonic drift
Symptom: offset trends steadily with temperature or airflow changes.
Clock-related cause: holdover oscillator temperature coefficient, thermal gradients, or insufficient isolation from heat sources.
Quick check: run a controlled temperature step and compare the drift signature with holdover mode enabled/disabled.
Fix: improve oscillator selection/placement, reduce gradients, and validate holdover drift across corners.
Pass criteria: drift stays within X over Y minutes across corners.
Pattern 4 · Rare spikes (non-periodic outliers)
Symptom: occasional large offset spikes with otherwise normal behavior.
Clock-related cause: capture-latency instability from power transients, coupling, or a marginal timebase noise floor.
Quick check: correlate spikes with power and event logs; verify timebase spur/noise under the same conditions.
Fix: harden the timebase supply and capture path isolation; treat correlated event sources as ledger items.
Pass criteria: outlier rate stays below X per Y minutes at required corners.
Pattern 5 · Offset changes with load state (traffic/power events)
Symptom: offset distribution shifts when load changes or power events occur.
Clock-related cause: insufficient isolation between noisy domains and the timestamp timebase or distribution rails.
Quick check: measure timebase spur/noise at N5 across load states; compare with converter/PHY node changes.
Fix: partition supplies, improve return paths, and use distribution isolation to protect the timebase domain.
Pass criteria: timebase noise and drift stay within X regardless of defined load corners.
One-step vs Two-step (clock sensitivity only)
  • One-step: more sensitive to timebase noise and insertion stability at the timestamp tap.
  • Two-step: more sensitive to timestamp generation and path stability (still dominated by timebase quality).
  • Pass criteria: measured offset stays within X under the defined window and corner set.
See also
Full PTP configuration and topology calibration belong on the dedicated PTP Hardware Timestamping page (link only; no expansion here).
PTP accuracy (clocking view): timebase → timestamp tap → servo Master timebase Noise Holdover drift Slave timebase Noise Holdover drift Timestamp tap Capture latency Stability Servo / filter Filter BW Offset stats Clocking controls: Noise floor • Holdover drift • Capture latency stability • Filter BW sensitivity
Diagnose offset behavior by separating short-term noise (phase noise/jitter), long-window drift (holdover), and capture-path stability.

H2-7 · SyncE Jitter Templates: Engineering Interpretation for Component Choice

This section translates SyncE jitter templates (masks) into engineering actions: where to measure, what the mask constrains, how to choose a cleaner/PLL, and how to test margin. Standard clause details and network planning are intentionally excluded.
Template → What it means → What to choose → How to test
A · Template (mask) in engineering terms
  • Mask concept: a limit region over offset frequency; not a single RMS number.
  • Measurement point: define the exact node (device output / cleaner output), not an arbitrary test pad.
  • Reporting fields: node ID, fout, offset-frequency range, RBW/VBW (or equivalent), and window/band.
  • Ledger rule: discrete spurs are listed separately (spur ledger), never “averaged away”.
B · What it means (track / clean / spurs)
Track region (inside loop BW)
Recovered clock variations are followed; bandwidth selection decides how much network behavior is tracked.
Clean region (outside loop BW)
Output noise is limited by attenuation and residual noise; this region often sets mask margin.
Spur / modulation
Discrete lines dominate compliance and system artifacts; log a spur list with frequency and amplitude.
C · What to choose (cleaner/PLL parameters)
Loop bandwidth (BW)
  • Controls: track vs clean boundary.
  • Risk: BW too wide tracks poor recovered behavior; BW too narrow slows tracking and shifts drift signatures.
Attenuation & residual noise
  • Controls: mask margin outside BW.
  • Rule: residual noise often sets the floor; do not select by attenuation only.
Wander transfer
Long-window behavior can dominate field signatures; capture it as a separate acceptance item.
Holdover
  • Controls: loss-of-lock survival and drift signature.
  • Acceptance: lock time and drift stay within threshold (X) across corners.
D · How to test (repeatable acceptance)
Test 1 · Mask margin baseline
  • Setup fields: node, fout, offset band, RBW/VBW profile ID.
  • Data: mask margin + banded jitter + spur list.
  • Pass: margin ≥ X at baseline conditions.
Test 2 · Temperature sweep
  • Goal: validate drift signature and spur stability across corners.
  • Data: margin trend + spur trend + long-window stability tag.
  • Pass: worst-corner margin ≥ X.
Test 3 · Supply ripple injection
  • Goal: reveal modulation lines that can dominate templates.
  • Data: spur list change + sideband emergence + margin delta.
  • Pass: modulation products stay below X and margin remains acceptable.
Boundary note
This page focuses on engineering interpretation, component choice, and repeatable acceptance. Clause-by-clause standard text and network planning belong on the dedicated SyncE page (link only).
SyncE cleaner view: recovered clock → PLL → SyncE out (BW regions + holdover) Recovered clock Input jitter Jitter cleaner / PLL Loop BW Track Clean SyncE out Mask margin Holdover Drift signature BW interpretation (not a curve) Follow Attenuate Residual BW Margin Temp sweep Ripple inject
Interpret templates by defining the measurement node and profile, then mapping loop bandwidth and residual noise to mask margin and corner tests.

H2-8 · Coupling to ADC/DAC Clocks: Turning Jitter into SNR/Spurs

This section maps clock phase noise and jitter to converter outcomes: SNR/ENOB degradation and discrete spurs/sidebands. The focus is engineering use: banded jitter, spur-ledger handling, and validation plans that match real measurements.
Engineering conclusion (usable, no derivation)
Sampling jitter → SNR impact (use with banded σt)
Treat sampling time uncertainty as phase noise on the input signal. Higher input frequency amplifies sensitivity to the same RMS jitter.
Rules that prevent misuse:
  • Rule 1: report banded jitter (node + band + fout).
  • Rule 2: random jitter lifts the noise floor; periodic jitter creates discrete spurs.
  • Rule 3: input frequency increases sensitivity; validate at worst-case input bands.
Band decomposition (close-in vs far-out)
Close-in
Captures slow phase behavior; can dominate long-window signatures and low-frequency tone shaping.
Far-out
Acts like wideband random jitter; often maps directly into noise-floor rise for high-frequency inputs.
Spurs
Discrete lines create tones/sidebands; always treat as a separate acceptance list.
Use-case cards (spec target → risk → verification → pass)
Use-case 1 · Low-frequency precision measurement
Spec target: stability and close-in behavior across long windows.
Risk: drift signatures and modulation lines appear as slow artifacts.
Verification: temperature sweep + long-window stability tags + spur list.
Pass criteria: drift and spurs remain within X across corners.
Use-case 2 · High-speed sampling (high input frequency)
Spec target: far-out banded jitter at the sampling clock node.
Risk: noise floor rises and SNR/ENOB drop at high input frequencies.
Verification: banded integrated jitter + input-frequency sweep.
Pass criteria: worst-case input band meets SNR target with margin ≥ X.
Use-case 3 · High dynamic range (spur-sensitive)
Spec target: spur list limits dominate over a single RMS figure.
Risk: discrete sidebands collapse SFDR even if RMS jitter looks fine.
Verification: spur scan + supply ripple injection + sideband observation.
Pass criteria: spur products stay below X at required tones.
Decision · Using recovered clock for ADC/DAC
Risk trigger: network modulation/spurs propagate into sampling and create unpredictable tones.
Quick check: compare spur list + banded jitter between recovered+cleaned clock and a local oscillator path.
Fix: add cleaner, adjust BW, isolate supplies, or use local clock with disciplined control.
Pass criteria: converter metrics meet targets with margin ≥ X across corners.
Clock PN / jitter → sampling error → phase modulation → noise / spurs Clock PN Jitter Sampling time error Phase modulation Outcomes Noise Spur Two ledgers (do not mix) Random jitter Noise floor ↑ Use banded σt Periodic jitter / spur Discrete tones Keep spur list Sensitivity Input freq ↑ Sensitivity ↑ Validate at worst-case input band
Separate random jitter (noise floor) and periodic jitter (spurs). Higher input frequency increases sensitivity to the same clock quality.

H2-9 · Ref Clock, Power, and Layout: Where Jitter Is Born

This section turns clock-noise physics into actionable layout and power hooks: return paths, supply ripple → spurs, and EMI/common-mode coupling that can masquerade as “jitter”. Protocol and general PCB theory are intentionally excluded.
Deliverables (what this chapter gives)
  • Do/Don’t hooks for refclk routing, power partitioning, and EMI containment.
  • Quick checks that point directly to the likely injection mechanism.
  • Anti-patterns (magnetics / PoE current paths / plane cuts) explained from a clock-only perspective.
Do / Don’t checklists (each item: one action + why + quick check)
A · Refclk routing & return paths
DO · Keep a continuous reference plane under refclk
Why: a short return path minimizes loop area and magnetic coupling.
Quick check: verify no plane cuts, slots, or via fences break continuity under the refclk segment.
DON’T · Route refclk across splits or return discontinuities
Why: forced return detours increase loop area and convert nearby aggressors into clock modulation.
Quick check: mark every “crossing of a split” on the layout and treat each as a likely injection point.
DO · Keep refclk far from fast edges and high-current loops
Why: aggressor fields couple into the refclk net and show up as spurs and apparent jitter.
Quick check: find the closest approach to SW nodes / PoE paths and minimize long parallel runs.
DON’T · Overuse layer swaps and dense via clusters on refclk
Why: discontinuities and return ambiguity make coupling and ringing more likely.
Quick check: count layer swaps and ensure each swap has a clear return reference strategy.
B · Power noise: ripple → spurs
DO · Partition oscillator/cleaner supply and isolate from switching rails
Why: switching ripple modulates clock phase and creates discrete lines at fSW and harmonics.
Quick check: spur scan at the clock node for peaks at fSW, 2fSW, … and their sidebands.
DON’T · Feed clock blocks directly from a noisy DCDC without isolation
Why: residual ripple and load steps translate into modulation products and mask-margin loss.
Quick check: correlate spur amplitude with DCDC load states and switching modes.
DO · Treat PSRR and supply filtering as a spur-control tool
Why: the worst failures are often discrete spurs, not just higher RMS jitter.
Quick check: inject controlled ripple and confirm spur products remain below threshold X.
DON’T · Mix clock return currents with high-current ground returns
Why: shared impedance creates phase modulation and makes jitter “load-dependent”.
Quick check: verify the clock block return does not cross PoE or power-stage return corridors.
C · EMI & common-mode coupling (apparent jitter)
DO · Create a “quiet zone” around oscillator/cleaner and refclk
Why: near-field coupling injects modulation that looks like jitter but tracks aggressor activity.
Quick check: list the nearest fast-edge nets and switching nodes inside the clock keepout.
DON’T · Allow aggressor return currents to cross the clock region
Why: shared return paths convert switching energy into phase noise and spurs.
Quick check: trace the high-current loop on the PCB and confirm it does not “cut through” the clock plane region.
DO · Use measurement cross-checks to detect coupling artifacts
Why: coupling-dominated “jitter” changes when probe grounding or fixture geometry changes.
Quick check: repeat a spur scan with an alternate grounding scheme; coupling artifacts often shift visibly.
D · Anti-patterns (clock-only view)
DON’T · Let magnetics / large inductors sit inside the clock quiet zone
Why: magnetic fields and high di/dt loops inject modulation and raise spur risk.
Quick check: measure distance to the nearest inductor/CMC and the nearest SW node.
DON’T · Cut planes with PoE high-current corridors near refclk returns
Why: plane cuts force return detours, turning PoE currents into clock phase modulation.
Quick check: mark every plane cut and confirm refclk return does not cross it.
DO · Provide a clean return corridor for refclk and clock power
Why: a defined corridor prevents high-current returns from becoming clock-reference impedance.
Quick check: ensure the corridor remains continuous across layers and connector transitions.
Minimal facts to record (layout/power)
  • Refclk crossings over plane cuts (locations) and total layer swaps.
  • Nearest distance to DCDC SW node and any long parallel segments.
  • Clock rail source type (LDO/DCDC), isolation elements, and shared return corridors.
  • PoE current path corridor and any plane slots near clock returns.
Return paths and noise injection (clock-only view) Clock region (quiet zone) Oscillator Cleaner / PLL Refclk net Reference plane / return path Continuous return corridor Plane cut Via gap Aggressors DCDC SW PoE path High di/dt loops Conducted ripple EMI coupling Spurs Jitter rise Quick checks plane continuity · SW distance · PoE corridor
Treat “jitter” as an injection problem: return discontinuities and power/EMI aggressors create spurs and apparent phase noise at clock nodes.

H2-10 · Validation & Correlation: Proving the Budget on Real Hardware

This section closes the loop: prove clocking budgets on real hardware, correlate measurements with system counters, and freeze repeatable acceptance criteria for production. Only clock-related fields are included.
Closure loop (bench → field → production)
Budget → Measure → Correlate → Adjust → Freeze criteria → Production test
Test plan cards (Test / Setup / Expected / Fail signature / Next action / Pass X)
A · Bring-up sequence (order matters)
Test 1 · Timebase baseline
Setup: measure at the defined clock node with a fixed profile (RBW/VBW ID + offset band).
Expected: stable banded jitter and a stable spur list.
Fail signature: spurs track power mode or load state.
Next action: power partition / return path audit (H2-9 hooks).
Pass: banded jitter and spur products remain within X.
Test 2 · Link clock sanity
Setup: evaluate recovered/SyncE output at the compliance node.
Expected: mask margin stays positive with stable lock state.
Fail signature: margin collapses during temperature or supply changes.
Next action: cleaner BW / residual noise selection (template interpretation).
Pass: margin ≥ X across required bands.
Test 3 · System metric confirmation
Setup: compute offset statistics in the same window used for clock metrics.
Expected: stable statistics without mode-dependent signatures.
Fail signature: drift signatures align with holdover entry/exit or power events.
Next action: verify holdover settings and clock-domain partitioning.
Pass: statistics remain within X across corners.
B · Correlation rules (avoid mismatched windows)
Rule 1 · Align time windows
Setup: use the same statistical window for jitter metrics and counter aggregation.
Expected: correlation becomes stable across runs.
Fail signature: “looks stable” metrics but inconsistent pass/fail decisions.
Next action: standardize the definition and log window ID per record.
Pass: repeatability within X across reruns.
Rule 2 · Keep two ledgers (random vs spurs)
Setup: correlate banded jitter with noise-like performance; correlate spur list with tone-like artifacts.
Expected: distinct failure signatures map to distinct mitigation actions.
Fail signature: a single RMS number hides a dominant discrete line.
Next action: add spur scan + ripple inject to acceptance (H2-9 + H2-7).
Pass: spur products remain below X at all corners.
C · Sweep strategies (temperature / supply / load)
Sweep 1 · Temperature
Expected: stable margin trend; spurs do not appear only at extremes.
Fail signature: drift signature changes shape at hot/cold corners.
Next action: revisit holdover and oscillator corner performance.
Pass: worst-corner margin ≥ X.
Sweep 2 · Supply ripple / load-step injection
Expected: spur products stay bounded; margin does not collapse.
Fail signature: sidebands appear at fSW offsets or ripple frequency.
Next action: power isolation + return-path audit (H2-9 B/C).
Pass: spur deltas remain within X.
Sweep 3 · System load states
Expected: clock metrics are insensitive to traffic/load changes.
Fail signature: jitter or spurs track load steps and mode transitions.
Next action: identify shared impedance and coupling paths (H2-9).
Pass: deltas remain within X across states.
D · Black-box fields (clock-only, minimal)
Identity: device-id, clock mode, profile ID, measurement node ID.
State: lock status, holdover enter/exit, reset reason.
Corners: temperature, rail voltage summary, power mode.
Clock quality: mask margin, banded jitter summary, top spurs (freq, level).
Correlation: offset statistics + selected error counters in the same window.
Closure loop: budget → validate → freeze for production Budget fields Measure banded Correlate window Adjust BW Freeze criteria pass X Prod test Key evidence tags (minimal) banded jitter spur list offset stats counters Adjustment knobs BW / residual layout / return power isolation iterate
Freeze criteria only after the same windowed evidence repeats across temperature, supply, and load corners with stable correlation.

H2-11 · Engineering Checklist (Design → Bring-up → Production)

A three-gate deliverables checklist that turns clock budgets into repeatable acceptance criteria. All items are clock/jitter/measurement-only to avoid protocol or stack overlap.
Gate overview (what must be proven)
  • Design gate: clock-tree + power/return + layout constraints + budget fields are complete and consistent.
  • Bring-up gate: timebase baseline + SyncE mask margin + PTP clock-related error signatures are verified and correlated.
  • Production gate: station profiles + thresholds + logging fields are frozen for traceability and consistent screening.
Gate A
Design gate — eliminate structural jitter sources before hardware exists
Checklist
  • ☐ Clock-tree roles are explicit (generate / clean / distribute), with a single source of truth diagram version.
  • ☐ Refclk format and domain crossings are fixed (LVDS/LVPECL/CMOS), with isolation boundaries identified.
  • ☐ Cleaner/PLL assumptions are frozen (loop BW, holdover mode, lock time budget), mapped to required tests.
  • ☐ Fanout plan exists (additive jitter targets, per-domain isolation, output format constraints).
  • ☐ Clock rail strategy is decided (separate rails or isolation networks; spur containment plan).
  • ☐ Return-path continuity is reviewed (no refclk crossing plane cuts; no large-current return through clock region).
  • ☐ Budget worksheet fields are complete (banded jitter, spur ledger, transfer assumptions, correlation/RSS note).
  • ☐ Every budget line item binds to: measurement node + profile ID + Pass criteria X.
Evidence artifacts (must exist)
  • Clock-tree diagram revision + interface list (node IDs and clock modes).
  • Layout review snapshots (refclk route + return plane continuity markers).
  • Budget worksheet revision (fields complete; Pass X placeholders present).
Gate B
Bring-up gate — prove timebase first, then link, then system correlation
Test sequence (order matters)
  • ☐ Timebase baseline: banded jitter (profile ID), spur list (RBW/VBW/window ID), phase-noise-to-jitter mapping is consistent.
  • ☐ SyncE compliance (if used): mask margin captured at the defined measurement point and bandwidths.
  • ☐ Holdover behavior: entry/exit conditions logged; recovery stability checked under defined disturbance.
  • ☐ PTP clock-only signatures: offset drift patterns are correlated with timebase noise/spurs (no protocol tuning here).
  • ☐ Corner sweeps: temperature corners + supply ripple injection + load-state changes are executed and recorded.
Minimum viable dataset (clock-only)
  • Device ID / node ID / clock mode.
  • Measurement node + profile ID + window ID (for every plot/capture).
  • Banded jitter summary + top spurs list (freq/level).
  • Mask margin summary (by band) + holdover events timeline.
  • PTP offset statistics (same windowing discipline as jitter evidence).
Gate C
Production gate — freeze station profiles, limits, and traceability
Station screening rules
  • ☐ Banded jitter station profile is fixed (profile ID); comparison uses the same integration bands.
  • ☐ Spur detection rules are fixed (Top-N, floor threshold X, frequency bands).
  • ☐ Mask margin lower bound is fixed (Pass X), including temperature sampling strategy.
  • ☐ Re-test policy is defined (avoid “one-shot” false rejects from setup artifacts).
  • ☐ Logging fields are frozen for field forensics (clock-only, no protocol noise).
Example “clock-only” logging fields
  • clock_mode, ref_source, lock_state, holdover_state, holdover_entry_reason.
  • temp_summary, rail_ripple_summary, load_state.
  • banded_jitter_summary, top_spurs_list, mask_margin_summary.
Diagram: Three-stage gate flow (deliverables + evidence lane)
Design gate Bring-up gate Production gate clock tree + node IDs power/return constraints layout “must-pass” list banded jitter profile spur ledger + windows mask margin + holdover station profile ID limits X (margin/spurs) logs for traceability Evidence lane (mandatory IDs) node ID profile / window ID Pass criteria X (frozen)

H2-12 · Applications & IC Selection (Clock/Jitter-only)

Applications are grouped only by clock/jitter requirements and acceptance criteria. Component examples include concrete part numbers for quick shortlisting without turning this page into a catalog.
Scope guard (to prevent cross-page overlap)
  • Included: timebase stability, jitter masks, holdover behavior, clock-tree choices, measurement nodes, Pass X.
  • Excluded: TSN schedule tables, PTP topology calibration procedures, PROFINET/EtherCAT stack details (link only elsewhere).
Application buckets (clock/jitter requirements + how to verify)
Bucket A · TSN motion / deterministic control
  • Clock requirement: stable timebase + repeatable holdover entry/exit; low spur content in sensitive bands.
  • Verify: banded jitter (profile ID) + top spurs list + holdover events under temp/load/supply disturbance.
  • Example parts (shortlist): Jitter attenuator / synchronizer: Renesas 8A34001; Microchip ZL30732A; Jitter cleaner: TI LMK04828; Skyworks Si5345. Rail LDO (clock): ADI LT3042; TI TPS7A47.
Bucket B · High-speed imaging / trigger accuracy
  • Clock requirement: spur discipline + low integrated jitter in ADC/DAC-sensitive bands; clean distribution.
  • Verify: spur ledger (window ID) + banded jitter + correlation of spur tones to system artifacts.
  • Example parts (shortlist): Clock distribution: ADI HMC7044; TI LMK00304. Fanout buffer: TI LMK1C1104; TI CDCLVC1102. Oscillator (examples): SiTime SiT5156; Microchip DSC1123; Abracon ASFL1.
Bucket C · Gateway / edge compute
  • Clock requirement: multi-domain isolation; deterministic clock mode switching without unexpected spurs.
  • Verify: mode-change test (clock source switching) + banded jitter delta + log field completeness.
  • Example parts (shortlist): Network synchronizer: Renesas 8A34001; Microchip ZL30732A. Jitter attenuator: Skyworks Si5345. Fanout / distribution: TI LMK1C1104; Renesas/IDT 5PB1108.
Bucket D · Remote I/O over long media (SPE/PoDL environments)
  • Clock requirement: resilience to supply ripple and EMI-coupled spur injection; robust holdover thresholds.
  • Verify: ripple injection + temperature sweep + recovered-clock vs local-oscillator comparison (same profile ID).
  • Example parts (shortlist): Cleaner / attenuator: Skyworks Si5345; TI LMK04828. Rail LDO (clock): ADI LT3045; TI TPS7A20. Oscillator (examples): SiTime SiT5156; Abracon ASFL1.
Selection logic (requirements → fields → component class → acceptance tests)
Step 1 · Translate requirements into comparable fields
  • PTP accuracy driven: timebase short-term noise + stability; holdover behavior consistency; spur discipline.
  • SyncE template driven: mask margin vs band; cleaner loop BW; wander transfer; lock/holdover transitions.
  • ADC/DAC coupling driven: integrated jitter in sensitive bands; spur list control; distribution additive jitter.
Step 2 · Pick a component class (with concrete examples)
  • Oscillator (reference source): SiTime SiT5156; Microchip DSC1123; Abracon ASFL1.
  • Jitter attenuator / network synchronizer: Renesas 8A34001; Microchip ZL30732A; Skyworks Si5345.
  • Clock distribution / fanout: ADI HMC7044; TI LMK00304; TI LMK1C1104; TI CDCLVC1102; Renesas/IDT 5PB1108.
  • Clock-rail LDO (spur containment): ADI LT3042; ADI LT3045; TI TPS7A47; TI TPS7A20.
Step 3 · Bind every field to a verification method
  • Measurement node: osc_out / cleaner_out / recovered_out / fanout_out (node ID required).
  • Profile discipline: banded jitter profile ID + spur window ID (repeatable settings).
  • Pass criteria: mask margin ≥ X; integrated jitter ≤ X; spur thresholds ≤ X; holdover stability within X.
Minimum viable selection fields (copyable template)
  • Oscillator: stability form, phase-noise anchors, aging note, startup/settling note.
  • Cleaner/PLL: loop BW, attenuation vs freq, wander transfer, lock time, holdover mode, mode-switch behavior.
  • Buffer/fanout: additive jitter, isolation boundary, output standards, power-supply sensitivity note.
  • Acceptance: measurement nodes, profile IDs, window IDs, Pass X thresholds, corner sweep plan.
Diagram: Clocking selection decision tree (requirements → fields → component class → tests)
Requirements PTP accuracy SyncE templates ADC/DAC coupling Required fields timebase noise / stability mask margin / loop BW spur ledger / banded jitter Component class Oscillator Cleaner / SyncE / DPLL Buffer / Distribution Acceptance tests (frozen profiles + Pass X) banded jitter (profile ID) spur ledger (window ID) mask margin ≥ X holdover behavior within X corner sweeps: temperature + supply ripple + load states

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H2-13 · FAQs (Field Troubleshooting, Clock/Jitter-only)

Scope: only long-tail field troubleshooting related to PTP accuracy, SyncE jitter templates, and ADC/DAC clock coupling. Format rule: each answer is exactly four lines — Likely cause / Quick check / Fix / Pass criteria (threshold placeholder X).
Phase noise looks better, but PTP offset still drifts — first correlation check?
Likely cause: metric/window mismatch (offset window ≠ jitter window) or the measured node is not the servo timebase.
Quick check: align time windows + profile IDs, then correlate offset drift vs banded-jitter delta and top-spur amplitude at the same node ID.
Fix: freeze a single measurement node for “servo timebase,” standardize windowing, and move jitter capture to the same clock domain used by timestamp/servo.
Pass criteria: offset drift ≤ X ns over Y min with a fixed window ID, and drift shows no correlation with banded jitter/top spurs within the same capture window.
Offset is stable at idle, but drifts under traffic — clock noise or timestamp path instability?
Likely cause: traffic-dependent capture latency variation (still a clock-path stability problem) or rail/ground noise coupling into the timestamp clock domain.
Quick check: compare banded jitter + spur ledger between “idle” and “load state” at the timestamp clock node; check for load-locked spur tones or jitter band inflation.
Fix: isolate timestamp timebase rail (clock-LDO / filtering), tighten clock-domain isolation, and freeze the traffic state used for acceptance measurements.
Pass criteria: offset statistics remain within X ns across defined load states, and banded jitter change between states is ≤ X (same node + profile ID).
Offset jumps after switching clock modes (GNSS/SyncE/holdover) — what is most suspicious?
Likely cause: holdover entry/exit transient, loop bandwidth reconfiguration, or a mode switch that changes phase/frequency without a controlled phase-continuity policy.
Quick check: log mode-switch timestamps and compare “pre/post” phase noise + spur ledger at the same output node; look for a step change or new modulation spurs.
Fix: enforce a single switching policy (phase-continuous if required), tune loop BW for stable transitions, and gate PTP acceptance to “lock-stable” state.
Pass criteria: post-switch settling time ≤ X s, offset step ≤ X ns, and spur/jitter profile returns to within X of baseline after settling.
Retimer/cleaner changed and the absolute offset shifted — deterministic latency or timebase scaling?
Likely cause: deterministic latency change in the clock/timestamp path or an unintended divider/ratio change in the timebase chain.
Quick check: compare the timebase frequency/ratio at the timestamp clock node, and check whether the offset shift is constant (step-like) across temperature and load states.
Fix: freeze divider ratios and clock-tree node IDs, and treat any constant offset shift as a calibration/latency alignment artifact (kept separate from jitter/accuracy drift).
Pass criteria: offset shift remains within X ns across temp/load corners after alignment, and drift slope stays within X ns/min under the same measurement window.
SyncE mask fails only at hot — holdover drift or supply spur injection?
Likely cause: temperature-dependent oscillator/PLL behavior (holdover accuracy or loop stability) or hot-only rail ripple creating mask-violating spurs.
Quick check: at hot, compare spur ledger vs room; if failures concentrate at discrete tones, suspect rail/EMI spur injection; if broadband margin collapses, suspect loop/holdover drift.
Fix: harden the clock rail (low-noise LDO/filtering), tighten thermal placement/airflow for the clock island, and constrain loop BW/holdover mode for hot corners.
Pass criteria: mask margin ≥ X across required bands at hot corner, and hot-induced spur amplitude stays below X dBc at the defined measurement node.
SyncE mask fails only in one band — loop BW mismatch or measurement bandwidth mismatch?
Likely cause: loop BW placed such that the “transition region” inflates jitter in one band, or the instrument integration bandwidth/window is not the template’s required definition.
Quick check: re-run the mask test with the frozen profile ID (bandwidth + window), then sweep a controlled loop BW setting and observe whether the failing band tracks the BW change.
Fix: standardize the measurement profile (no ad-hoc RBW/VBW), then retune loop BW/attenuation so the failing band gains margin without violating adjacent bands.
Pass criteria: all required bands pass with margin ≥ X under the frozen profile ID, and results repeat within X across Y re-runs.
Recovered clock passes at the PHY pin but fails at SoC/FPGA input — what changed?
Likely cause: distribution additive jitter, poor return-path continuity, or supply/ground noise coupling introduced after the measurement point.
Quick check: measure banded jitter at multiple nodes (PHY out → buffer out → load pin) with identical settings; identify which hop adds the failing band/jitter.
Fix: replace/retune the fanout stage (lower additive jitter), harden the clock rail for the distribution stage, and restore return-path integrity (no plane cuts under the clock route).
Pass criteria: each hop adds ≤ X additive jitter (per band), and the final load-pin measurement meets mask margin ≥ X using the same profile ID.
ADC SNR is worse than expected — clock jitter budget error or layout coupling?
Likely cause: integrated jitter at the sampling clock node exceeds the budget, or spurs/noise are coupling into sampling edges via power/return/layout.
Quick check: compare measured integrated/banded jitter at the ADC clock pin vs budget; then check whether SNR degradation aligns with discrete spur tones (spur ledger).
Fix: reduce clock spurs (rail cleanup, isolation), tighten clock routing/return, and ensure the measured node is truly the ADC sampling clock pin (not upstream).
Pass criteria: measured sampling-clock jitter ≤ X (defined band/profile) and ADC SNR is within X dB of the budget target at fin=Y under the same test setup.
Spurs appear only when SyncE/PTP is enabled — reference coupling or PLL tracking modulation?
Likely cause: loop tracking introduces phase modulation, or enabling timing features changes internal clock modes/rails and injects periodic tones into refclk.
Quick check: capture spur ledger with timing disabled vs enabled at the same node; identify tones tied to known update/servo rates or switching rails.
Fix: adjust loop BW/attenuation to reduce tracking modulation, and isolate/clean the clock rail to suppress feature-dependent spur injection.
Pass criteria: enabling timing does not introduce new spurs above X dBc, and banded jitter remains within X of the disabled baseline (same node + profile ID).
Using recovered clock for sampling made ENOB worse — what assumption is most often wrong?
Likely cause: recovered clock noise transfer (loop BW) places noise into the sampling-sensitive band, or recovered clock carries line/EMI-induced spurs not present in a local oscillator.
Quick check: compare sampling performance using recovered vs local oscillator under identical ADC setup; measure banded jitter at the ADC pin for both sources.
Fix: insert a jitter cleaner between recovered clock and ADC/DAC, narrow loop BW as needed, or switch to local oscillator with controlled disciplining strategy.
Pass criteria: ADC ENOB/SNR difference between recovered and reference clock sources is ≤ X, and measured ADC-pin jitter meets the same budget target ≤ X (defined profile/band).
Offset jumps when PoE load changes — return-path coupling into refclk or rail spur injection?
Likely cause: PoE current step disturbs the return path near the clock island, or rail ripple injects spurs into oscillator/PLL supply (appearing as phase modulation).
Quick check: trigger captures on PoE load step and compare spur ledger/timebase jitter before/after; check whether the offset jump aligns with a new spur tone or broadband jitter rise.
Fix: reroute PoE return paths away from the clock zone, enforce continuous reference planes under refclk, and harden the clock rail with low-noise regulation/filtering.
Pass criteria: offset step during load changes ≤ X ns, and PoE-induced spur amplitude at the clock node stays below X dBc with banded jitter delta ≤ X.
Cleaner added but the system got worse — loop BW too wide or wander tracking too aggressive?
Likely cause: the cleaner is tracking upstream noise (BW too wide), or mode/ratio configuration changed and introduced new spurs or phase discontinuities.
Quick check: compare spur ledger + banded jitter at cleaner input vs output; if output mirrors input noise in the sensitive band, BW is effectively “too wide.”
Fix: narrow loop BW / increase attenuation in the sensitive band, lock down dividers/clock modes, and validate phase-continuity behavior during lock/holdover transitions.
Pass criteria: output jitter shows ≥ X attenuation where required, no new spurs above X dBc, and system KPIs (offset/SNR) meet the same Pass X under frozen profiles.
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