• Where time is taken: ingress/egress timestamp points across PHY/PCS/MAC/DMA stages.
• How time is delivered: timestamp queues, descriptors, interrupts, mapping keys, and overflow behavior.
• How time is used: one-step/two-step field updates, correctionField/residence-time relationship, and E2E vs P2P hook requirements.
• What limits accuracy: quantization, jitter, queue sensitivity, domain crossings, and asymmetry (defined as error sources, not servo algorithms).

• SyncE jitter templates and holdover loop design.
• White Rabbit sub-ns calibration and bi-directional frequency lock details.
• TSN scheduling (Qbv/Qci/GCL parameterization and time-slot tables).
• Industrial stacks (PROFINET/EtherCAT/CIP) implementation and certification internals.
• Protection co-design (TVS/CMC/surge return paths) device-level selection and layout recipes.
• Security (MACsec/DTLS/TLS) key flows and cryptographic plumbing.

• Transport: PTP event messages run over L2 Ethernet or UDP (IPv4/IPv6). Matching rules must reflect the actual transport.
• Timestamp source: timestamps are generated at a defined hardware stage (PHY/PCS/MAC/DMA) and delivered via a deterministic driver interface.
• Time base: a PHC/TSU timecounter exists with known resolution and stable increment behavior (time alignment method is treated as a separate concern).
• Network elements: boundary/transparent clocks may exist; this page only uses their effects on correction and residency, not their full control-plane behavior.

• End-to-end time error: offset ≤ ±X ns over a Y-second evaluation window (define window and statistic upfront).
• Device timestamp jitter: RMS timestamp jitter < X ns (measured at the hardware delivery interface, not at user-space capture time).
• Reliability: missing timestamp rate < X per 10⁶ event packets; timestamp queue overflow = 0 in steady state.
• Metric definitions: offset/delay/wander must declare sampling window, aggregation (RMS/peak/p95), and time base used for comparisons.

• Closer to the wire (PHY/PCS): less queue sensitivity and fewer software-induced delays, typically tighter determinism.
• Closer to the CPU (DMA/driver): delivery is easier to implement, but queueing, batching, and backpressure can inflate variation.
• Engineering rule: choose a timestamp point that stays stable under worst-case traffic, not just in an idle lab capture.

• Ingress (RX): time is taken when a frame crosses a selected boundary (PHY/PCS/MAC). The main risk is losing the timestamp on the way out (queue overflow or mapping loss).
• Egress (TX): time is taken when a frame leaves a selected boundary. The main risk is variable queueing before the stamp point, plus conflicts with offloads that modify the frame.
• Consistency gate: the stamp point must be declared and held constant across builds, tests, and field captures.

1. Time base (PHC): resolution and increment behavior are known; reading PHC is distinct from reading system time.
2. Match point (TSU): event packets are correctly classified (L2 EtherType or UDP port; VLAN/IPv6 awareness if used).
3. Delivery (interface): timestamps are exported via queue/descriptor/IRQ with a stable mapping key and defined overflow behavior.

• Event messages require hardware timestamps because they define the timing events (typical: Sync, Delay_Req).
• General messages usually carry complementary data and primarily require correct association (typical: Follow_Up, Delay_Resp, optional Delay_Resp_Follow_Up).
• Verification rule: if an event packet is observed on the wire, the platform must prove a matching timestamp was captured and delivered without ambiguity.

• t1: Master TX timestamp of Sync at the chosen egress capture point.
• t2: Slave RX timestamp of Sync at the chosen ingress capture point.
• t3: Slave TX timestamp of Delay_Req at the chosen egress capture point.
• t4: Master RX timestamp of Delay_Req at the chosen ingress capture point.

• Hook correctness: event packets must hit the hardware filter with the intended transport and domain.
• Capture correctness: each required t-value must be taken at the declared ingress/egress point (PHY/PCS/MAC).
• Delivery correctness: timestamps must be exported through queue/descriptor/IRQ without loss under load.
• Association correctness: timestamps and related general messages must be mapped using stable keys (sequenceId + domain + port + direction).

• What changes: the TX datapath rewrites timing fields (precise timestamp / correctionField) before the frame is finalized.
• Hard requirement: rewrite must occur with deterministic latency and before link-layer finalization (CRC/FCS generation).
• Compatibility gate: checksum/segmentation offloads must not conflict with the rewrite point and update order.

• What changes: Sync is sent first, then Follow_Up carries the precise origin timestamp derived from the TX timestamp.
• Hard requirement: TX timestamp must be exported reliably and associated to the correct Sync instance.
• Failure mode: queue overflow, reordering, or weak mapping keys cause incorrect associations even when packets are present on the wire.

• Checksum offload conflict: one-step rewrite order vs checksum/TSO path produces sporadic integrity errors or inconsistent fields.
• Cut-through datapaths: field updates and residence accounting must remain consistent across different forwarding behaviors.
• Follow_Up mapping loss: Sync count ≠ Follow_Up count, or TX timestamp count ≠ Sync count under load.

• Primary requirement: required event timestamps are never missing (capture + delivery remain lossless under load).
• Consistency requirement: ingress/egress capture points remain stable across link speed, VLAN mode, and traffic class.
• Mapping requirement: TX timestamps associate to the correct packet instance (sequenceId + domain + direction).

• Port-scoped timestamps: each port must maintain independent ingress/egress timestamp integrity.
• Mapping scope expands: mapping keys must include port identity to prevent cross-port mis-association.
• Re-timestamp / re-send paths: egress timestamp capture must remain on the actual transmit path used under load.

• Must measure: ingress event timestamp and egress event timestamp for the same packet instance.
• Residence time: Δt = (egress TS − ingress TS) under the declared capture-point definition.
• Correction update: correctionField must be incremented consistently using Δt, without breaking integrity checks or association.

• Core exchange: Delay_Req / Delay_Resp (event timing must be captured reliably).
• Required event TS: endpoint TX/RX timestamps that complete the E2E timing set (t3/t4 in addition to Sync path).
• PDV reality: delay variation is observed as jittery measurements; the requirement here is consistent timestamp capture and export, not filtering theory.

• Core exchange: Pdelay_* messages (peer delay relies on timestamps at each hop).
• Hardware dependency: switches/bridges often must support hop-level timestamping and stable correction accounting.
• Correction coupling: peer delay and residence time are both timestamp-defined; inconsistent capture points create non-physical corrections.

• Capability-gated choice: if a hop cannot provide the required peer-delay/timestamp features, prefer an E2E-valid configuration over a partially-verifiable P2P path.
• Consistency first: avoid mixing incompatible correction definitions along a single critical path.
• Observability priority: choose the mechanism with the strongest counters and timestamp visibility under worst-case load.

• Gate A — Timestamp completeness: no missing event timestamps (Delay_* or Pdelay_*), even during bursts.
• Gate B — Association integrity: sequenceId/domain/port mapping does not reorder or mix streams.
• Gate C — Correction stability: correction increments remain consistent for a stable configuration (no unexplained load-coupled jumps).

• Resolution & increment: the tick/increment definition sets the quantization floor and determines wrap/rollover behavior.
• Timescale alignment: capability to represent and align timescale (TAI/UTC) matters for system-wide consistency.
• Step vs slew support: step changes risk discontinuities; slew support enables controlled rate adjustments without breaking monotonic time.
• Capture I/O (if available): PPS in/out or capture pins are only useful when they share the same PHC domain and are documented with clear latency/precision.

• Match rules: EtherType, UDP ports (319/320), VLAN tags/PCP, and L2/L3 mode selection define which frames become timestamp events.
• Capture point: MAC/PCS/PHY-side capture determines the best-achievable precision and the sensitivity to queueing.
• Event indexing: sequenceId/domain/port identity must be available to correlate captured timestamps back to the correct packet instance.

• Typical domains: PHY/PCS, MAC, TSU/PHC, bus/DMA, and CPU/driver domains can differ.
• CDC effect: the risk is not just added latency, but latency variation through async FIFOs, arbitration, and bus contention.
• Correlation checks: timestamp delivery jitter that grows with CPU load or DMA traffic indicates CDC/bus-pressure coupling.

• Gate A — Match hits: TSU hit counters scale with the intended PTP event rate; miss counters remain explained (e.g., non-PTP traffic).
• Gate B — No missing timestamps: event TS missing < X per 10⁶ events (placeholder).
• Gate C — No association errors: mapping misses/reorders remain < X per 10⁶ events (placeholder).
• Gate D — Stress stability: under CPU/DMA load and VLAN/priority changes, counters remain stable and no overflows occur.

• Set by PHC increment and timestamp format.
• Dominates when resolution is coarse relative to the target offset requirement.
• Mitigation: higher-resolution timebase, closer-to-line capture point, or better PHC granularity.

• Introduced by capture-point uncertainty, CDC, arbitration, and internal pipeline variability.
• Dominates when jitter grows with load, DMA pressure, or multi-queue activity.
• Mitigation: consistent capture point, reduce CDC hops, isolate traffic classes, and validate under stress conditions.

• May not change the timestamp value, but can cause missing timestamps or wrong association.
• Dominates when event queues near full, overflows occur, or batching increases association misses.
• Mitigation: sufficient queue depth, conservative batching, deterministic mapping keys, and robust counters.

• Caused by non-identical TX/RX paths, media differences, and PHY internal delay asymmetry.
• Dominates when offset shows stable bias rather than noise, especially across media or cable types.
• Mitigation: explicit calibration/accounting boundaries and consistent physical configurations for validation.

• Occurs when ingress/egress capture points are inconsistent, or forwarding paths change under load.
• Dominates when correction increments vary strongly with traffic load in an otherwise static configuration.
• Mitigation: explicit capture-point definition, stable forwarding behavior, and correction increment distribution checks.

One-step requires deterministic on-wire field updates at transmit time. Offloads can shift where checksums/segmentation occur, creating invisible mismatches between “what software thinks it sent” and “what actually went on the wire.”

First check: compare TSU “TX event captured” counters with the expected Sync rate; then validate association correctness under identical traffic with offloads toggled.

• Common pitfall: the TSU parser matches EtherType/UDP ports, but VLAN insertion (or QinQ double tags) changes parsing expectations and breaks match rules.
• First check: TSU hit/miss counters must track the known PTP event rate; test “no VLAN → single VLAN → QinQ” to isolate parsing gaps.
• Fix principle: explicitly cover VLAN presence and QinQ presence in match rules; keep PTP traffic VLAN/PCP consistent with QoS policy and validate across all intended tag modes.
• Pass criteria: hit counter slope remains linear vs event rate; miss counters are explainable (non-PTP traffic) and stable.

• Observable behavior: store-and-forward tends to add latency with more stability; cut-through reduces latency but often increases sensitivity to congestion and internal arbitration.
• First check: under controlled load sweeps, monitor correction increment distribution width and timestamp jitter p99/p999.
• Fix principle: treat congestion as a mandatory validation scenario; verify tails, not only averages.

• Common pitfall: association keys do not include enough identity (port + domain + sequence), causing timestamps to “cross” between ports or domains.
• First check: ability to break counters per port and per domain; association misses/reorders should cluster to the problematic port if isolation exists.
• Fix principle: isolate event queues per port when supported; ensure mapping keys include at least port identity and sequenceId, and keep domain separation explicit.
• Pass criteria: per-port missing and map-miss counters remain < X per 10⁶ events (placeholder).

• Completeness: RX/TX event timestamps present; missing < X per 10⁶ events.
• Association: sequence-based mapping stable; map-miss/reorder < X per 10⁶.
• Classification: hit counters track known event rate under L2 and UDP modes (as applicable).

• Two-device exchange: fixed roles; evaluate offset using declared statistics (RMS/p99/peak-to-peak) over a declared window.
• PPS/ToD alignment: verify PHC alignment behavior and stability trends (capability/consistency, not servo tuning).
• Interval checks: validate that timestamp intervals match expected periodicity and that the quantization floor is visible in quiet runs.

• Load sweep: 10% → 50% → 90% → congestion (placeholder) while tracking p99/p999 jitter and queue watermarks.
• Counter focus: near-full, overflow, late delivery, map-miss, reorder—record together with throughput and CPU/DMA pressure.
• Pass criteria: tails remain within X ns (placeholder) and missing/overflow remain 0 (or < X).

• Temperature: low/room/high sweeps while tracking PHC stability trend and missing rate.
• Power disturbance: ripple/transients (principle-level) while monitoring overflow and late delivery counters.
• Production minimal set: select a small scenario set that triggers known failure modes (VLAN, batching, burst, thermal).

Industrial control loop (determinism-first)

• What matters: low timestamp jitter tails under load.
• Must-have: deep event queue + overflow counters + stable association.
• Verify: p99/p999 jitter within X; overflow=0 at target throughput.

Power / grid sync (continuity + stability)

• What matters: PHC continuity (step/slew behavior) and clean observability.
• Must-have: clear PHC controls + capture hooks (optional PPS/ToD) + robust logging.
• Verify: holdover/step events recorded; drift bounded within X over Y.

Gateway / switch / multi-port (BC/TC aware)

• What matters: per-port timestamp domains + residence/correction correctness.
• Must-have: per-port event handling + stable port identity + TC/BC hooks.
• Verify: per-hop correction/residence monotonic; mismatch ≤ X/hr.